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2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)

Design of a 4-6GHz Wideband LNA in 0.13m


CMOS Technology
Sana Arshad*, Faiza Zafar and Qamar-ul Wahab
Department of Electronic Engineering
NED University of Engineering & Technology
Karachi-75270, Pakistan
*sana@neduet.edu.pk
input of the amplifier form low pass filter with the resistor and,
thus, degrade the response at high frequencies.
In this paper, we present the design of a wideband LNA
employing reactive elements similar to narrowband design to
achieve wideband input and output impedance matching. The
conventional cascode architecture has been used in
combination with reactive input network. Cascaded CS and
CG stages provide high gain and help in suppressing the
Miller effect, thereby, rendering a better reverse isolation. A
second cascode stage is also added to further increase the gain.
The conventional LNAs use a buffer for output impedance
matching (for measurement purpose) which degrades the gain
of the core LNA and increases power consumption. In our
design, the use of RLC combination at the output provides
wideband matching without trading-off the gain and power
consumption. A similar strategy has also been employed in [8]
for output impedance matching at the cost of gain.
The organisation of the paper is as follows. The wideband
LNA design theory is explained in Section II. Section III
discusses the layout of the LNA and post layout simulation
results are presented in Section IV. Finally the paper is
concluded in Section V.

Abstract This paper presents the design of a single ended


wideband LNA utilizing reactive elements at the input and
output for impedance matching. It has been shown through
simulations that the LNA architecture utilizes components
similar to a narrowband design but achieves a much wider
bandwidth with high gain and low noise figure. The single ended
wideband LNA is based on 0.13-m CMOS technology from IBM
and simulated in Cadence SpectreRF. The LNA operates for
frequencies approximately between 4-6 GHz. The maximum gain
of the LNA is 29.6 dB and average NF is 2.6 dB. The linearity
analysis shows the input referred P1dB and IIP3 of -25.07 dBm
and -13.47 dBm respectively. The two stage wideband LNA
consumes only 13.9 mA from a 1.5 V supply. It shows good
comparison with other LNAs designed for 4-6 GHz range with a
much higher gain and smaller NF.

I.

INTRODUCTION

With the emergence of various communication standards,


the need for low cost and reconfigurable/wideband receiver
units is indispensable. The reconfigurable receivers usually
employ inductors for tuning to a specific frequency band and,
thus, occupy large area [1]-[3]. Wideband receivers have
gained significant popularity during the past two decades since
they not only provide the flexibility of operation at various
frequencies simultaneously but can be made even without
inductors [4]-[5].
The low noise amplifier (LNA) is the main and first active
block in any receiver. The performance metrics of a wideband
LNA are very critical compared to narrowband design.
Achieving high and flat gain with low noise figure (NF) is the
never-ending demand. This in conjunction with high linearity
and small power consumption makes the LNA design very
challenging. Several topologies for wideband LNAs have been
reported in literature, each trading off some parameter with the
other. The Distributed amplifiers are known for their large
bandwidth but the gain is relatively small. The large area of
inductors limits their use in some applications, although NF
reduction techniques for distributed amplifiers have already
been proposed [6]. The Common Gate (CG) and resistive
feedback topologies are other ways of achieving wideband
behaviour but the former suffers from large NFmin and the
latter restricts the bandwidth to lower frequencies. The large
NF of CG LNA was worked out in [7] but NF could not go
below 2.5 dB. The resistive feedback topology suffers from
reduced bandwidth because the parasitic capacitances at the

978-1-4673-2163-1/12/$31.00 2012 IEEE

II. THEORY AND ANALYSIS


In an LNA design, we need to optimize various
parameters such as gain, input and output impedances, NF,
linearity and power consumption. The source impedance for
good power match differs from the one at which noise figure
is optimum [9]. Besides, there is an inverse relation between
gain and linearity of the LNA whereas power consumption
and linearity varies linearly with each other. It is apparent
from the above discussion that performance parameters of an
LNA are inter-related; therefore, optimizing one, degrades the
other. Hence, designing an LNA includes optimization of all
of them or applying any technique to break the trade-off
between these quantities. It is almost impossible to achieve a
good LNA design just by altering the gate width and effective
gate voltages of the transistors [10].
Fig. 1 shows the schematic of our wideband LNA. In
general, a common source (CS) amplifier with a degeneration
inductor offers a narrowband impedance matching inherently.
The generalized expression for the input impedance of a
degenerated CS transistor can be expressed as:

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2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)

are added for stability and also help in achieving a high gain.
Besides, resistor R4 also helps in output impedance matching.
It is a very common practice to design an LNA with a
buffer at output for output impedance matching during LNA
measurement. However, this buffer degrades the gain of core
LNA since the buffer gain is smaller than 1. In addition to gain
reduction, the buffer also consumes extra power. Taking this
fact into account we have utilized a series LC combination for
output matching as well. The desired wideband impedance
match is achieved through the combined impedance of C4, L4,
R4 and L5.
The high gain of the LNA is primarily because of the two
gain stages as shown in Fig. 1. However, the power
consumption is still comparable to single stage designs [11].
The overall voltage gain is obtained by evaluating the gain of
each stage of LNA individually and multiplying them together.

VDD

R2

R4

R3

L3

L4

M3

M5

M2

R1

RFIN L1

Stage 1

L5

RFOUT

C3
M4

M1
C1

C4

C2
L2

RBIAS
Vbias

Stage 2

Figure 1. The 4-6 GHz Wideband LNA

(1)

(3)

In our design, a series combination of inductor (L1) and


capacitor (C2) is added before the degenerated cascode pair.
As the input impedance of the LNA has a reactive part, the L1,
L2, C1 and C2 combination helps in resonating this reactive
part over multiple frequencies within the band of interest, thus,
providing larger bandwidth. The capacitor, C2, in parallel with
Cgs of M1 also helps to further increase the bandwidth. An
approximate analysis for the input impedance of the LNA
gives Zin as

where Av1 and Av2 are the gains of first and second stage
respectively. The individual voltage gains are calculated by
the method presented in [12] as follows:
(4)
(5)
where Gm1, Rout1 and Gm2, Rout2 are the transconductances and
output impedances of the first and second stage respectively.
Approximate analysis using the method mentioned above
renders (6) (9). It should be noted that Rout2 is also the total
output impedance of our LNA.
The stability of LNA is estimated through Rollett's Stability
criteria (K factor and ) given by (10) and (11) [13]. In our
design, all critical resistors, inductors and capacitors are
adjusted for stability rendering an unconditionally stable
frequency response for the LNA.

(2)
The biasing of the main transistor, M1, is carried out by
means of a current mirror, M3, whereas the cascoded
transistor M2 is biased directly through the Vdd supply. The
use of a cascode pair provides a high gain with good reverse
isolation. To further increase the gain, a second cascode stage
is added. Additionally, this stage totally isolates the input and
output matching of the LNA. Inductors, L3 and L4, at the
drain are placed to provide exact supply voltage values to the
drain of the transistors, M2 and M5. The resistors, R3 and R4,

(10)
Where
(11

(6)
(7)
(8)
(9)

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2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)

For achieving stability through the Rollett's Stability Criterion,


the K 1 shall be met in combination with 0 < B1 < 1 where
(12)
The simulated K factor and B1f values for our LNA are
presented in section IV.
In our two staged wideband LNA, total NF is dominated by
the NF of first stage. Also, the higher the gain of the first stage,
the smaller will be the noise contribution of the next stage.
This is in accordance with the Friis formula for finding the NF
of the cascaded stages as in (13) [14].
(13)
Where F is the total noise factor, F1 and F2 are the noise
factors of first and second stage respectively and G1 is the first
stage gain. The drain current noise, gate induced noise from
the cascode stage (M1 and M2) and thermal noise from the
resistor are the major noise contributors since the effect of
second stage noise factor will be smaller due to high gain of
the first stage. For input impedance matching at which both
NF and power match are optimum, we obtain a minimum NF
of 1.9 dB in the passband.
III. LAYOUT DESIGN
Cadence Virtuoso Layout XL is used for designing the
LNA layout. Physical verification checks including DRC,
LVS, and QRC have been successfully performed using
Assura 1.8.0.1DM. The LNA is designed using standard 1.5 V
thin oxide transistors. On-chip MIM capacitors and parallel
spiral inductors are used for the design. The maximum and
minimum values of inductors used are 4.25 nH and 1.07 nH
respectively.
After complete layout design, post-layout simulations were
performed to check the effects of parasitics on LNA results.
The track widths were then adjusted to keep both, the parasitic
resistance and capacitance, optimum. This helped to obtain
better NF and bandwidth from the layout as well. Together
with this, large number of transistor fingers also contributed to
a reduced NF. The total area of the chip is 1.26 mm2 whereas
the effective area of layout covers only 0.5 mm2 excluding
bond pads. Fig. 2 shows the layout of the LNA.

transistors to operate well in the saturation region, thereby,


obtaining maximum signal swing through the cascode pairs to
achieve maximum gain. With a power supply of 1.5 V, the
LNA draws only 13.9 mA current.
For a bandwidth nearly equal to 2 GHz (~4-6 GHz), the
simulated input (S11) and output (S22) port reflection
coefficients achieve values better than -10 dB and -5 dB
respectively. The average forward gain (S21) and reverse
isolation (S12) are 25.5 dB and -74.5 dB respectively in the
passband. These parameters are plotted in Fig. 3.
The NF of the LNA is plotted in Fig. 4 which shows a
minimum NF of 1.9 dB at a frequency of 4.1 GHz. The
stability analysis of the LNA indicates both K >1 and B1f < 1
over a large frequency span. This clearly indicates the
unconditional stability of our LNA. Fig. 5 shows the combined
plot of both K and B1f. The linearity analysis is performed
using the two tone test. Since the LNA is wideband in nature,
two tones (5 GHz and 5.01 GHz) with spacing of 10 MHz are
selected. This is to ensure that any intermodulation product
does not oscillate the LNA under any condition. The resulting
third order intermodulation product frequency is identified and
the input power is swept from -40 dBm to 0 dBm. The IIP3
obtained is -13.47 dBm as plotted in Fig. 6. The input referred
P1dB is -25.07 dBm as shown in Fig. 7.
A comparison of our LNA with other state-of-the-art LNAs
of similar frequency range, bandwidth and technology nodes is
presented in Table I. It is apparent that the gain of our LNA is
substantially higher compared to other wideband LNAs with
slight degradation in linearity and power consumption. The
average gain of 25.5 dB is among the best values reported in
0.13-m CMOS technology for 4-6 GHz frequency range with
NF as small as 1.9 dB in the passband.

IV. SIMULATION RESULTS


All simulations of the LNA are performed in Cadence
Spectre RF using IBM 0.13-m CMOS technology. The gate
widths of transistors M1, M2, M4 and M5 are all chosen to be
90-m through simulations. The diode connected transistor
M3 for biasing, is set for a gate width of 3-m. As a result,
bias voltage of 0.65 volts appears at the gate of M1. The gate
voltages of M2, M4 and M5 are 1.5, 0.6 and 1.5 volts
respectively. The selected gate widths and biasing allow the

Figure 2. Layout of the LNA

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2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)

10

Output Power (dBm)

S-Parameters (dB)

40
30
20

S11

S21

S22

10
0
-10
-20
-30
2

Frequency (GHz)

Noise Figure (dB)

-5

1dB/dB

-10

-35

-30

-25

-20

-15

Input Power (dBm)

-10

-5

Figure 7. Input referred 1 dB Compression Point


(P1dB= -25.07 dBm)

TABLE I. COMPARSION OF SINGLE ENDED CMOS LNAS


3

Ref. No.

4.5

Frequency (GHz)

5.5

2000

1
0.9

B1f

0.8
1000

Kf

0.7

B1f

0.6
0
2

0.5
7

Frequency (GHz)

0
1dB/dB
3dB/dB

-40
-60
-80
-40

-35

-30

-25

-20

-15

Input Power (dBm)

-10

-5

[17]

[18]

This
work
0.13
< -10
< -5
25.51
1.92
-25.07
20.9
~4-6

A wideband LNA in the range 4-6 GHz has been designed


in IBM 0.13-m CMOS technology. The wideband operation
is achieved by using RLC networks both at the input and
output. The two staged cascaded cascode topology provides
high gain. The post layout simulation results depict forward
gain as high as 29.6 dB and NF as low as 1.9 dB in the
passband. The simulated input referred P1dB and IIP3 are 25.07 dBm and -13.47 dBm respectively. The two staged LNA
consumes only 13.9 mA from a 1.5 V supply. Input and output
impedances are matched to 50 with reverse isolation of 74.5 dB. The results show that our simulated LNA is similar in
performance to other wideband LNAs designed in this range
but with a much higher gain and better NF. The summary of
the results is presented in Table II.

IIP3= -13.47 dBm

-20

[16]

V. CONCLUSION

Figure 5. Stability factors K and B1f

20

[15]

0.18
0.18
0.18
0.18
Tech
(m)
< -10.5
<-9.9
<-.94
<-11
S11
(dB)
< -13.1
<-9.9
<-9.6
<-10
S22
(dB)
<16
<10
<17
12.1
S21
(dB)
2.2max
9
2.25
3.52
NF
(dB)
-23
P1dB
(dBm)
7.68
9
12.1
11.1
Power
Consumption
(mW)
3-5
2.3-9.2
4-6
0.7-6.5
Frequency
(GHz)
1
Avg. in passband 2Min. in passband

Figure 4. Simulated NF (NF= 1.9 dB at 4.1GHz)

Kf

Input referred P 1dB= -25.07 dBm

NF

Output Power (dBm)

-15
-40

Figure 3. Simulated S-Parameters

Figure 6. IIP3 of the LNA (IIP3= -13.47 dBm)

128

2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)

TABLE II.

SUMMARY OF RESULTS

S11
S21
S22
Input referred P1dB
IIP3
NFmin
Power Consumption
Bandwidth
1Avg.

[18] J. Hu, Y. Zhu, and H. Wu, "An Ultra-Wideband Resistive-Feedback


Low-Noise Amplifier with Noise Cancellation in 0.18m Digital
CMOS", IEEE Topical Meeting on Silicon Monolithic Integrated
Circuits, 2008.

<-10 dB
25.5 dB1
-5 dB
-25.07 dBm
-13.47 dBm
1.9 dB
20.9 mW
2 GHz (4-6 GHz)

ACKNOWLEDGEMENT
The authors would like to thank High Performance
Computing Centre, NED University of Engineering &
Technology, for the technical support and other facilities.
REFERENCES
[1]
[2]

[3]
[4]
[5]

[6]
[7]

[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]

N. Ahsan, A. Ouacha, J. Dabrowski and C. Samuelsson Dual band


Tunable LNA for Flexible RF Front-End, International Bhurban
Conference on Applied Sciences & Technology, pp 19-22, January 2007.
K. Datta, R. Datta, A. Dutta, T.K. Bhattacharyya, PSO based Output
Matching Network for Concurrent Dual-Band LNA, IEEE
International Conference on Microwave and Millimeter Wave
Technology, May 2010.
H. Hashemi and A. Hajimiri, Concurrent multiband low-noise
amplifiersTheory, design, and applications, IEEE Trans. Microwave
Theory Tech., vol. 50, pp. 288301, Jan. 2002.
R. Ramzan, S. Andersson, J. Dabrowski, C. Svensson, " A 1.4V 25mW
Inductorless Wideband LNA in 0.13m CMOS", IEEE International
Solid State Circuits Conference, pp.424-425, June, 2007.
H. Wang, L. Zhang, and Z. Yu, A wideband inductorless LNA with
local feedback and noise cancelling for low-power low-voltage
applications, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 8,
Aug. 2010.
K. Moez and M.I. Elmasry, A low-noise CMOS distributed amplifier
for ultra-wide-band applications, IEEE Trans. Circuits Syst. II: Express
Briefs, 2008, 55, (2), pp. 126130.
J. Kim, S. Hoyos, and J. Martinez, Wideband common-gate CMOS
LNA employing dual negative feedback with simultaneous noise, gain,
and bandwidth optimization, IEEE Trans. On Micr. Theory and Tech.,
vol. 58, no. 9, September 2010.
H. J. Lee, D. S. Ha, and S. S. Choi, A 3 to 5 GHz CMOS UWB LNA
with input matching using Miller effect, IEEE Solid-State Circuits
Conf., pp. 731740, February 2006.
T. H. Lee, 5-GHz CMOS wireless LANs, IEEE Trans. Microwave
Theory Tech., vol. 50, pp. 268280, January 2002.
S. Ock, K. Han, J. Ryul Lee and B. Kim, A Modified Cascade Type
Low Noise Amplifier Using Dual Common Source Transistors, IEEE
International Microwave Symposium Digest, pp. 1423 1426, Aug. 2002
M. E. Nozahi, A. A. Helmy, E. S. Sinencio and K. Entesari, "A 2-1100
MHz Wideband Low Noise Amplifier with 1.43 dB minimum Noise
Figure", IEEE Radio Freq. Int. Circuits Symp., pp.119-122, 2010.
B. Razavi, Design of Analog CMOS Integrated Circuits, Edition 2002.
S. Kassim, F. Malek, Microwave FET amplifier stability analysis using
Geometrically-Derived Stability Factors, International Conference on
Intelligent and Advanced Systems, pp. 1-5, June 2010.
A. van der Ziel, Noise: Sources, Characterization, Measurement,
Englewood Cliffs, NJ: Prentice-Hall, 1970.
H.J. Lee, Dong. S. H, S. S. Choi, "A 3 to 5GHz CMOS UWB LNA with
Input Matching using Miller Effect", IEEE Solid-State Circuits Conf.,
2006.
A. Bevilacqua, and A. M. Niknejad, An Ultra-Wideband CMOS LNA
for 3.1 to 10.6GHz Wireless Receivers, IEEE Solid-State Circuits
Conf., pp.382, 2004.
T. Yuxiang, C. Wang, "A 4-6GHz Current-Mode Differential
Transconductance Wide Band LNA", IEEE International Conf. on
Control and Engineering, 2011.

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