I.
INTRODUCTION
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2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)
are added for stability and also help in achieving a high gain.
Besides, resistor R4 also helps in output impedance matching.
It is a very common practice to design an LNA with a
buffer at output for output impedance matching during LNA
measurement. However, this buffer degrades the gain of core
LNA since the buffer gain is smaller than 1. In addition to gain
reduction, the buffer also consumes extra power. Taking this
fact into account we have utilized a series LC combination for
output matching as well. The desired wideband impedance
match is achieved through the combined impedance of C4, L4,
R4 and L5.
The high gain of the LNA is primarily because of the two
gain stages as shown in Fig. 1. However, the power
consumption is still comparable to single stage designs [11].
The overall voltage gain is obtained by evaluating the gain of
each stage of LNA individually and multiplying them together.
VDD
R2
R4
R3
L3
L4
M3
M5
M2
R1
RFIN L1
Stage 1
L5
RFOUT
C3
M4
M1
C1
C4
C2
L2
RBIAS
Vbias
Stage 2
(1)
(3)
where Av1 and Av2 are the gains of first and second stage
respectively. The individual voltage gains are calculated by
the method presented in [12] as follows:
(4)
(5)
where Gm1, Rout1 and Gm2, Rout2 are the transconductances and
output impedances of the first and second stage respectively.
Approximate analysis using the method mentioned above
renders (6) (9). It should be noted that Rout2 is also the total
output impedance of our LNA.
The stability of LNA is estimated through Rollett's Stability
criteria (K factor and ) given by (10) and (11) [13]. In our
design, all critical resistors, inductors and capacitors are
adjusted for stability rendering an unconditionally stable
frequency response for the LNA.
(2)
The biasing of the main transistor, M1, is carried out by
means of a current mirror, M3, whereas the cascoded
transistor M2 is biased directly through the Vdd supply. The
use of a cascode pair provides a high gain with good reverse
isolation. To further increase the gain, a second cascode stage
is added. Additionally, this stage totally isolates the input and
output matching of the LNA. Inductors, L3 and L4, at the
drain are placed to provide exact supply voltage values to the
drain of the transistors, M2 and M5. The resistors, R3 and R4,
(10)
Where
(11
(6)
(7)
(8)
(9)
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2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)
127
2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)
10
S-Parameters (dB)
40
30
20
S11
S21
S22
10
0
-10
-20
-30
2
Frequency (GHz)
-5
1dB/dB
-10
-35
-30
-25
-20
-15
-10
-5
Ref. No.
4.5
Frequency (GHz)
5.5
2000
1
0.9
B1f
0.8
1000
Kf
0.7
B1f
0.6
0
2
0.5
7
Frequency (GHz)
0
1dB/dB
3dB/dB
-40
-60
-80
-40
-35
-30
-25
-20
-15
-10
-5
[17]
[18]
This
work
0.13
< -10
< -5
25.51
1.92
-25.07
20.9
~4-6
-20
[16]
V. CONCLUSION
20
[15]
0.18
0.18
0.18
0.18
Tech
(m)
< -10.5
<-9.9
<-.94
<-11
S11
(dB)
< -13.1
<-9.9
<-9.6
<-10
S22
(dB)
<16
<10
<17
12.1
S21
(dB)
2.2max
9
2.25
3.52
NF
(dB)
-23
P1dB
(dBm)
7.68
9
12.1
11.1
Power
Consumption
(mW)
3-5
2.3-9.2
4-6
0.7-6.5
Frequency
(GHz)
1
Avg. in passband 2Min. in passband
Kf
NF
-15
-40
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2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)
TABLE II.
SUMMARY OF RESULTS
S11
S21
S22
Input referred P1dB
IIP3
NFmin
Power Consumption
Bandwidth
1Avg.
<-10 dB
25.5 dB1
-5 dB
-25.07 dBm
-13.47 dBm
1.9 dB
20.9 mW
2 GHz (4-6 GHz)
ACKNOWLEDGEMENT
The authors would like to thank High Performance
Computing Centre, NED University of Engineering &
Technology, for the technical support and other facilities.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
129