OF
EXPERIMENT E1.07
DIFFERENTIAL AMPLIFIER
GROUP E12
GROUP MEMBER
YAP WAI MING
YAP CHIH HSIUNG
PRESENTED BY
YAP CHIH HSIUNG
INTRODUCTION
The input stage of most operational amplifier is a differential amplifier. Its circuit is
shown in Figure 1. The differential amplifier is composed of two emitter-coupled
common-emitter dc amplifiers with two inputs, vi1 and vi2, and three outputs, vo1, vo2,
and vo. vo is the difference between vo1 and vo2. Figure 2 shows the block diagram of a
differential amplifier. Voltages may be applied to either or both input terminals and
output may be taken from either or both output terminals
Figure 1
Figure 2
Objectives
To understand and explain the operation of the differential amplifier as constructed
from discrete components with both symmetrical and unsymmetrical operating voltage.
THEORY
Important Points (Refer to Figure 1)
1.
2.
3.
4.
5.
6.
output.
Single-ended Operation
In Figure 3, input signal vi1 is applied to terminal 1 with terminal 2 grounded. An
amplified and inverted output signal is obtained at terminal 3 but an equally-amplified
and in-phase signal appears across output terminal 4. The output voltage has the
polarity shown in the figure.
Figure 3
Figure 4
As shown in figure 4, when input signal vi2 is applied to input terminal 2, an amplified
and inverted signal appears at output terminal 4, whereas equally-amplified but inphase signal appears at terminal 3.
In summary, input at any of the two terminals causes outputs at both terminals 3 and 4.
the two outputs are opposite in phase but of equal amplitude.
Double-ended Operation
Figure 5 illustrates the double-ended mode of operation when two input signals of
opposite phase are applied to the two input terminals.
Figure 5
Input signal at each input terminal causes signals to appear at both output terminals.
The resultant output signals have a peak value of 2V - twice the value for single-ended
operation. However, if two in-phase and equal signals were applied at the two input
terminals, the resultant output signal at each output terminal would be zero as shown
in Figure 6. It means that output between the collectors would be zero.
Figure 6
If vi1 and vi2 change by exactly the same amount, even then output voltage between
terminals 3 and 4 remains zero because of symmetry. Only when vi1 and vi2 differ from
each other, we get an output voltage. When vi1 is more positive than vi2, the output
terminal 4 is more positive than terminal 3.
Experiment
Differential Amplifier with Asymmetrical Operating Voltage
Circuit
Procedure
1.
Insert the bridging plugs as shown in the circuit diagram. Carry out the offset
adjust: set UB1 to the same value as UB2 using R5. Connect MP3 and MP4
using a measuring lead. Now set UA to as small a voltage as possible (ideally
UA = 0V) with R6. Remove the measuring lead. Determine the values required
to complete table 1.
2.
Starting at the base voltage of transistor V1 (value from table 1) increase and
decrease the voltage UB1 in 100mV steps by varying the value of R5 (table 2).
Determine the values required to complete table 2.
3.
Results
5
1.
The offset adjust is carried out to balance the circuit. The two inputs U B1 and
UB2 are made equal and the circuit is in common-mode.
2.
UB (V)
15.00
UB1 (V)
7.42
UB2 (V)
7.42
UC1 (V)
11.82
UC2 (V)
1.76
UC2 (V)
11.76
12.05
12.41
11.35
11.00
Table 2
4.
5.
Procedure
1.
Carry out the offset adjustment : set UB1 to the same value as UB2 using R5.
Connect MP3 and MP4 using a measuring lead. Now set U A to as a small a
voltage as possible (ideally UA = 0 V) with R6. Remove the measuring lead.
Insert the bridging plugs as shown in the circuit diagram.
2.
Apply a sinusoidal a.c. voltage of 200 mVPP / 1 kHz (Ue1) to the base of V1.
Connect the base of V2 to the reference point. Use the oscilloscope/multimeter
to determine the voltages Ue1, UC1 and UC2 and transfer these to the appropriate
graticule/table 3.
Carry out a new offset adjust. Connect the base of V2 with the base of V1
(MP4 - MP3). Apply a sinusoidal a.c. voltage of 200 mVPP / 1 kHz (Ue1) to the
base of V1. Determine the values required to complete table 3.
Complete the experiment record and the exercises.
3.
4.
Results
1.
ax : 0.2 ms/Div
aY : 50 mV/Div
Ue1 : 200mVPP
f : 1 kHz
2.
ax :
aYA :
aYB :
UC1 :
UC2 :
:
0.2 ms/Div
2 V/Div
2 V/Div
8.9 VPP
7.5 VPP
180
Graticule 2 UC1;UC2
3.
UB1 : 200 mVPP
UB2 : 0 V
UB1 : 200 mVPP
UB2 : 200 mVPP
UC1
8.9 VPP
UC2
7.5 VPP
UA
16.4 VPP
970 mVPP
970 mVPP
0V
Conclusions
1.
2.
10
References
1.
2.
11
Contents
Introduction
Objectives
Theory
Single-ended Operation
Double-ended Operation
Common-mode and Differential-mode
2
3
4
Experiment
5
Differential Amplifier with Asymmetrical Operating Voltage 5
Circuit
Procedure
Results
5
5
6
Conclusions
10
Circuit
Procedure
Results
References
11
12
7
8
8