International Journal of Electronics,

Communication & Instrumentation Engineering

Research and Development (IJECIERD)
ISSN(P): 2249-684X; ISSN(E): 2249-7951
Vol. 4, Issue 6, Dec 2014, 21-28
TJPRC Pvt. Ltd.

RECONFIGURABLE SINGLE PRECISION FLOATING POINT

MULTIPLIER USING REVERSIBLE LOGIC
ARATI B. SUDHAKAR1 & VEENA M. B.2
1

Department of Telecommunication Engineering, Vemana Institute of Technology, Bangalore, Karnataka, India

2

Department of Electronics & Communication, BMSCE, Bangalore, Karnataka, India

ABSTRACT
Now a days Reversible logic has received great attention due to their ability to reduce the power dissipation. It is
the main requirement in low power Very large scale integration (VLSI) design. Using reversible logic circuits Quantum
computers are constructed which has applications in various research areas such as DNA computing, low power CMOS
design, optical computing, nanotechnology bio-informatics, quantum computing, and thermodynamic technology. It is very
difficult to construct quantum circuits without the use of reversible logic gates. Since fan-out and feedback is not allowed
in reversible logic circuits, Synthesis of reversible logic circuits is significantly more complicated than traditional
irreversible logic circuits. There are several reversible logic gates. Some of them are: Taffoli gate, Fredkin gate, Feynmen
gate, Peres gate, etc. These logical gates as well as some derivatives of these gates are explored in this project and will be
used conveniently to design the single precision floating point multiplier to improve its area, speed and power parameters.

KEYWORDS: Reversible Logic, Multiplier Circuit, VLSI

INTRODUCTION
INTRODUCTION TO REVERSIBLE CIRCUITS
In order to implement reversible computation, judge its limits and to estimate its cost, it is formally used in terms
of gate-level circuits. For example, the inverter is reversible because it can be undone. The exclusive or gate is irreversible
since its inputs cannot be unambiguously reconstructed from an output value. However, it is possible to define a reversible
version of the XOR gatethe controlled NOT gate (CNOT) by preserving one of the inputs. The three-input CNOT
gate is called as Toffoli gate, which preserves two of its inputs a, b and replaces the third input c by c. (a . b). With cdot b
= 1 this gives the NOT function, and with c=0, this gives the AND function. Therefore the Toffoli gate is universal and can
be used to implement any reversible Boolean function. Generally, reversible gates have the equal number of inputs and
outputs. The connections of reversible gates without any loops and fanouts are called as a reversible circuit.
Thus, reversible circuits contain same number of input and output wires, each passing through an entire circuit.
In 1960s the reversible logic circuits have been first motivated by considering zero-energy computation as well as
practical improvement of bit-manipulation transforms in cryptography and computer graphics theoretically. Since the
1980s, reversible circuits have attracted interest as components of quantum algorithms, and more recently in photonic and
nano-computing technologies where some switching devices offer no signal gain. Surveys of reversible circuits, their
construction and optimization as well as recent research challenges is available.

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Arati B. Sudhakar & Veena M. B

Fundamentals of Reversible Logic

R. Landauer's research in the early 1960s demonstrated that irreversible hardware computation, regardless of its
realization technique, results in energy dissipation due to the information loss . It is proved that the loss of each one bit of
information dissipates at least KTln2 joules of energy (heat), where K = 1.38x10-23m2kg-2K-1 (joules Kelvin-1) is the
Boltzmanns constant and T is the absolute temperature at which operation is performed . Reversible logic circuits
(or gates) are information lossless. Hence, reversible logic circuits have theoretically zero internal power dissipation. In
1973, Bennett proved that to avoid KTln2 joules of energy dissipation in a circuit, it must be built using reversible logic
gates.
If the input vector can be uniquely determined from the output vector and there is a one-to-one correspondence
between its input and output assignments, then the circuit is said to be reversible i.e. in other words not only the outputs
can be uniquely determined from the inputs but also the inputs can be recovered from the outputs. Therefore, the number of
inputs and outputs in reversible logic circuits, as well in logic gates are equal. Such circuits and gates allow recovering the
inputs from the outputs.
Thus we can say that the reversible circuits are circuits (gates) in which:

The number of input bits is equal to the number of output bits. For example, a circuit with input vector is of length
4 then the output vector length should be 4.

There should be one-to-one correspondence between input and output vectors. None of the two or more than two
input vectors should give the same output vector.

The reversible circuits input vector can always be reconstructed from the output vector.
Toffoli and Fredkin discovered reversible logic in the late 70s and early 80s . Any reversible logic gate can be

characterized by its number of inputs and outputs. A m*n gate has m inputs and n outputs. There are several 2*2 reversible
gates and all of them are linear. A gate is said to be linear when all its outputs are linear functions of input variables.
Implementation of Full-Adder Design Using Reversible Gates
CMOS implementation is the most conventional way to synthesize a logic circuit, hence reversible circuits can
also be constructed using CMOS. We cannot guarantee that the power consumption of reversible logic circuit implemented
using CMOS is less than that of conventional circuit i.e. non-reversible. This is because the power saved by the reversible
circuit is pretty much less compared to the power consumption by any CMOS design. Therefore, in order to make use of
this power saved due to reversibility we need to use the technology that implements logic circuits, so that it would consume
much less power compared to current CMOS technology. For functional testing and for comparing delay and area CMOS
technology can be used.
Three full adders can be constructed using different combination of basic reversible gates i.e. Toffoli, Fredkin and
Feynman gate.

2 Toffoli gates and 2 Feynman gates gives two garbage outputs.

3 Feynman gates and 1 Fredkin gate gives two garbage outputs.

Impact Factor (JCC): 4.9467

Index Copernicus Value (ICV): 3.0

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Reconfigurable Single Precision Floating Point Multiplier Using Reversible Logic

5 Fredkin gates give five garbage outputs.

The full adder shown in figure 1.1 uses 3 Feynman gates and 1 Fredkin gate which have minimum area and

complexity in comparison to above three full adders. As compared to any other reversible full adder, that produces two
garbage outputs, it has minimum number of garbage outputs. For the three distinct input combinations (0, 0, 1), (0, 1, 0)
and (1, 0, 0), the full adder output produces the same output (1, 0). Hence, to separate all the repeated values of outputs S
and Cout we need to have at least two garbage outputs.

Figure 1.1: Full Adder Using 3 Feynman Gate and 1 Fredkin Gate

FLOATING POINT MULTIPLICATION ALGORITHM

Floating point numbers are one possible way of representing real numbers in binary format; the IEEE 754
standard presents two different floating point formats, Binary interchange format and Decimal interchange format.

Figure 2.1: IEEE 754 Format of Representing Single Precision Floating Point Numbers
The algorithm for Floating Point Multiplication consists of the following steps.

Check for zeros, NaN's, inf on inputs.

Add the exponents

Multiply the mantissas

Normalize the product and round using the specified rounding mode. Also generate exceptions.

Figure 2.2: Flow Chart Describing the Single Precision Floating Point Multiplication Algorithm
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Arati B. Sudhakar & Veena M. B

Figure 2.3: Simulation Results Illustrating the Multiplication Operation

REVERSIBLE FULL ADDER IMPLEMENTATION

In order to test the effect of reversible logic in IEEE standard floating point multiplier, we short list the following
reversible logic circuits that are proven to perform well. The full adder is the most important part of a floating point
multiplier and forms about 70% of the logic. Hence, it is best to evaluate the effect of reversible logic by implementing a
reversible full adder. The following reversible full adder implementations are considered for evaluation.
Full Adder Using DKG Gate
A 4* 4 reversible DKG gate shown in figure 3.1.1 can work singly as a reversible Full adder. It is been verified
that input pattern corresponding to a particular output pattern can uniquely be determined. Its implementation as a full
adder is shown in the figure 3.1.2. If we make input A=0, the DKG gate works as a reversible Full adder. It is been seen
that a reversible full-adder circuit has only two garbage outputs to make the output combinations unique, which is the
prime requirement for a reversible circuit. Since the proposed reversible full adder circuit using DKG gate produces two
garbage outputs, so it meets optimization in terms of number of garbage outputs.

Figure 3.1.1: DKG Gate

Figure 3.1.2: A Full-adder Implemented Using DKG Gate

Full-adder Using TSG Gate

The reversible TS Gate is shown in figure 3.2.1. It can be verified that input pattern corresponding to a particular
output pattern can be uniquely determined. The proposed TSG gate is capable of implementing all Boolean functions and
can also work singly as a reversible Full adder. Figure 3.2.2 shows the implementation of the proposed gate as a reversible
Full adder.

Figure 3.2.1: TSG Gate Configuration

Figure 3.2.2: TSG Configured as a Full-adder

Full Adder Using Fredkin Gate

The Fredkin gate (also CSWAP gate) is a computational circuit suitable for reversible computing, invented by Ed

Impact Factor (JCC): 4.9467

Index Copernicus Value (ICV): 3.0

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Reconfigurable Single Precision Floating Point Multiplier Using Reversible Logic

Fredkin. It is universal, which means that any logical or arithmetic operation can be constructed entirely of Fredkin gates.
The basic Fredkin gate is a controlled swap gate that maps three inputs (C, I1, I2) onto three outputs (C, O1, O2).
The C input is mapped directly to the C output. If C = 0, no swap is performed; I1 maps to O1, and I2 maps to O2.
Otherwise, the two outputs are swapped so that I1 maps to O2, and I2 maps to O1. It is easy to see that this circuit is
reversible, i.e, "undoes itself" when run backwards. A generalized nn Fredkin gate passes its first n-2 inputs unchanged to
the corresponding outputs, and swaps its last two outputs if and only if the first n-2 inputs are all 1.The Fredkin gate is the
reversible three-bit gate that swaps the last two bits if the first bit is 1.

Figure 3.3.1: Fredkin Gate

Figure 3.3.2: Fredkin Full-Adder

Full Adder Using FTRG Gate

A New 5x5 Fault Tolerant reversible Gate, (FTRG) is shown in Figure 3.4.1. This is not a one-through gate. It can
be seen that every output has unique input. Input can easily be recovered from output. FTRG gate can be used to
implement any arbitrary Boolean function. Thus it is called as universal gate. It is also a parity preserving. It can easily be
verified by making the comparison between the parity of the input to the parity of the output i.e. ABCDE and
PQRST. A full-adder can be realized using FTRG as shown in Figure 3.4.2.

Figure 3.4.1: FTRG Configuration

Figure 3.4.2: Full adder Using FTRG Gate

Full Adder Using PFAG Gate

PFAG is based on the Peres gate as shown in figure 3.4.1. PFAG has 4-input lines and 4-output lines. This gate
can be used to realize any arbitrary Boolean function and therefore universal. The hardware complexity of this gate is less
compared to the existing ones and requires only one clock cycle. The quantum realization cost of this gate is only 8 and
ready for use in current nanotechnology. Reversible logic design differs significantly from traditional combinational logic
design approaches. A full adder implementation using the Peres gates also known as Peres Full Adder Gate is shown in
figure 3.4.2

Figure 3.5.1: Peres Gate Fig

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Figure 3.5.2: Peres Full Adder Gate

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Arati B. Sudhakar & Veena M. B

METHODOLOGY FOR TESTING THE EFFECTS

The methodology for testing the effects of using Reversible logic in the given floating point multiplier is best
explained through a flow chart:

Figure 4.1: Methodology

RESULTS
The area and speed (delay) information can be noted from the Synthesis report generated by the Xilinx synthesis
tool. Power analysis is done using the Xilinx XPower tool.
Table 1
Area (LUTS)
Speed (MHz)
Power (mW)

Conventional
4357
16.6
0.412

DKG
4750
18.77
0.047

Peres
4395
16.47
0.081

Fredkin
4420
23.46
0.040

FTRG
4403
16.584
0.110

TSG
4378
16.668
0.114

Clearly, of the various implementations, the floating point unit with reversible logic in almost all the chosen cases
has performed better in-terms of power. However, there can be variations in area and speed since reversible logic uses
more regular logic to satisfy and implement the reversible logic principles in the design. One more point to note is that this
analysis is done on the FPGA platform that uses LUTs and flip-flops.

CONCLUSIONS
Floating-point implementation on FPGAs has been the interest of many researchers. Multiplier implemented with
the reversible logic can be conveniently modeled in Verilog and tested on a FPGA. A lot of work has been done on
implementing basic multipliers but not the floating point multipliers with reversible computing. In this project work,
a floating point single precision multiplier will be designed with Verilog and implemented on the FPGA. It can be
concluded that the floating point multiplier shows significant improvement in terms of power and improvements in certain
cases in terms of area and speed when implemented using reversible logic.

REFERENCES
1.

R. Landuer, IBM, Irreversibility and heat generation in the computing process, J. Res. Develop, 5 (1961) 183.

2.

C. H. Bennet, Logical reversibility of computation, IBM J. Res. Dev, 6 (1973) 525

Impact Factor (JCC): 4.9467

Index Copernicus Value (ICV): 3.0

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Reconfigurable Single Precision Floating Point Multiplier Using Reversible Logic

3.

V. V. Shende, I.L. Markov, and S.S. Bullock, Synthesis of quantum logic circuits, IEEE Trans. Comput.-Aided
Des. Integr. Circuits Syst, 25 (2006) 1000

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M. Haghparast, S. J. Jassbi, K. Navi and O. Hashemipour, "Design of a novel reversible multiplier circuit using
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R. Landuer, IBM, Irreversibility and heat generation in the computing process, J. Res. Develop, 5 (1961) 183.

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C. H. Bennet, Logical reversibility of computation, IBM J. Res. Dev, 6 (1973) 525

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V. V. Shende, I.L. Markov, and S.S. Bullock, Synthesis of quantum logic circuits, IEEE Trans. Comput.-Aided
Des. Integr. Circuits Syst, 25 (2006) 1000

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M. Haghparast, S. J. Jassbi, K. Navi and O. Hashemipour, "Design of a novel reversible multiplier circuit using
HNG gate in nanotechnology", World Appl. Sci. 1, 3 (2008) 974.

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M. Haghparast and K. Navi, "A Novel Reversible Full Adder Circuit for Nanotechnology Based Systems". J.
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