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Calculation of Setup time and Hold time

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ASIC Design Methodologies and Tools (Digital)


Calculation of Setup time and Hold time
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9th December
2005,10:12

anan_tv
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lvision model generation for clock


gating cells in LV flow
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How to provide definition of clock...
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Interfacing rtc(ds1307) pic24f


Hi All, I am trying to interface RTC(DS1307 WITH I2C
) with pic24fj128ga010, somewhere i m doing

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Calculation
of
Setup
time
and
Hold
time
Haiii,

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#1

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How to
calcula
te
Setup
time
and
Hold
time
manual
ly???
How
does

04/11/2014 11:15 AM

Calculation of Setup time and Hold time


mistake but i m not getting where please can any
one find wt i m doing wrong and help me please.. ...

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9th December 2005,10:12

Posted By Ranjitharanju. Today 05:56 in


Microcontrollers

HFSS field calculator


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help required -- HFSS to Gerber


hello i have power divider designed in HFSS.Now for
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12th December 2005,15:46

Posted By shilpa.k. Today 05:44 in Electromagnetic


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How design the encapsulation M-bus in


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Precision M

Hello, As I am novice in embedded sofware


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they
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9th December
2005,21:40

semiconductorman
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#2

Re:
Calculation
of
Setup
time
and
Hold
time
setup
and
holdtim

04/11/2014 11:15 AM

Calculation of Setup time and Hold time


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e will
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12th December
2005,10:24

anan_tv
Junior Member level 1

#3

Re:
Calculation
of
Setup
time
and
Hold
time
haiii ,

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I think
the
vendor
will be
giving
it for
ASIC
only.
what
abt
FPGA?
??
also for
any
circuit ,
how to
calucul
ate
them??
?

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#4

04/11/2014 11:15 AM

Calculation of Setup time and Hold time


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12th December
2005,15:03

anjali
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Re:
Calculation
of
Setup
time
and
Hold
time
even
for
FPGA,
there
will be
tech
specific
librarie
s.
setup
& hold
periods
r given
in
those
libs.

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12th December
2005,15:46

farhada
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#5

Calculation
of
Setup
time
and
Hold
time
Take a
look at:
http://w
ww.arl.
wustl.e
du
/~jaf/ha
rdwa...l
culatio

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
n.html

Top Posters

It has a
good
explan
ation
about
how to
calcual
te the
S&H.

FvM (25582), keith1200rs (10883), alexan_e


(10804), IanP (7943), bigdogguru (7314)

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found
this post
helpful.
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13th December
2005,06:00

anan_tv
Junior Member level 1

#6

Re:
Calculation
of
Setup
time
and
Hold
time
haii ,

Join Date:

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I
already
seen
more
websit
es for
the
formula
es.
also
there
are lot
of
variant

5 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
s in the
formula
es
such
as:
Hold
time <=

shorest
contam
ination
path
delays
<=
propag
ation
delay
<=
clk-Q
delay +
combin
ational
path
delay clk
skew
Setup
time <=
clk
period
-(
clk-Q
delay +
combin
ational
path
delay +
clk
skew)

Also
w.r.t
clock
clk-low
>=
Setup
time
clk-hig
h <=
Hold

6 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
time
which
of the
above
has to
be
used
for
checki
ng
violatio
ns???
& for
require
ments?
??
[/list]

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22nd December
2005,14:15

beckchm
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#7

Re:
Calculation
of
Setup
time
and
Hold
time
in
general
,
differen
t libs
have
differen
t time
constra
ints.

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23rd December
2005,02:51

7 of 23

#8

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

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Yun Lin
Member level 4

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China

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Level:

Calculation
of
Setup
time
and
Hold
time
if you
want to
calcula
te, the
simulat
ion can
tell you
the
setup
and
hold
time.
The
setup
and
hold
time is
the
point
that the
functio
n is
fail.

Reply With
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23rd December
2005,13:56

bansalr
Full Member level 2

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#9

Re:
Calculation
of
Setup
time
and
Hold
time
The
setUp
and
Hold
time

8 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
are
defined
by the
Library
vendor
s.
In
FPGA
the
data
sheet
provide
s the
setup
and
hold
time.

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24th December
2005,06:33

cfriend
Full Member level 1

9 of 23

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#10

Calculation
of
Setup
time
and
Hold
time
Calcula
ting the
setup
and
hold
times
at the
pins of
a chip
I'm
recordi
ng this
informa
tion not
becaus
e it is
difficult
to
rederiv
e, but

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
becaus
e I've
derived
it at
least
twice
now,
and it
always
takes
me
about
half an
hour.
Next
time I
need
this
informa
tion, I'll
know
where
to look
it up
quickly!
Summ
ary
A
positiv
e setup
time
indicat
es a
time
before
the
active
edge of
clock,
a
negativ
e setup
time,
after.
(setup
time at
pin of
whole
chip) =
(setup
time of
flip-flop
data
pin)

10 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
- (min
clock
delay
from
chip
pin to
FF pin)
+ (max
data
delay
from
chip
pin to
FF pin)
A
positiv
e hold
time
indicat
es a
time
after
the
active
edge of
clock,
a
negativ
e hold
time,
before.
(hold
time at
pin of
whole
chip) =
(hold
time of
flip-flop
data
pin)
+ (max
clock
delay
from
chip
pin to
FF pin)
- (min
data
delay
from
chip

11 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
pin to
FF pin)

Details
Suppo
se that
you
have a
chip
with a
data
input
pin
whose
signal
goes
throug
h some
delay
on chip
(e.g.,
the
input
pad,
RC
delay
on the
wire to
a FF
(flip-flo
p)
input,
some
logic
inserte
d
expres
sly for
adding
delay)
before
being
sample
d at a
FF.
This
FF
respon
ds to
active
edges
of a
clock
pin,

12 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
which
is also
delaye
d
before
it
reache
s the
FF
clock
input.
Given
the
setup
and
hold
times
of the
FF
data
input
relative
the the
FF
clock
input,
what
are the
setup
and
hold
times
of the
pin A
relative
to the
the pin
CK of
the
chip?
Here
are
some
abbrevi
ations
used
below:

cf time
when
active
edge

13 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
occurs
on
Clock
pin of
Flip-flo
p
cc time
when
active
edge
occurs
on
Clock
pin of
the
whole
Chip
df time of
a
transiti
on on
Data
input of
Flip-flo
p
dc time of
a
transiti
on on
Data
input of
the
whole
Chip
Let's
specify
the
setup-h
old
window
of the
FF as
follows.
The FF
will
reliably
sample
the
data
input
as its
next

14 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

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state
as long
as the
data
input of
the FF
remain
s
stable
in the
interval
[cf-fset
up,
cf+fhol
d], or:
df is
not in
[cf-fset
up,
cf+fhol
d]
Alterna
tely:

(df < cf
fsetup)
(1)
OR
(df > cf
+
fhold)
(2)
then
the FF
will
reliably
sample
the
data
input
as its
next
state.
Also
suppos
e that
the
delay
from a
transiti
on on
the

15 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
data
pin of
the
whole
chip to
a
transiti
on on
the
data
input of
the FF
is in
the
range
[dmin,
dmax].
Stated
anothe
r way:

(dc+d
min <=
df) (3)
AND
(df <=
dc+dm
ax) (4)
Finally,
suppos
e that
the
delay
from
an
active
transiti
on on
the
clock
pin of
the
whole
chip to
an
active
transiti
on on
the
clock
input of
the FF
is in
the

16 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
range
[cmin,
cmax].

(cc+cm
in <=
cf) (5)
AND
(cf <=
cc+cm
ax) (6)
Now,
we
wish to
determi
ne the
smalle
st
interval
that the
data
pin of
the
whole
chip
must
be
stable,
of the
form
[cc-cse
tup,
cc+cho
ld], to
guaran
tee that
the FF
data
pin
meets
its
setup
and
hold
times.
I'm
going
to
derive
these
"backw
ards",
with a

17 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
sequen
ce of
statem
ents of
the
form:
statem
ent 1
<== {
reason
1}
statem
ent 2
<==> {
reason
2}
statem
ent 3
This
means
that
statem
ent 2
implies
that
statem
ent 1 is
true,
with
any
justifica
tion or
comme
nts
given
as
reason
1. It
also
means
that
statem
ent 2 is
true if
and
only if
statem
ent 3 is
true,
with
any
justifica
tion

18 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
given
as
reason
2.
Here
we go,
for the
setup
time:
df < cf
- fsetup
<== {
(4) }
(dc+d
max) <
cf fsetup
<== {
(5) }
(dc+d
max) <
(cc+cm
in) fsetup
<==> {
algebra
}
dc < cc
(fsetup
- cmin
+
dmax)
The
final
result
implies
that the
setup
time at
the
whole
chip is
(fsetup
- cmin
+
dmax),
as
summa
rized at
the
beginni

19 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
ng.
Now
for the
hold
time,
which
is
derived
almost
identic
ally:
df > cf
+ fhold
<== {
(3) }
(dc+d
min) >
cf +
fhold
<== {
(6) }
(dc+d
min) >
(cc+cm
ax) +
fhold
<==> {
algebra
}
dc > cc
+
(fhold
+ cmax
- dmin)
The
final
result
implies
that the
setup
time at
the
whole
chip is
(fhold
+ cmax
dmin),
as
summa
rized at
the

20 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
beginni
ng.
Added
after
35
second
s:
http://w
ww.arl.
wustl.e
du
/~jaf/ha
rdwa...l
culatio
n.html

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#11

24th December
2005,20:13

Resistance
Member level 4

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Dec 2005

Posts:

74

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Level:

Re:
Calculation
of
Setup
time
and
Hold
time
Hi,

Set up
times
and
hold
times
of a
flop or
latch
are
specifi
ed by
the
vendor.
.
but
these

21 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

http://www.edaboard.com/thread51611.html
depend
on the
technol
gy u
would
be
choosi
ng and
many
more
factors.
.
but set
up
times
for a
port(in
put or
output)
is
differen
t and
ought
to
estimat
ed by
the
user..
ru
interest
ed in
that?
Plus
for
FPGA
and
ASIC
dont
have
diff
concep
ts for
set and
hold
times..
may be
the
values
may
differ .
plus if

22 of 23

04/11/2014 11:15 AM

Calculation of Setup time and Hold time

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u are
taking
about
pin set
up
times
then
differen
ce
does
exist..

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