Analog Features:
Analog-to-Digital Converter (ADC) module:
- 10-bit resolution, up to 8 channels
- Conversion available during Sleep
Analog Comparator module:
- Up to two rail-to-rail analog comparators
- Power mode control
- Software controllable hysteresis
Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
- 5-bit rail-to-rail resistive DAC with positive
and negative reference selection
Peripheral Highlights:
Up to 11 I/O Pins and 1 Input-Only Pin:
- High current sink/source 25 mA/25 mA
- Programmable weak pull-ups
- Programmable interrupt-on-change pins
Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler
Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Dedicated, low-power 32 kHz oscillator driver
Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
Enhanced CCP (ECCP) modules:
- Software selectable time bases
- Auto-shutdown and auto-restart
- PWM steering
Master Synchronous Serial Port (MSSP) with SPI
and I2CTM with:
- 7-bit address masking
- SMBus/PMBusTM compatibility
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module:
- RS-232, RS-485 and LIN compatible
- Auto-Baud Detect
Capacitive Sensing (CPS) module (mTouch):
- Up to 8 input channels
DS40001413D-page 1
PIC12(L)F1822/16(L)F1823
Peripheral Features (Continued):
Data Signal Modulator module
- Selectable modulator and carrier sources
SR Latch:
- Multiple Set/Reset input options
- Emulates 555 Timer applications
Data EEPROM
(bytes)
Data SRAM
(bytes)
I/Os(2)
CapSense (ch)
Comparators
Timers
(8/16-bit)
EUSART
MSSP (I2C/SPI)
ECCP (Full-Bridge)
ECCP (Half-Bridge)
CCP
Debug(1)
XLP
PIC12(L)F1822
(1)
2K
256
128
2/1
0/1/0
I/H
PIC12(L)F1840
(2)
4K
256
256
2/1
0/1/0
I/H
PIC16(L)F1823
(1)
2K
256
128
12
2/1
1/0/0
I/H
PIC16(L)F1824
(3)
4K
256
256
12
4/1
1/1/2
I/H
PIC16(L)F1825
(4)
8K
256
1024
12
4/1
1/1/2
I/H
PIC16(L)F1826
(5)
2K
256
256
16
12
12
2/1
1/0/0
I/H
PIC16(L)F1827
(5)
4K
256
384
16
12
12
4/1
1/1/2
I/H
PIC16(L)F1828
(3)
4K
256
256
18
12
12
4/1
1/1/2
I/H
PIC16(L)F1829
(4)
8K
256
1024
18
12
12
4/1
1/1/2
I/H
PIC16(L)F1847
(6)
8K
256
1024
16
12
12
4/1
1/1/2
I/H
SR Latch
Device
Program Memory
Flash (words)
TABLE 1:
Note:
For other small form-factor package availability and marking information, please visit
www.microchip.com/packaging or contact your local sales office.
DS40001413D-page 2
PIC12(L)F1822/16(L)F1823
FIGURE 1:
VDD
RA5
RA4
2
3
4
MCLR/VPP/RA3
8
7
6
5
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RA3
RA4
AN3
RA5
VDD
VSS
C1IN+
P1B(1)
TX(1)
CK(1)
SDO(1)
SS(1)
IOC
MDOUT
ICSPDAT
ICDDAT
C1IN0-
SRI
RX(1)
DT(1)
SCL
SCK
IOC
MDMIN
ICSPCLK
ICPCLK
CPS2 C1OUT
SRQ
T0CKI
CCP1(1)
P1A(1)
FLT0
SDA
SDI
INT/
IOC
MDCIN1
T1G(1)
SS(1)
IOC
MCLR
VPP
CPS3
C1IN1-
T1G(1)
T1OSO
P1B(1)
TX(1)
CK(1)
SDO(1)
IOC
MDCIN2
OSC2
CLKOUT
CLKR
SRNQ
T1CKI
T1OSI
CCP1(1)
P1A(1)
RX(1)
DT(1)
IOC
OSC1
CLKIN
VDD
VSS
Cap Sense
Basic
AN2
Pull-up
Modulator
RA2
Interrupt
VREF+
MSSP
AN1
EUSART
ECCP
RA1
Timers
AN0
SR Latch
Comparator
A/D
RA0
Reference
8-Pin PDIP/SOIC/DFN/UDFN
I/O
TABLE 2:
PIC12(L)F1822
DACOUT CPS0
CPS1
DS40001413D-page 3
PIC12(L)F1822/16(L)F1823
FIGURE 2:
FIGURE 3:
RA5
RA4
MCLR/VPP/RA3
RC5
RC4
RC3
PIC16(L)F1823
VDD
14
VSS
13
RA0/ICSPDAT
12
RA1/ICSPCLK
11
RA2
10
RC0
RC1
RC2
RA4 2
VDD
NC
NC
VSS
15
14
13
RA5 1
16
QFN, UQFN
11 RA1/ICSPCLK
PIC16(L)F1823
RC1 8
9 RC0
RC2 7
RC5 4
RC3 6
10 RA2
MCLR/VPP/RA3 3
RC4
DS40001413D-page 4
12 RA0/ICSPDAT
PIC12(L)F1822/16(L)F1823
14-PIN ALLOCATION TABLE (PIC16(L)F1823)
Reference
Cap Sense
Comparator
SR Latch
Timers
ECCP
EUSART
MSSP
Interrupt
Modulator
Pull-up
Basic
RA0
13 12
AN0
DACOUT
CPS0
C1IN+
TX(1)
CK(1)
IOC
ICSPDAT
ICDDAT
RA1
12 11
AN1
VREF+
CPS1
C12IN0-
SRI
RX(1)
DT(1)
IOC
ICSPCLK
ICDCLK
RA2
11 10
AN2
CPS2
C1OUT
SRQ
T0CKI
FLT0
INT/
IOC
RA3
T1G(1)
SS(1)
IOC
MCLR
VPP
RA4
AN3
CPS3
T1G(1)
T1OSO
SDO(1)
IOC
OSC2
CLKOUT
CLKR
RA5
T1CKI
T1OSI
IOC
OSC1
CLKIN
RC0
10
AN4
CPS4
C2IN+
SCL
SCK
RC1
AN5
CPS5
C12IN1-
SDA
SDI
RC2
AN6
CPS6
C12IN2-
P1D
SDO(1)
MDCIN1
RC3
AN7
CPS7
C12IN3-
P1C
SS(1)
MDMIN
RC4
C2OUT
SRNQ
P1B
TX(1)
CK(1)
MDOUT
RC5
CCP1
P1A
RX(1)
DT(1)
MDCIN2
VDD
16
VDD
VSS
14 13
VSS
I/O
A/D
16-Pin QFN/UQFN
14-Pin PDIP/SOIC/TSSOP
TABLE 3:
Note 1:
DS40001413D-page 5
PIC12(L)F1822/16(L)F1823
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 8
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 15
3.0 Memory Organization ................................................................................................................................................................. 17
4.0 Device Configuration .................................................................................................................................................................. 45
5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 51
6.0 Reference Clock Module ............................................................................................................................................................ 68
7.0 Resets ........................................................................................................................................................................................ 71
8.0 Interrupts .................................................................................................................................................................................... 80
9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 92
10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 95
11.0 Data EEPROM and Flash Program Memory Control ................................................................................................................. 98
12.0 I/O Ports ................................................................................................................................................................................... 112
13.0 Interrupt-on-Change ................................................................................................................................................................. 123
14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 127
15.0 Temperature Indicator Module ................................................................................................................................................. 129
16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 130
17.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 143
18.0 SR Latch................................................................................................................................................................................... 147
19.0 Comparator Module.................................................................................................................................................................. 152
20.0 Timer0 Module ......................................................................................................................................................................... 162
21.0 Timer1 Module ......................................................................................................................................................................... 165
22.0 Timer2 Modules........................................................................................................................................................................ 176
23.0 Data Signal Modulator (DSM) .................................................................................................................................................. 180
24.0 Capture/Compare/PWM Module .............................................................................................................................................. 190
25.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 217
26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 268
27.0 Capacitive Sensing (CPS) module ........................................................................................................................................... 196
28.0 In-Circuit Serial Programming (ICSP) ................................................................................................................................ 305
29.0 Instruction Set Summary .......................................................................................................................................................... 308
30.0 Electrical Specifications............................................................................................................................................................ 322
31.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 354
32.0 Development Support............................................................................................................................................................... 382
33.0 Packaging Information.............................................................................................................................................................. 386
Appendix A: Revision History............................................................................................................................................................. 412
Appendix B: Device Differences......................................................................................................................................................... 412
The Microchip Web Site ..................................................................................................................................................................... 413
Customer Change Notification Service .............................................................................................................................................. 413
Customer Support .............................................................................................................................................................................. 413
Product Identification System............................................................................................................................................................. 414
DS40001413D-page 6
PIC12(L)F1822/16(L)F1823
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
DS40001413D-page 7
PIC12(L)F1822/16(L)F1823
1.0
DEVICE OVERVIEW
Peripheral
PIC16(L)F1823
DEVICE PERIPHERAL
SUMMARY
PIC12(L)F1822
TABLE 1-1:
ADC
Data EEPROM
EUSART
SR Latch
ECCP1
C1
Capture/Compare/PWM Modules
Comparators
C2
Timer0
Timer1
Timer2
Timers
DS40001413D-page 8
PIC12(L)F1822/16(L)F1823
FIGURE 1-1:
Program
Flash Memory
CLKR
RAM
EEPROM
Clock
Reference
OSC2/CLKOUT
Timing
Generation
OSC1/CLKIN
INTRC
Oscillator
PORTA
CPU
(Figure 2-1)
PORTC(3)
MCLR
Note
1:
2:
3:
SR
Latch
Timer0
Timer1
ADC
10-Bit
DAC
Comparators
ECCP1
MSSP
Modulator
EUSART
FVR
CapSense
DS40001413D-page 9
PIC12(L)F1822/16(L)F1823
TABLE 1-2:
Name
Function
Input
Type
RA0/AN0/CPS0/C1IN+/
DACOUT/TX(1)/CK(1)/SDO(1)/
SS(1)/P1B(1)/MDOUT/ICSPDAT/
ICDDAT
RA0
TTL
AN0
AN
RA1/AN1/CPS1/VREF+/C1IN0-/
SRI/RX(1)/DT(1)/SCL/SCK/
MDMIN/ICSPCLK/ICDCLK
RA2/AN2/CPS2/C1OUT/SRQ/
T0CKI/CCP1(1)/P1A(1)/FLT0/
SDA/SDI/INT/MDCIN1
RA3/SS(1)/T1G(1)/VPP/MCLR
Output
Type
Description
CPS0
AN
C1IN+
AN
DACOUT
AN
TX
CK
ST
SDO
SS
ST
P1B
MDOUT
ICSPDAT
ST
RA1
TTL
AN1
AN
CPS1
AN
VREF+
AN
C1IN0-
AN
SRI
ST
SR latch input.
RX
ST
DT
ST
SCL
I2C
SCK
ST
I2C clock.
MDMIN
ST
ICSPCLK
ST
RA2
ST
AN2
AN
CPS2
AN
C1OUT
SRQ
T0CKI
ST
CCP1
ST
CMOS Capture/Compare/PWM 1.
P1A
FLT0
ST
SDA
I2C
OD
SDI
CMOS
INT
ST
External interrupt.
MDCIN1
ST
RA3
TTL
SS
ST
T1G
ST
VPP
HV
Programming voltage.
MCLR
ST
DS40001413D-page 10
PIC12(L)F1822/16(L)F1823
TABLE 1-2:
Name
Function
Input
Type
RA4/AN3/CPS3/OSC2/
CLKOUT/T1OSO/C1IN1-/CLKR/
SDO(1)/CK(1)/TX(1)/P1B(1)/
T1G(1)/MDCIN2
RA4
TTL
Output
Type
Description
AN3
AN
CPS3
AN
OSC2
XTAL
XTAL
CLKOUT
T1OSO
XTAL
XTAL
C1IN1-
AN
CLKR
SDO
CK
ST
TX
P1B
T1G
ST
MDCIN2
ST
RA5
TTL
CLKIN
CMOS
OSC1
XTAL
T1OSI
XTAL
XTAL
T1CKI
ST
SRNQ
P1A
CCP1
ST
CMOS Capture/Compare/PWM 1.
DT
ST
RX
ST
VDD
VDD
Power
Positive supply.
VSS
VSS
Power
Ground reference.
RA5/CLKIN/OSC1/T1OSI/
T1CKI/SRNQ/P1A(1)/CCP1(1)/
DT(1)/RX(1)
DS40001413D-page 11
PIC12(L)F1822/16(L)F1823
TABLE 1-3:
Name
Function
Input
Type
RA0/AN0/CPS0/C1IN+/
DACOUT/TX(1)/CK(1)/ICSPDAT/
ICDDAT
RA0
TTL
AN0
AN
RA1/AN1/CPS1/C12IN0-/VREF+/
SRI/RX(1)/DT(1)/ICSPCLK/
ICDCLK
RA2/AN2/CPS2/T0CKI/INT/
C1OUT/SRQ/FLT0
RA3/SS(1)/T1G(1)/VPP/MCLR
RA4/AN3/CPS3/OSC2/
CLKOUT/T1OSO/CLKR/SDO(1)/
T1G(1)
Output
Type
Description
CPS0
AN
C1IN+
AN
DACOUT
AN
TX
CK
ST
ICSPDAT
ST
RA1
TTL
AN1
AN
CPS1
AN
C12IN0-
AN
VREF+
AN
SRI
ST
SR latch input.
RX
ST
DT
ST
ICSPCLK
ST
RA2
ST
AN2
AN
CPS2
AN
T0CKI
ST
INT
ST
External interrupt.
C1OUT
SRQ
FLT0
ST
RA3
TTL
SS
ST
T1G
ST
VPP
HV
Programming voltage.
MCLR
ST
RA4
TTL
AN3
AN
CPS3
AN
OSC2
XTAL
XTAL
CLKOUT
T1OSO
XTAL
CLKR
SDO
T1G
ST
XTAL
DS40001413D-page 12
PIC12(L)F1822/16(L)F1823
TABLE 1-3:
Name
Function
Input
Type
RA5/CLKIN/OSC1/T1OSI/T1CKI
RA5
TTL
CLKIN
CMOS
OSC1
XTAL
T1OSI
XTAL
XTAL
T1CKI
ST
RC0
TTL
AN4
AN
RC0/AN4/CPS4/C2IN+/SCL/
SCK
RC1/AN5/CPS5/C12IN1-/SDA/
SDI
RC2/AN6/CPS6/C12IN2-/P1D/
SDO(1)/MDCIN1
RC3/AN7/CPS7/C12IN3-/P1C/
SS(1)/MDMIN
RC4/C2OUT/SRNQ/P1B/CK(1)/
TX(1)/MDOUT
RC5/P1A/CCP1/DT(1)/RX(1)/
MDCIN2
Output
Type
Description
CPS4
AN
C2IN+
AN
SCL
I2C
OD
I2C clock.
SCK
ST
RC1
TTL
AN5
AN
CPS5
AN
C12IN1-
AN
SDA
I2C
OD
SDI
CMOS
RC2
TTL
AN6
AN
CPS6
AN
C12IN2-
AN
P1D
SDO
MDCIN1
ST
RC6
TTL
AN7
AN
CPS7
AN
C12IN3-
AN
P1C
SS
ST
MDMIN
ST
RC4
TTL
C2OUT
SRNQ
P1B
CK
ST
TX
MDOUT
RC5
TTL
P1A
CCP1
ST
CMOS Capture/Compare/PWM 1.
CMOS USART synchronous data.
DT
ST
RX
ST
MDCIN2
ST
DS40001413D-page 13
PIC12(L)F1822/16(L)F1823
TABLE 1-3:
Input
Type
Output
Type
VDD
VDD
Power
Positive supply.
VSS
VSS
Power
Ground reference.
Name
Description
DS40001413D-page 14
PIC12(L)F1822/16(L)F1823
2.0
2.1
2.2
2.3
2.4
Instruction Set
DS40001413D-page 15
PIC12(L)F1822/16(L)F1823
FIGURE 2-1:
15
Configuration
15
MUX
Flash
Program
Memory
Program
Bus
16-Level
8 Level Stack
Stack
(13-bit)
(15-bit)
14
Instruction
Instruction Reg
reg
Data Bus
Program Counter
RAM
Program Memory
Read (PMR)
12
RAM Addr
Addr MUX
Indirect
Addr
12
12
Direct Addr 7
5
BSR
FSR Reg
reg
15
FSR0reg
Reg
FSR
FSR1
Reg
FSR reg
15
STATUS Reg
reg
STATUS
8
3
Power-up
Timer
OSC1/CLKIN
OSC2/CLKOUT
Instruction
Decodeand
&
Decode
Control
Timing
Generation
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
MUX
ALU
8
W Reg
Internal
Oscillator
Block
VDD
DS40001413D-page 16
VSS
PIC12(L)F1822/16(L)F1823
3.0
MEMORY ORGANIZATION
3.1
TABLE 3-1:
PIC12(L)F1822
PIC16(L)F1823
2,048
07FFh
DS40001413D-page 17
PIC12(L)F1822/16(L)F1823
FIGURE 3-1:
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
RETLW Instruction
Stack Level 0
Stack Level 1
Stack Level 15
EXAMPLE 3-1:
0000h
Interrupt Vector
0004h
0005h
Page 0
Rollover to Page 0
Wraps to Page 0
07FFh
0800h
RETLW
RETLW
RETLW
RETLW
DATA0
DATA1
DATA2
DATA3
RETLW INSTRUCTION
;Add Index in W to
;program counter to
;select data
;Index0 data
;Index1 data
The BRW instruction makes this type of table very simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
Wraps to Page 0
Rollover to Page 0
constants
BRW
my_function
; LOTS OF CODE
MOVLW
DATA_INDEX
CALL constants
; THE CONSTANT IS IN W
Wraps to Page 0
DS40001413D-page 18
There are two methods of accessing constants in program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.1.1.1
Reset Vector
On-chip
Program
Memory
3.1.1
7FFFh
PIC12(L)F1822/16(L)F1823
3.1.1.2
The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the
lower eight bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the program memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.
The HIGH directive will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
constants
RETLW DATA0
;Index0 data
RETLW DATA1
;Index1 data
RETLW DATA2
RETLW DATA3
my_function
; LOTS OF CODE
MOVLW
LOW constants
MOVWF
FSR1L
MOVLW
HIGH constants
MOVWF
FSR1H
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
3.2
3.2.1
CORE REGISTERS
INDF0
INDF1
PCL
STATUS
FSR0 Low
FSR0 High
FSR1 Low
FSR1 High
BSR
WREG
PCLATH
INTCON
Note:
12 core registers
20 Special Function Registers (SFR)
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of common RAM
DS40001413D-page 19
PIC12(L)F1822/16(L)F1823
3.2.1.1
STATUS Register
REGISTER 3-1:
U-0
U-0
R-1/q
R-1/q
R/W-0/u
R/W-0/u
R/W-0/u
TO
PD
DC(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
bit 0
C: Carry/Borrow bit(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the
second operand.
DS40001413D-page 20
PIC12(L)F1822/16(L)F1823
3.2.2
3.2.3
3.2.4
TABLE 3-2:
Device
3.2.3.1
3.2.5
PIC12(L)F1822/16(L)F1823
Banks
Table No.
0-7
Table 3-3
8-15
Table 3-4
16-23
Table 3-5
24-31
Table 3-6
31
Table 3-7
COMMON RAM
FIGURE 3-2:
BANKED MEMORY
PARTITIONING
Memory Region
00h
0Bh
0Ch
Core Registers
(12 bytes)
6Fh
70h
Common RAM
(16 bytes)
7Fh
DS40001413D-page 21
BANK 0
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PORTA
PORTC(1)
PIR1
PIR2
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
CPSCON0
CPSCON1
General
Purpose
Register
80 Bytes
06Fh
070h
BANK 1
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
0A0h
0BFh
0CFh
0EFh
0F0h
Legend:
Note 1:
Unimplemented
Read as 0
BANK 2
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
0FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
LATA
LATC(1)
CM1CON0
CM1CON1
CM2CON0(1)
CM2CON1(1)
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
APFCON
16Fh
170h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
ANSELA
ANSELC(1)
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
RCREG
TXREG
SPBRGL
SPBRGH
RCSTA
TXSTA
BAUDCON
Accesses
70h 7Fh
17Fh
BANK 4
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
Unimplemented
Read as 0
1EFh
1F0h
BANK 3
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
Unimplemented
Read as 0
Accesses
70h 7Fh
Common RAM
07Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TRISA
TRISC(1)
PIE1
PIE2
OPTION
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
General
Purpose
Register
32 Bytes
BANK 5
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
Unimplemented
Read as 0
26Fh
270h
Accesses
70h 7Fh
1FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
WPUA
WPUC(1)
SSP1BUF
SSP1ADD
SSP1MASK
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3
BANK 6
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
Unimplemented
Read as 0
BANK 7
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
Unimplemented
Read as 0
Accesses
70h 7Fh
2FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
36Fh
370h
2EFh
2F0h
Accesses
70h 7Fh
27Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
Unimplemented
Read as 0
3EFh
3F0h
Accesses
70h 7Fh
37Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
IOCAP
IOCAN
IOCAF
CLKRCON
MDCON
MDSRC
MDCARL
MDCARH
Accesses
70h 7Fh
3FFh
PIC12(L)F1822/16(L)F1823
DS40001413D-page 22
TABLE 3-3:
TABLE 3-4:
BANK 8
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 9
480h
481h
482h
483h
484h
485h
486h
487h
488h
489h
48Ah
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
Unimplemented
Read as 0
DS40001413D-page 23
46Fh
470h
Legend:
BANK 10
500h
501h
502h
503h
504h
505h
506h
507h
508h
509h
50Ah
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
Unimplemented
Read as 0
4EFh
4F0h
Accesses
70h 7Fh
47Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 11
580h
581h
582h
583h
584h
585h
586h
587h
588h
589h
58Ah
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
Unimplemented
Read as 0
56Fh
570h
Accesses
70h 7Fh
4FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Unimplemented
Read as 0
5EFh
5F0h
Accesses
70h 7Fh
57Fh
BANK 12
600h
601h
602h
603h
604h
605h
606h
607h
608h
609h
60Ah
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
BANK 13
680h
681h
682h
683h
684h
685h
686h
687h
688h
689h
68Ah
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
Unimplemented
Read as 0
66Fh
670h
Accesses
70h 7Fh
5FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 14
700h
701h
702h
703h
704h
705h
706h
707h
708h
709h
70Ah
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
Unimplemented
Read as 0
6EFh
6F0h
Accesses
70h 7Fh
67Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 15
780h
781h
782h
783h
784h
785h
786h
787h
788h
789h
78Ah
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
Unimplemented
Read as 0
76Fh
770h
Accesses
70h 7Fh
6FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Unimplemented
Read as 0
7EFh
7F0h
Accesses
70h 7Fh
77Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Accesses
70h 7Fh
7FFh
PIC12(L)F1822/16(L)F1823
400h
401h
402h
403h
404h
405h
406h
407h
408h
409h
40Ah
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
BANK 16
800h
801h
802h
803h
804h
805h
806h
807h
808h
809h
80Ah
80Bh
80Ch
80Dh
80Eh
80Fh
810h
811h
812h
813h
814h
815h
816h
817h
818h
819h
81Ah
81Bh
81Ch
81Dh
81Eh
81Fh
820h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 17
880h
881h
882h
883h
884h
885h
886h
887h
888h
889h
88Ah
88Bh
88Ch
88Dh
88Eh
88Fh
890h
891h
892h
893h
894h
895h
896h
897h
898h
899h
89Ah
89Bh
89Ch
89Dh
89Eh
89Fh
8A0h
Unimplemented
Read as 0
86Fh
870h
Legend:
BANK 18
900h
901h
902h
903h
904h
905h
906h
907h
908h
909h
90Ah
90Bh
90Ch
90Dh
90Eh
90Fh
910h
911h
912h
913h
914h
915h
916h
917h
918h
919h
91Ah
91Bh
91Ch
91Dh
91Eh
91Fh
920h
Unimplemented
Read as 0
8EFh
8F0h
8FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 19
980h
981h
982h
983h
984h
985h
986h
987h
988h
989h
98Ah
98Bh
98Ch
98Dh
98Eh
98Fh
990h
991h
992h
993h
994h
995h
996h
997h
998h
999h
99Ah
99Bh
99Ch
99Dh
99Eh
99Fh
9A0h
Unimplemented
Read as 0
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Accesses
70h 7Fh
97Fh
BANK 20
A00h
A01h
A02h
A03h
A04h
A05h
A06h
A07h
A08h
A09h
A0Ah
A0Bh
A0Ch
A0Dh
A0Eh
A0Fh
A10h
A11h
A12h
A13h
A14h
A15h
A16h
A17h
A18h
A19h
A1Ah
A1Bh
A1Ch
A1Dh
A1Eh
A1Fh
A20h
Unimplemented
Read as 0
9EFh
9F0h
96Fh
970h
Accesses
70h 7Fh
Accesses
70h 7Fh
87Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 21
A80h
A81h
A82h
A83h
A84h
A85h
A86h
A87h
A88h
A89h
A8Ah
A8Bh
A8Ch
A8Dh
A8Eh
A8Fh
A90h
A91h
A92h
A93h
A94h
A95h
A96h
A97h
A98h
A99h
A9Ah
A9Bh
A9Ch
A9Dh
A9Eh
A9Fh
AA0h
Unimplemented
Read as 0
BANK 22
B00h
B01h
B02h
B03h
B04h
B05h
B06h
B07h
B08h
B09h
B0Ah
B0Bh
B0Ch
B0Dh
B0Eh
B0Fh
B10h
B11h
B12h
B13h
B14h
B15h
B16h
B17h
B18h
B19h
B1Ah
B1Bh
B1Ch
B1Dh
B1Eh
B1Fh
B20h
Unimplemented
Read as 0
Accesses
70h 7Fh
A7Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
AEFh
AF0h
A6Fh
A70h
Accesses
70h 7Fh
9FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 23
B80h
B81h
B82h
B83h
B84h
B85h
B86h
B87h
B88h
B89h
B8Ah
B8Bh
B8Ch
B8Dh
B8Eh
B8Fh
B90h
B91h
B92h
B93h
B94h
B95h
B96h
B97h
B98h
B99h
B9Ah
B9Bh
B9Ch
B9Dh
B9Eh
B9Fh
BA0h
Unimplemented
Read as 0
Unimplemented
Read as 0
Accesses
70h 7Fh
B7Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BEFh
BF0h
B6Fh
B70h
Accesses
70h 7Fh
AFFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Accesses
70h 7Fh
BFFh
PIC12(L)F1822/16(L)F1823
DS40001413D-page 24
TABLE 3-5:
TABLE 3-6:
BANK 24
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 25
C80h
C81h
C82h
C83h
C84h
C85h
C86h
C87h
C88h
C89h
C8Ah
C8Bh
C8Ch
C8Dh
C8Eh
C8Fh
C90h
C91h
C92h
C93h
C94h
C95h
C96h
C97h
C98h
C99h
C9Ah
C9Bh
C9Ch
C9Dh
C9Eh
C9Fh
CA0h
Unimplemented
Read as 0
DS40001413D-page 25
C6Fh
C70h
CFFh
BANK 26
D00h
D01h
D02h
D03h
D04h
D05h
D06h
D07h
D08h
D09h
D0Ah
D0Bh
D0Ch
D0Dh
D0Eh
D0Fh
D10h
D11h
D12h
D13h
D14h
D15h
D16h
D17h
D18h
D19h
D1Ah
D1Bh
D1Ch
D1Dh
D1Eh
D1Fh
D20h
Unimplemented
Read as 0
CEFh
CF0h
Accesses
70h 7Fh
Legend:
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 27
D80h
D81h
D82h
D83h
D84h
D85h
D86h
D87h
D88h
D89h
D8Ah
D8Bh
D8Ch
D8Dh
D8Eh
D8Fh
D90h
D91h
D92h
D93h
D94h
D95h
D96h
D97h
D98h
D99h
D9Ah
D9Bh
D9Ch
D9Dh
D9Eh
D9Fh
DA0h
Unimplemented
Read as 0
D6Fh
D70h
Accesses
70h 7Fh
CFFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Unimplemented
Read as 0
DEFh
DF0h
Accesses
70h 7Fh
D7Fh
BANK 28
E00h
E01h
E02h
E03h
E04h
E05h
E06h
E07h
E08h
E09h
E0Ah
E0Bh
E0Ch
E0Dh
E0Eh
E0Fh
E10h
E11h
E12h
E13h
E14h
E15h
E16h
E17h
E18h
E19h
E1Ah
E1Bh
E1Ch
E1Dh
E1Eh
E1Fh
E20h
BANK 29
E80h
E81h
E82h
E83h
E84h
E85h
E86h
E87h
E88h
E89h
E8Ah
E8Bh
E8Ch
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
E9Bh
E9Ch
E9Dh
E9Eh
E9Fh
EA0h
Unimplemented
Read as 0
E6Fh
E70h
Accesses
70h 7Fh
DFFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 30
F00h
F01h
F02h
F03h
F04h
F05h
F06h
F07h
F08h
F09h
F0Ah
F0Bh
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
F20h
Unimplemented
Read as 0
EEFh
EF0h
Accesses
70h 7Fh
E7Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 31
F80h
INDF0
F81h
INDF1
F82h
PCL
F83h
STATUS
F84h
FSR0L
F85h
FSR0H
F86h
FSR1L
F87h
FSR1H
F88h
BSR
F89h
WREG
F8Ah
PCLATH
F8Bh
INTCON
F8Ch
F8Dh
F8Eh
F8Fh
F90h
F91h
F92h
F93h
F94h
F95h
F96h
F97h
See Table 3-7 for
F98h register mapping
F99h
details
F9Ah
F9Bh
F9Ch
F9Dh
F9Eh
F9Fh
FA0h
Unimplemented
Read as 0
F6Fh
F70h
Accesses
70h 7Fh
EFFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
FEFh
FF0h
Accesses
70h 7Fh
F7Fh
Accesses
70h 7Fh
FFFh
PIC12(L)F1822/16(L)F1823
C00h
C01h
C02h
C03h
C04h
C05h
C06h
C07h
C08h
C09h
C0Ah
C0Bh
C0Ch
C0Dh
C0Eh
C0Fh
C10h
C11h
C12h
C13h
C14h
C15h
C16h
C17h
C18h
C19h
C1Ah
C1Bh
C1Ch
C1Dh
C1Eh
C1Fh
C20h
PIC12(L)F1822/16(L)F1823
TABLE 3-7:
PIC12(L)F1822/16(L)F1823
MEMORY MAP, BANK 31
Bank 31
FA0h
Unimplemented
Read as 0
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
Legend:
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
STKPTR
TOSL
TOSH
= Unimplemented data memory locations,
read as 0.
DS40001413D-page 26
3.2.6
PIC12(L)F1822
PIC16(L)F1823
Bank(s)
Page No.
27
28
29
30
31
32
33
34
35
9-30
36
31
37
PIC12(L)F1822/16(L)F1823
TABLE 3-8:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 0
000h(1)
INDF0
001h(1)
INDF1
002h(1)
PCL
003h(1)
STATUS
004h(1)
FSR0L
005h(1)
FSR0H
006h(1)
FSR1L
007h(1)
FSR1H
008h(1)
BSR
009h(1)
WREG
00Ah(1)
PCLATH
00Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
00Ch
PORTA
RA5
RA4
RA3
RA2
RA1
RA0
RC5
RC4
RC3
RC2
RC1
RC0
PD
DC
BSR<4:0>
Working Register
00Dh
00Eh
PORTC(2)
00Fh
Unimplemented
010h
Unimplemented
011h
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
012h
PIR2
OSFIF
C2IF(2)
C1IF
EEIF
BCL1IF
013h
Unimplemented
014h
Unimplemented
015h
TMR0
016h
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
017h
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
018h
T1CON
TMR1CS1
TMR1CS0
019h
T1GCON
TMR1GE
T1GPOL
01Ah
TMR2
01Bh
PR2
01Ch
T2CON
Unimplemented
T1CKPS<1:0>
T1GTM
T1GSPM
T1OSCEN
T1SYNC
T1GGO/
DONE
T1GVAL
TMR2ON
CPSCON0
CPSON
CPSRM
CPSRNG<1:0>
01Fh
CPSCON1
CPSCH<3:2>(2)
1:
2:
3:
4:
TMR1ON
T1GSS<1:0>
01Eh
Note
01Dh
Legend:
T2CKPS<1:0>
Unimplemented
CPSOUT
T0XCS
CPSCH<1:0>
DS40001413D-page 27
PIC12(L)F1822/16(L)F1823
TABLE 3-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 1
080h(1)
INDF0
081h(1)
INDF1
082h(1)
PCL
083h(1)
STATUS
084h(1)
FSR0L
085h(1)
FSR0H
086h(1)
FSR1L
087h(1)
FSR1H
088h(1)
BSR
089h(1)
WREG
08Ah(1)
PCLATH
08Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
08Ch
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
TO
PD
DC
BSR<4:0>
Working Register
08Dh
08Eh
TRISC(2)
08Fh
Unimplemented
090h
Unimplemented
091h
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
092h
PIE2
OSFIE
C2IE(2)
C1IE
EEIE
BCL1IE
093h
Unimplemented
094h
Unimplemented
095h
OPTION_REG
WPUEN
INTEDG
TMR0CS
TMR0SE
STKOVF
STKUNF
Unimplemented
096h
PCON
097h
WDTCON
098h
OSCTUNE
099h
OSCCON
SPLLEN
OSCSTAT
09Bh
ADRESL
09Ch
ADRESH
09Dh
ADCON0
09Eh
ADCON1
ADFM
09Fh
Note
1:
2:
3:
4:
PSA
PLLR
PS<2:0>
RMCLR
RI
POR
WDTPS<4:0>
OSTS
HFIOFR
BOR
SWDTEN
HFIOFL
SCS<1:0>
MFIOFR
LFIOFR
HFIOFS
CHS<4:0>
ADCS<2:0>
GO/DONE
ADON
ADPREF<1:0>
Unimplemented
DS40001413D-page 28
TUN<5:0>
IRCF<3:0>
09Ah
Legend:
T1OSCR
PIC12(L)F1822/16(L)F1823
TABLE 3-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 2
100h(1)
INDF0
101h(1)
INDF1
102h(1)
PCL
103h(1)
STATUS
104h(1)
FSR0L
105h(1)
FSR0H
106h(1)
FSR1L
107h(1)
FSR1H
108h(1)
BSR
109h(1)
WREG
10Ah(1)
PCLATH
10Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
10Ch
LATA
LATA5
LATA4
LATA2
LATA1
LATA0
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
TO
PD
DC
BSR<4:0>
Working Register
10Dh
10Eh
LATC(2)
10Fh
Unimplemented
110h
Unimplemented
111h
CM1CON0
C1ON
C1OUT
112h
CM1CON1
C1INTP
C1INTN
C2ON
C2OUT
C2INTP
C2INTN
Unimplemented
(2)
C1OE
C1POL
C1SP
C1HYS
C2SP
MC2OUT(2)
MC1OUT
BORRDY
C1PCH<1:0>
113h
CM2CON0
114h
CM2CON1(2)
115h
CMOUT
116h
BORCON
SBOREN
117h
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
118h
DACCON0
DACEN
DACLPS
DACOE
DACPSS<1:0>
C2OE
C2POL
C2PCH<1:0>
C1SYNC
C1NCH1(2)
C1NCH0
C2HYS
C2SYNC
C2NCH<1:0>
ADFVR<1:0>
119h
DACCON1
11Ah
SRCON0
SRLEN
11Bh
SRCON1
SRSPE
11Ch
11Dh
APFCON
11Eh
Unimplemented
11Fh
Unimplemented
Legend:
Note
1:
2:
3:
4:
DACR<4:0>
SRCLK<2:0>
SRSCKE
SRQEN
SRNQEN
SRPS
SRPR
SRRC2E
SRRC1E
CCP1SEL
SRSC2E(2)
SRSC1E
SRRPE
SRRCKE
SSSEL
---
T1GSEL
TXCKSEL P1BSEL(4)
(2)
Unimplemented
RXDTSEL
SDOSEL
(4)
DS40001413D-page 29
PIC12(L)F1822/16(L)F1823
TABLE 3-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 3
180h(1)
INDF0
181h(1)
INDF1
182h(1)
PCL
183h(1)
STATUS
184h(1)
FSR0L
185h(1)
FSR0H
186h(1)
FSR1L
187h(1)
FSR1H
188h(1)
BSR
189h(1)
WREG
18Ah(1)
PCLATH
18Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
18Ch
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
ANSC3
ANSC2
ANSC1
ANSC0
TO
PD
DC
BSR<4:0>
Working Register
18Dh
18Eh
ANSELC(2)
18Fh
Unimplemented
190h
Unimplemented
191h
EEADRL
192h
EEADRH
193h
EEDATL
194h
EEDATH
195h
EECON1
196h
EECON2
197h
Unimplemented
198h
Unimplemented
199h
RCREG
19Ah
TXREG
19Bh
SPBRGL
19Ch
SPBRGH
19Dh
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
19Eh
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
19Fh
BAUDCON
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
Legend:
Note
1:
2:
3:
4:
Unimplemented
(3)
EEPGD
CFGS
FREE
WRERR
WREN
WR
DS40001413D-page 30
PIC12(L)F1822/16(L)F1823
TABLE 3-8:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 4
200h(1)
INDF0
201h(1)
INDF1
202h(1)
PCL
203h(1)
STATUS
204h(1)
FSR0L
205h(1)
FSR0H
206h(1)
FSR1L
207h(1)
FSR1H
208h(1)
BSR
209h(1)
WREG
20Ah(1)
PCLATH
20Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
20Ch
WPUA
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
TO
PD
DC
BSR<4:0>
Working Register
20Dh
20Eh
WPUC(2)
20Fh
Unimplemented
210h
Unimplemented
211h
SSP1BUF
Unimplemented
212h
SSP1ADD
ADD<7:0>
213h
SSP1MSK
MSK<7:0>
214h
SSP1STAT
SMP
CKE
D/A
215h
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
216h
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
217h
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
218h
Unimplemented
219h
Unimplemented
21Ah
Unimplemented
21Bh
Unimplemented
21Ch
Unimplemented
21Dh
Unimplemented
21Eh
Unimplemented
21Fh
Unimplemented
Legend:
Note
1:
2:
3:
4:
R/W
UA
BF
SSPM<3:0>
DS40001413D-page 31
PIC12(L)F1822/16(L)F1823
TABLE 3-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 5
280h(1)
INDF0
281h(1)
INDF1
282h(1)
PCL
283h(1)
STATUS
284h(1)
FSR0L
285h(1)
FSR0H
286h(1)
FSR1L
287h(1)
FSR1H
288h(1)
BSR
289h(1)
WREG
28Ah(1)
PCLATH
28Bh(1)
INTCON
GIE
28Ch
Unimplemented
28Dh
Unimplemented
28Eh
Unimplemented
28Fh
Unimplemented
290h
Unimplemented
291h
CCPR1L
292h
CCPR1H
293h
CCP1CON
294h
PWM1CON
295h
CCP1AS
296h
PSTR1CON
297h
Unimplemented
298h
Unimplemented
299h
Unimplemented
29Ah
Unimplemented
29Bh
Unimplemented
29Ch
Unimplemented
29Dh
Unimplemented
29Eh
Unimplemented
29Fh
Unimplemented
Legend:
Note
1:
2:
3:
4:
PD
DC
BSR<4:0>
Working Register
P1M<1:0>
TMR0IE
INTE
IOCIE
INTF
IOCIF
DC1B<1:0>
CCP1M<3:0>
P1DC<6:0>
CCP1ASE
CCP1AS<2:0>
P1RSEN
PSS1AC<1:0>
STR1SYNC
STR1D
PSS1BD<1:0>
STR1C
STR1B
STR1A
DS40001413D-page 32
PIC12(L)F1822/16(L)F1823
TABLE 3-8:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 6
300h(1)
INDF0
301h(1)
INDF1
302h(1)
PCL
303h(1)
STATUS
304h(1)
FSR0L
305h(1)
FSR0H
306h(1)
FSR1L
307h(1)
FSR1H
308h(1)
BSR
309h(1)
WREG
30Ah(1)
PCLATH
30Bh(1)
INTCON
GIE
30Ch
Unimplemented
30Dh
Unimplemented
30Eh
Unimplemented
30Fh
Unimplemented
310h
Unimplemented
311h
Unimplemented
312h
Unimplemented
313h
Unimplemented
314h
Unimplemented
315h
Unimplemented
316h
Unimplemented
317h
Unimplemented
318h
Unimplemented
319h
Unimplemented
31Ah
Unimplemented
31Bh
Unimplemented
31Ch
Unimplemented
31Dh
Unimplemented
31Eh
Unimplemented
31Fh
Unimplemented
Legend:
Note
1:
2:
3:
4:
PD
DC
BSR<4:0>
Working Register
TMR0IE
INTE
IOCIE
INTF
IOCIF
DS40001413D-page 33
PIC12(L)F1822/16(L)F1823
TABLE 3-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 7
380h(1)
INDF0
381h(1)
INDF1
382h(1)
PCL
383h(1)
STATUS
384h(1)
FSR0L
385h(1)
FSR0H
386h(1)
FSR1L
387h(1)
FSR1H
388h(1)
BSR
389h(1)
WREG
38Ah(1)
PCLATH
38Bh(1)
INTCON
GIE
38Ch
Unimplemented
38Dh
Unimplemented
38Eh
Unimplemented
38Fh
Unimplemented
390h
Unimplemented
391h
IOCAP
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
392h
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
393h
IOCAF
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
394h
Unimplemented
395h
Unimplemented
396h
Unimplemented
397h
Unimplemented
398h
Unimplemented
399h
Unimplemented
39Ah
CLKRCON
CLKREN
39Bh
MDCON
MDEN
39Dh
MDSRC
MDMSODIS
39Eh
MDCARL
MDCLODIS
39Fh
MDCARH
MDCHODIS
Note
1:
2:
3:
4:
PD
DC
BSR<4:0>
Working Register
39Ch
Legend:
CLKROE
TMR0IE
CLKRSLR
INTE
IOCIE
CLKRDC<1:0>
INTF
IOCIF
CLKRDIV<2:0>
Unimplemented
MDOE
MDOUT
MDOPOL
MDMS<3:0>
MDCLPOL
MDCLSYNC
MDCL<3:0>
MDCHPOL MDCHSYNC
MDCH<3:0>
MDBIT
DS40001413D-page 34
MDSLR
PIC12(L)F1822/16(L)F1823
TABLE 3-8:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 8
400h(1)
INDF0
401h(1)
INDF1
402h(1)
PCL
403h(1)
STATUS
404h(1)
FSR0L
405h(1)
FSR0H
406h(1)
FSR1L
407h(1)
FSR1H
408h(1)
BSR
409h(1)
WREG
40Ah(1)
PCLATH
40Bh(1)
INTCON
GIE
40Ch
Unimplemented
40Dh
Unimplemented
40Eh
Unimplemented
40Fh
Unimplemented
410h
Unimplemented
411h
Unimplemented
412h
Unimplemented
413h
Unimplemented
414h
Unimplemented
415h
Unimplemented
416h
Unimplemented
417h
Unimplemented
418h
Unimplemented
419h
Unimplemented
41Ah
Unimplemented
41Bh
Unimplemented
41Ch
Unimplemented
41Dh
Unimplemented
41Eh
Unimplemented
41Fh
Unimplemented
Legend:
Note
1:
2:
3:
4:
PD
DC
BSR<4:0>
Working Register
TMR0IE
INTE
IOCIE
INTF
IOCIF
DS40001413D-page 35
PIC12(L)F1822/16(L)F1823
TABLE 3-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Banks 9-30
x00h/
x80h(1)
INDF0
x00h/
x81h(1)
INDF1
x02h/
x82h(1)
PCL
x03h/
x83h(1)
STATUS
x04h/
x84h(1)
FSR0L
x05h/
x85h(1)
FSR0H
x06h/
x86h(1)
FSR1L
x07h/
x87h(1)
FSR1H
x08h/
x88h(1)
BSR
x09h/
x89h(1)
WREG
x0Ah/
x8Ah(1)
PCLATH
x0Bh/
x8Bh(1)
INTCON
GIE
x0Ch/
x8Ch
x1Fh/
x9Fh
Legend:
Note
1:
2:
3:
4:
TO
PD
DC
BSR<4:0>
Working Register
TMR0IE
INTE
IOCIE
Unimplemented
INTF
IOCIF
DS40001413D-page 36
PIC12(L)F1822/16(L)F1823
TABLE 3-8:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 31
F80h(1)
INDF0
F81h(1)
INDF1
F82h(1)
PCL
F83h(1)
STATUS
F84h(1)
FSR0L
F85h(1)
FSR0H
F86h(1)
FSR1L
F87h(1)
FSR1H
F88h(1)
BSR
F89h(1)
WREG
F8Ah(1)
PCLATH
F8Bh(1)
INTCON
GIE
F8Ch
FE3h
FE4h
STATUS_
PD
DC
BSR<4:0>
Working Register
TMR0IE
INTE
IOCIE
INTF
IOCIF
Unimplemented
Z_SHAD
DC_SHAD
C_SHAD
SHAD
FE5h
WREG_
SHAD
FE6h
BSR_
SHAD
FE7h
PCLATH_
SHAD
FE8h
FSR0L_
SHAD
FE9h
FSR0H_
SHAD
FEAh
FSR1L_
SHAD
FEBh
FSR1H_
SHAD
FECh
FEDh
STKPTR
FEEh
TOSL
FEFh
TOSH
Legend:
Note
1:
2:
3:
4:
Unimplemented
DS40001413D-page 37
PIC12(L)F1822/16(L)F1823
3.3
3.3.3
FIGURE 3-3:
PC
LOADING OF PC IN
DIFFERENT SITUATIONS
14
PCH
14
PCH
PCL
PCLATH
PC
ALU Result
PCL
11
OPCODE <10:0>
PC
14
PCLATH
PC
Instruction with
PCL as
Destination
GOTO, CALL
PCLATH
14
PCH
PCL
PCH
CALLW
W
PCL
BRW
14
PCH
3.3.4
BRANCHING
15
PC + W
PC
The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
PCL
0
BRA
15
PC + OPCODE <8:0>
3.3.1
MODIFYING PCL
3.3.2
COMPUTED GOTO
DS40001413D-page 38
PIC12(L)F1822/16(L)F1823
3.4
Stack
3.4.1
Note:
FIGURE 3-4:
TOSH:TOSL
0x0F
STKPTR = 0x1F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
TOSH:TOSL
0x1F
0x0000
STKPTR = 0x1F
DS40001413D-page 39
PIC12(L)F1822/16(L)F1823
FIGURE 3-5:
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL
FIGURE 3-6:
0x00
Return Address
STKPTR = 0x00
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
TOSH:TOSL
DS40001413D-page 40
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
STKPTR = 0x06
PIC12(L)F1822/16(L)F1823
FIGURE 3-7:
TOSH:TOSL
3.4.2
0x0F
Return Address
0x0E
Return Address
0x0D
Return Address
0x0C
Return Address
0x0B
Return Address
0x0A
Return Address
0x09
Return Address
0x08
Return Address
0x07
Return Address
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
STKPTR = 0x10
OVERFLOW/UNDERFLOW RESET
3.5
Indirect Addressing
DS40001413D-page 41
PIC12(L)F1822/16(L)F1823
FIGURE 3-8:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x1000
0x1FFF
0x0FFF
Reserved
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR
Address
Range
0x7FFF
0x8000
Reserved
0x0000
Program
Flash Memory
0xFFFF
Note:
0x7FFF
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
DS40001413D-page 42
PIC12(L)F1822/16(L)F1823
3.5.1
FIGURE 3-9:
BSR
Indirect Addressing
From Opcode
7
0
Bank Select
Location Select
0x00
FSRxH
0
FSRxL
0
Bank Select
11111
Bank 31
Location Select
0x7F
DS40001413D-page 43
PIC12(L)F1822/16(L)F1823
3.5.2
3.5.3
FIGURE 3-10:
7
FSRnH
0 0 1
FSRnL
FIGURE 3-11:
7
1
FSRnH
PROGRAM FLASH
MEMORY MAP
0
Location Select
Location Select
0x2000
FSRnL
0x8000
0x0000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x29AF
DS40001413D-page 44
0xF6F
0xFFFF
0x7FFF
PIC12(L)F1822/16(L)F1823
4.0
DEVICE CONFIGURATION
4.1
Configuration Words
DS40001413D-page 45
PIC12(L)F1822/16(L)F1823
REGISTER 4-1:
CONFIGURATION WORD 1
R/P-1/1
R/P-1/1
R/P-1/1
FCMEN
IESO
CLKOUTEN
R/P-1/1
R/P-1/1
BOREN<1:0>
bit 13
R/P-1/1
R/P-1/1
R/P-1/1
CP
MCLRE
PWRTE
R/P-1/1
CPD
bit 8
R/P-1/1
R/P-1/1
WDTE<1:0>
R/P-1/1
R/P-1/1
R/P-1/1
FOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
0 = Bit is cleared
1 = Bit is set
bit 13
bit 12
bit 11
bit 10-9
bit 8
bit 7
bit 6
bit 5
bit 4-3
Note 1:
2:
3:
DS40001413D-page 46
PIC12(L)F1822/16(L)F1823
REGISTER 4-1:
bit 2-0
Note 1:
2:
3:
DS40001413D-page 47
PIC12(L)F1822/16(L)F1823
REGISTER 4-2:
CONFIGURATION WORD 2
R/P-1/1
R/P-1/1
U-1
R/P-1/1
R/P-1/1
R/P-1/1
LVP(1)
DEBUG(2)
BORV
STVREN
PLLEN
bit 13
bit 8
U-1
U-1
U-1
R-1
U-1
U-1
Reserved
R/P-1/1
R/P-1/1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
0 = Bit is cleared
1 = Bit is set
bit 13
bit 12
bit 11
Unimplemented: Read as 1
bit 10
bit 9
bit 8
bit 7-5
Unimplemented: Read as 1
bit 4
bit 3-2
Unimplemented: Read as 1
bit 1-0
Note 1:
2:
3:
The LVP bit cannot be programmed to 0 when Programming mode is entered via LVP.
The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and
programmers. For normal device operation, this bit should be maintained as a '1'.
See Vbor parameter for specific trip point voltages.
DS40001413D-page 48
PIC12(L)F1822/16(L)F1823
4.2
Code Protection
4.2.1
4.2.2
4.3
Write Protection
4.4
User ID
DS40001413D-page 49
PIC12(L)F1822/16(L)F1823
4.5
REGISTER 4-3:
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 13
bit 8
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Readable bit
0 = Bit is cleared
bit 13-5
bit 4-0
1 = Bit is set
DS40001413D-page 50
PIC12(L)F1822/16(L)F1823
5.0
5.1
Overview
DS40001413D-page 51
PIC12(L)F1822/16(L)F1823
SIMPLIFIED PIC MCU CLOCK SOURCE BLOCK DIAGRAM
FIGURE 5-1:
External
Oscillator
OSC2
Sleep
4 x PLL
Oscillator Timer1
FOSC<2:0> = 100
T1OSO
T1OSCEN
Enable
Oscillator
IRCF<3:0>
HFPLL
500 kHz
Source
16 MHz
(HFINTOSC)
Postscaler
Internal
Oscillator
Block
500 kHz
(MFINTOSC)
31 kHz
Source
31 kHz
31 kHz (LFINTOSC)
DS40001413D-page 52
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
MUX
T1OSI
Sleep
T1OSC
MUX
OSC1
CPU and
Peripherals
Internal Oscillator
Clock
Control
FOSC<2:0> SCS<1:0>
Clock Source Option
for other modules
PIC12(L)F1822/16(L)F1823
5.2
5.2.1
FIGURE 5-2:
OSC1/CLKIN
Clock from
Ext. System
PIC MCU
FOSC/4 or I/O(1)
Note 1:
OSC2/CLKOUT
5.2.1.1
EC Mode
5.2.1.2
DS40001413D-page 53
PIC12(L)F1822/16(L)F1823
FIGURE 5-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 5-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
PIC MCU
PIC MCU
OSC1/CLKIN
C1
C1
To Internal
Logic
Quartz
Crystal
C2
OSC1/CLKIN
RS(1)
RF(2)
Sleep
RP(3)
OSC2/CLKOUT
Note 1:
2:
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
AN826, Crystal Oscillator Basics and
Crystal Selection for rfPIC and PIC
Devices (DS00826)
AN849, Basic PIC Oscillator Design
(DS00849)
AN943, Practical PIC Oscillator
Analysis and Design (DS00943)
AN949, Making Your Oscillator Work
(DS00949)
To Internal
Logic
C2 Ceramic
RS(1)
Resonator
Note 1:
RF(2)
Sleep
OSC2/CLKOUT
5.2.1.3
5.2.1.4
4X PLL
DS40001413D-page 54
PIC12(L)F1822/16(L)F1823
5.2.1.5
5.2.1.6
TIMER1 Oscillator
External RC Mode
The Timer1 Oscillator can be used as an alternate system clock source and can be selected during run-time
using clock switching. Refer to Section 5.3 Clock
Switching for more information.
FIGURE 5-5:
QUARTZ CRYSTAL
OPERATION (TIMER1
OSCILLATOR)
FIGURE 5-6:
VDD
PIC
MCU
PIC MCU
REXT
OSC1/CLKIN
T1OSI
C1
To Internal
Logic
32.768 kHz
Quartz
Crystal
Internal
Clock
CEXT
VSS
FOSC/4 or I/O(1)
C2
EXTERNAL RC MODES
OSC2/CLKOUT
T1OSO
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
AN826, Crystal Oscillator Basics and
Crystal Selection for rfPIC and PIC
Devices (DS00826)
AN849, Basic PIC Oscillator Design
(DS00849)
AN943, Practical PIC Oscillator
Analysis and Design (DS00943)
AN949, Making Your Oscillator Work
(DS00949)
TB097, Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS (DS91097)
AN1288, Design Practices for
Low-Power External Oscillators
(DS01288)
Note 1:
DS40001413D-page 55
PIC12(L)F1822/16(L)F1823
5.2.2
The device may be configured to use the internal oscillator block as the system clock by performing one of the
following actions:
Program the FOSC<2:0> bits in Configuration
Word 1 to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run-time. See Section 5.3
Clock Switchingfor more information.
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.
The function of the OSC2/CLKOUT pin is determined
by the state of the CLKOUTEN bit in Configuration
Word 1.
The internal oscillator block has two independent
oscillators and a dedicated Phase-Locked Loop,
HFPLL that can produce one of three internal system
clock sources.
1.
2.
3.
5.2.2.1
HFINTOSC
5.2.2.2
MFINTOSC
The
Medium-Frequency
Internal
Oscillator
(MFINTOSC) is a factory calibrated 500 kHz internal
clock source. The frequency of the MFINTOSC can be
altered via software using the OSCTUNE register
(Register 5-3).
The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.7 Internal
Oscillator Clock Switch Timing for more information.
The MFINTOSC is enabled by:
Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
FOSC<2:0> = 100, or
Set the System Clock Source (SCS) bits of the
OSCCON register to 1x
The Medium Frequency Internal Oscillator Ready bit
(MFIOFR) of the OSCSTAT register indicates when the
MFINTOSC is running and can be utilized.
DS40001413D-page 56
PIC12(L)F1822/16(L)F1823
5.2.2.3
5.2.2.4
LFINTOSC
5.2.2.5
DS40001413D-page 57
PIC12(L)F1822/16(L)F1823
5.2.2.6
DS40001413D-page 58
5.2.2.7
5.
6.
7.
PIC12(L)F1822/16(L)F1823
FIGURE 5-7:
HFINTOSC/
MFINTOSC
HFINTOSC/
MFINTOSC
Running
LFINTOSC
IRCF <3:0>
System Clock
HFINTOSC/
MFINTOSC
HFINTOSC/
MFINTOSC
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
System Clock
LFINTOSC
HFINTOSC/MFINTOSC
LFINTOSC
Oscillator Delay(1) 2-cycle Sync
Running
HFINTOSC/
MFINTOSC
IRCF <3:0>
=0
System Clock
Note 1:
DS40001413D-page 59
PIC12(L)F1822/16(L)F1823
5.3
Clock Switching
5.3.3
TIMER1 OSCILLATOR
5.3.1
5.3.4
5.3.2
DS40001413D-page 60
PIC12(L)F1822/16(L)F1823
5.4
5.4.1
TABLE 5-1:
Switch From
Switch To
Frequency
Oscillator Delay
LFINTOSC(1)
Sleep/POR
MFINTOSC(1)
HFINTOSC(1)
31 kHz
31.25 kHz-500 kHz
31.25 kHz-16 MHz
Sleep/POR
EC, RC(1)
DC 32 MHz
2 cycles
LFINTOSC
EC,
RC(1)
DC 32 MHz
1 cycle of each
Sleep/POR
Timer1 Oscillator
LP, XT, HS(1)
32 kHz-20 MHz
MFINTOSC(1)
HFINTOSC(1)
2 s (approx.)
LFINTOSC(1)
31 kHz
1 cycle of each
Timer1 Oscillator
32 kHz
PLL inactive
PLL active
16-32 MHz
2 ms (approx.)
Note 1:
PLL inactive.
DS40001413D-page 61
PIC12(L)F1822/16(L)F1823
5.4.2
1.
2.
3.
4.
5.
6.
7.
TWO-SPEED START-UP
SEQUENCE
5.4.3
FIGURE 5-8:
TWO-SPEED START-UP
INTOSC
TOST
OSC1
1022 1023
OSC2
Program Counter
PC - N
PC
PC + 1
System Clock
DS40001413D-page 62
PIC12(L)F1822/16(L)F1823
5.5
5.5.3
FIGURE 5-9:
External
Clock
LFINTOSC
Oscillator
64
31 kHz
(~32 s)
488 Hz
(~2 ms)
Sample Clock
5.5.4
Clock
Failure
Detected
FAIL-SAFE DETECTION
5.5.2
5.5.1
FAIL-SAFE OPERATION
DS40001413D-page 63
PIC12(L)F1822/16(L)F1823
FIGURE 5-10:
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Note:
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
DS40001413D-page 64
PIC12(L)F1822/16(L)F1823
5.6
REGISTER 5-1:
R/W-0/0
R/W-1/1
SPLLEN
R/W-1/1
IRCF<3:0>
R/W-1/1
U-0
R/W-0/0
R/W-0/0
SCS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-3
bit 2
Unimplemented: Read as 0
bit 1-0
Note 1:
DS40001413D-page 65
PIC12(L)F1822/16(L)F1823
REGISTER 5-2:
R-1/q
R-0/q
R-q/q
R-0/q
R-0/q
R-q/q
R-0/0
R-0/q
T1OSCR
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
q = Conditional
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001413D-page 66
PIC12(L)F1822/16(L)F1823
REGISTER 5-3:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TUN<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
000001 =
000000 = Oscillator module is running at the factory-calibrated frequency.
111111 =
TABLE 5-2:
Name
Bit 7
OSCCON
SPLLEN
OSCSTAT
T1OSCR
OSCTUNE
PIE2
Legend:
Note 1:
OSTS
Bit 3
Bit 2
HFIOFR
HFIOFL
MFIOFR
BCL1IE
IRCF<3:0>
C1IE
EEIE
OSFIF
(1)
C1IF
EEIF
C2IF
Bit 1
C2IE(1)
Bit 0
SCS<1:0>
T1CKPS<1:0>
Register
on Page
65
LFIOFR
HFIOFS
BCL1IF
90
T1OSCEN
T1SYNC
TMR1ON
173
TUN<5:0>
TMR1CS<1:0>
66
67
88
= unimplemented location, read as 0. Shaded cells are not used by clock sources.
PIC16(L)F1823 only.
TABLE 5-3:
CONFIG1
PLLR
Bit 4
T1CON
Name
Bit 5
OSFIE
PIR2
Legend:
Note 1:
Bit 6
Bits
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
FCMEN
7:0
CP
MCLRE
PWRTE
Bit 10/2
Bit 9/1
BOREN<1:0>
WDTE<1:0>
FOSC<2:0>
Bit 8/0
CPD
Register
on Page
46
= unimplemented location, read as 0. Shaded cells are not used by clock sources.
PIC12F1822/16F1823 only.
DS40001413D-page 67
PIC12(L)F1822/16(L)F1823
6.0
6.3
6.3.1
6.1
OSCILLATOR MODES
6.3.2
CLKOUT FUNCTION
6.4
Slew Rate
6.2
Effects of a Reset
DS40001413D-page 68
PIC12(L)F1822/16(L)F1823
REGISTER 6-1:
R/W-0/0
R/W-0/0
R/W-1/1
CLKREN
CLKROE
CLKRSLR
R/W-1/1
R/W-0/0
R/W-0/0
CLKRDC<1:0>
R/W-0/0
R/W-0/0
CLKRDIV<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4-3
bit 2-0
Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.
2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%
is selected.
3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration
Word 1 = 0 will result in FOSC/4. See Section 6.3 Conflicts with the CLKR pin for details.
DS40001413D-page 69
PIC12(L)F1822/16(L)F1823
TABLE 6-1:
Name
CLKRCON
Legend:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CLKREN
CLKROE
CLKRSLR
CLKRDC1
CLKRDC0
CLKRDIV2
CONFIG1
Legend:
Bit 0
CLKRDIV1 CLKRDIV0
Register
on Page
69
= unimplemented locations read as 0. Shaded cells are not used by reference clock sources.
TABLE 6-2:
Name
Bit 1
Bits
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
FCMEN
IESO
CLKOUTEN
BOREN1
BOREN0
CPD
7:0
CP
MCLRE
PWRTE
WDTE1
WDTE0
FOSC2
FOSC1
FOSC0
Register
on Page
46
= unimplemented locations read as 0. Shaded cells are not used by reference clock sources.
DS40001413D-page 70
PIC12(L)F1822/16(L)F1823
7.0
RESETS
FIGURE 7-1:
MCLR
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
Brown-out
Reset
BOR
Enable
PWRT
Zero
LFINTOSC
64 ms
PWRTEN
DS40001413D-page 71
PIC12(L)F1822/16(L)F1823
7.1
7.2
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
7.1.1
TABLE 7-1:
Device Mode
BOR Mode
Device
Device
Operation upon
Operation upon
wake- up from
release of POR
Sleep
BOR_ON (11)
Active
BOR_NSLEEP (10)
Awake
Active
BOR_NSLEEP (10)
Sleep
Disabled
BOR_SBOREN (01)
Active
Begins immediately
BOR_SBOREN (01)
Disabled
Begins immediately
BOR_OFF (00)
Disabled
Begins immediately
BOREN
Config bits
Note 1:
In these specific cases, Release of POR and Wake-up from Sleep, there is no delay in start-up. The
BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the
BOR circuit is forced on by the BOREN<1:0> bits.
7.2.1
BOR IS ALWAYS ON
7.2.2
DS40001413D-page 72
PIC12(L)F1822/16(L)F1823
7.2.3
FIGURE 7-2:
BROWN-OUT READY
SBOREN
TBORRDY
BORRDY
FIGURE 7-3:
BROWN-OUT SITUATIONS
VDD
Internal
Reset
VBOR
TPWRT(1)
VDD
Internal
Reset
VBOR
< TPWRT
TPWRT(1)
VDD
Internal
Reset
Note 1:
VBOR
TPWRT(1)
DS40001413D-page 73
PIC12(L)F1822/16(L)F1823
REGISTER 7-1:
R/W-1/u
U-0
U-0
U-0
U-0
U-0
U-0
R-q/u
SBOREN
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-1
Unimplemented: Read as 0
bit 0
DS40001413D-page 74
PIC12(L)F1822/16(L)F1823
7.3
MCLR
7.8
Power-Up Timer
TABLE 7-2:
MCLR CONFIGURATION
MCLRE
LVP
MCLR
Disabled
Enabled
Enabled
7.3.1
MCLR ENABLED
7.3.2
MCLR DISABLED
7.4
7.9
Start-up Sequence
The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See
Section 5.0 Oscillator Module (With Fail-Safe
Clock Monitor) for more information.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low long
enough, the Power-up Timer and oscillator start-up
timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see Figure 7-4). This
is useful for testing purposes or to synchronize more
than one device operating in parallel.
7.5
RESET Instruction
7.6
7.7
DS40001413D-page 75
PIC12(L)F1822/16(L)F1823
FIGURE 7-4:
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Internal Oscillator
Oscillator
FOSC
FOSC
DS40001413D-page 76
PIC12(L)F1822/16(L)F1823
7.10
TABLE 7-3:
STKOVF STKUNF
RMCLR
RI
POR
BOR
TO
PD
Condition
Power-on Reset
Brown-out Reset
WDT Reset
TABLE 7-4:
STATUS
Register
PCON
Register
Power-on Reset
0000h
---1 1000
00-- 110x
0000h
---u uuuu
uu-- 0uuu
0000h
---1 0uuu
uu-- 0uuu
WDT Reset
0000h
---0 uuuu
uu-- uuuu
PC + 1
---0 0uuu
uu-- uuuu
Brown-out Reset
0000h
---1 1uuu
00-- 11u0
---1 0uuu
uu-- uuuu
---u uuuu
uu-- u0uu
Condition
PC + 1
(1)
0000h
0000h
---u uuuu
1u-- uuuu
0000h
---u uuuu
u1-- uuuu
DS40001413D-page 77
PIC12(L)F1822/16(L)F1823
7.11
REGISTER 7-2:
R/W/HS-0/q
R/W/HS-0/q
U-0
U-0
R/W/HC-1/q
R/W/HC-1/q
R/W/HC-q/u
R/W/HC-q/u
STKOVF
STKUNF
RMCLR
RI
POR
BOR
bit 7
bit 0
Legend:
HC = Bit is cleared by hardware
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS40001413D-page 78
PIC12(L)F1822/16(L)F1823
TABLE 7-5:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON
SBOREN
BORRDY
74
PCON
STKOVF
STKUNF
RMCLR
RI
POR
BOR
78
STATUS
TO
PD
DC
20
WDTCON
WDTPS4
WDTPS3
WDTPS2
WDTPS1
WDTPS0 SWDTEN
97
Legend: = unimplemented bit, reads as 0. Shaded cells are not used by Resets.
DS40001413D-page 79
PIC12(L)F1822/16(L)F1823
8.0
INTERRUPTS
Operation
Interrupt Latency
Interrupts During Sleep
INT Pin
Automatic Context Saving
FIGURE 8-1:
INTERRUPT LOGIC
Interrupt to CPU
INTE
IOCIF
IOCIE
From Peripheral Interrupt
Logic (Figure 8-2)
PEIE
GIE
DS40001413D-page 80
PIC12(L)F1822/16(L)F1823
FIGURE 8-2:
TMR1GIF
TMR1GIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR1IF
TMR1IE
To Interrupt Logic
(Figure 8-1)
TMR2IF
TMR2IE
EEIF
EEIE
OSFIF
OSFIE
C1IF
C1IE
C2IF(1)
C2IE(1)
BCLIF
BCLIE
Note 1:
PIC16(L)F1823 only.
DS40001413D-page 81
PIC12(L)F1822/16(L)F1823
8.1
Operation
8.2
Interrupt Latency
The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will
be set, regardless of the status of the GIE, PEIE and
individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
Current prefetched instruction is flushed
GIE bit is cleared
Current Program Counter (PC) is pushed onto the
stack
Critical registers are automatically saved to the
shadow registers (See Section 8.5 Automatic
Context Saving.)
PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupts
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
DS40001413D-page 82
PIC12(L)F1822/16(L)F1823
FIGURE 8-3:
INTERRUPT LATENCY
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT
Interrupt Sampled
during Q1
Interrupt
GIE
PC
Execute
PC-1
PC
1 Cycle Instruction at PC
PC+1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
PC+1/FSR
ADDR
New PC/
PC+1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
FSR ADDR
PC+1
PC+2
0004h
0005h
INST(PC)
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
FSR ADDR
PC+1
0004h
0005h
INST(PC)
NOP
NOP
Inst(0004h)
Interrupt
GIE
PC
Execute
PC-1
PC
2 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
PC+2
NOP
NOP
DS40001413D-page 83
PIC12(L)F1822/16(L)F1823
FIGURE 8-4:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF
(5)
GIE
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
PC
Inst (PC)
Inst (PC 1)
PC + 1
Inst (PC + 1)
Inst (PC)
PC + 1
Dummy Cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
2:
Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
4:
For minimum width of INT pulse, refer to AC specifications in Section 30.0 Electrical Specifications.
5:
DS40001413D-page 84
PIC12(L)F1822/16(L)F1823
8.3
8.4
INT Pin
8.5
W register
STATUS register (except for TO and PD)
BSR register
FSR registers
PCLATH register
Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the
value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the users application, other registers may also need to be saved.
DS40001413D-page 85
PIC12(L)F1822/16(L)F1823
8.5.1
INTCON REGISTER
Note:
REGISTER 8-1:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCAF register
have been cleared by software.
DS40001413D-page 86
PIC12(L)F1822/16(L)F1823
8.5.2
PIE1 REGISTER
REGISTER 8-2:
Note:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001413D-page 87
PIC12(L)F1822/16(L)F1823
8.5.3
PIE2 REGISTER
REGISTER 8-3:
Note:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
OSFIE
C2IE(1)
C1IE
EEIE
BCLIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Unimplemented: Read as 0
Note 1:
PIC16(L)F1823 only.
DS40001413D-page 88
PIC12(L)F1822/16(L)F1823
8.5.4
PIR1 REGISTER
REGISTER 8-4:
Note:
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001413D-page 89
PIC12(L)F1822/16(L)F1823
8.5.5
PIR2 REGISTER
REGISTER 8-5:
Note:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
OSFIF
C2IF(1)
C1IF
EEIF
BCLIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Unimplemented: Read as 0
Note 1:
PIC16(L)F1823 only.
DS40001413D-page 90
PIC12(L)F1822/16(L)F1823
TABLE 8-1:
Name
INTCON
OPTION_REG
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS2
PS1
PS0
164
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIE2
OSFIE
C2IE(1)
C1IE
EEIE
BCL1IE
88
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
89
PIR2
OSFIF
C2IF(1)
C1IF
EEIF
BCL1IF
90
Legend:
Note 1:
DS40001413D-page 91
PIC12(L)F1822/16(L)F1823
9.0
9.1
1.
2.
3.
4.
5.
6.
1.
DS40001413D-page 92
PIC12(L)F1822/16(L)F1823
9.1.1
FIGURE 9-1:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1(1)
TOST(3)
CLKOUT(2)
Interrupt flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
Processor in
Sleep
PC
Inst(PC) = Sleep
Inst(PC - 1)
PC + 1
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
PC + 2
Dummy Cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
DS40001413D-page 93
PIC12(L)F1822/16(L)F1823
TABLE 9-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
IOCAF
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
125
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
125
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
125
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
IOCAP
PIE1
PIE2
OSFIE
PIR1
TMR1GIF
PIR2
STATUS
WDTCON
Legend:
Note 1:
OSFIF
C2IE
(1)
ADIF
C2IF
(1)
C1IE
EEIE
BCL1IE
88
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
89
C1IF
EEIF
BCL1IF
90
TO
PD
DC
20
WDTPS4
WDTPS3
WDTPS2
WDTPS1
WDTPS0
SWDTEN
97
DS40001413D-page 94
PIC12(L)F1822/16(L)F1823
10.0
WATCHDOG TIMER
FIGURE 10-1:
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
LFINTOSC
23-bit Programmable
Prescaler WDT
WDT Time-out
WDTE<1:0> = 10
Sleep
WDTPS<4:0>
DS40001413D-page 95
PIC12(L)F1822/16(L)F1823
10.1
10.3
10.2
10.2.1
WDT IS ALWAYS ON
10.2.2
10.2.3
TABLE 10-1:
by
Sleep.
See
WDTE
Config bits
SWDTEN
Device
Mode
WDT
Mode
WDT_ON (11)
Active
WDT_NSLEEP (10)
Awake
Active
WDT_NSLEEP (10)
Sleep
Disabled
WDT_SWDTEN (01)
Active
WDT_SWDTEN (01)
Disabled
WDT_OFF (00)
Disabled
TABLE 10-2:
10.4
Any Reset
CLRWDT instruction is executed
Device enters Sleep
Device wakes up from Sleep
Oscillator fail event
WDT is disabled
OST is running
10.5
Time-Out Period
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Cleared
DS40001413D-page 96
PIC12(L)F1822/16(L)F1823
REGISTER 10-1:
U-0
U-0
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
WDTPS<4:0>
bit 7
R/W-0/0
SWDTEN
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-1
bit 0
DS40001413D-page 97
PIC12(L)F1822/16(L)F1823
11.0
EECON1
EECON2
EEDATL
EEDATH
EEADRL
EEADRH
11.1
11.1.1
DS40001413D-page 98
PIC12(L)F1822/16(L)F1823
11.2
The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of
frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables
in another section do not change, it is possible to
exceed the total number of write cycles to the
EEPROM without exceeding the total number of write
cycles to a single byte. Refer to Section 30.0 Electrical Specifications. If this is the case, then a refresh
of the array must be performed. For this reason, variables that change infrequently (such as constants, IDs,
calibration, etc.) should be stored in Flash program
memory.
11.2.1
EXAMPLE 11-1:
BANKSEL EEADRL
;
MOVLW
DATA_EE_ADDR ;
MOVWF
EEADRL
;Data Memory
;Address to read
BCF
EECON1, CFGS ;Deselect Config space
BCF
EECON1, EEPGD;Point to DATA memory
BSF
EECON1, RD
;EE Read
MOVF
EEDATL, W
;W = EEDATL
Note:
11.2.2
11.2.3
11.2.4
DS40001413D-page 99
PIC12(L)F1822/16(L)F1823
Required
Sequence
EXAMPLE 11-2:
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
EEADRL
DATA_EE_ADDR
EEADRL
DATA_EE_DATA
EEDATL
EECON1, CFGS
EECON1, EEPGD
EECON1, WREN
;
;
;Data Memory Address to write
;
;Data Memory Value to write
;Deselect Configuration space
;Point to DATA memory
;Enable writes
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
BTFSC
GOTO
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
EECON1,
EECON1,
$-2
;Disable INTs.
;
;Write 55h
;
;Write AAh
;Set WR bit to begin write
;Enable Interrupts
;Disable writes
;Wait for write to complete
;Done
FIGURE 11-1:
GIE
WR
GIE
WREN
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR
PC
Flash Data
PC + 1
INSTR (PC)
INSTR(PC - 1)
executed here
EEADRH,EEADRL
INSTR (PC + 1)
BSF EECON1,RD
executed here
PC
+3
PC+3
EEDATH,EEDATL
INSTR(PC + 1)
executed here
PC + 5
PC + 4
INSTR (PC + 3)
Forced NOP
executed here
INSTR (PC + 4)
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
EEDATH
EEDATL
Register
EERHLT
DS40001413D-page 100
PIC12(L)F1822/16(L)F1823
11.3
It is important to understand the Flash program memory structure for erase and programming operations.
Flash Program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory
words. A row is the minimum block size that can be
erased by user software.
Flash program memory may only be written or erased
if the destination address is in a segment of memory
that is not write-protected, as defined in bits WRT<1:0>
of Configuration Word 2.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the EEDATH:EEDATL register pair.
Note:
11.3.1
TABLE 11-1:
Device
PIC12(L)F1822
PIC16(L)F1823
FLASH MEMORY
ORGANIZATION BY DEVICE
Erase Block
(Row) Size/
Boundary
Number of
Write Latches/
Boundary
16 words,
EEADRL<3:0>
= 0000
16 words,
EEADRL<3:0>
= 0000
DS40001413D-page 101
PIC12(L)F1822/16(L)F1823
EXAMPLE 11-3:
EEADRL
PROG_ADDR_LO
EEADRL
PROG_ADDR_HI
EEADRH
BCF
BSF
BCF
BSF
NOP
NOP
BSF
EECON1,CFGS
EECON1,EEPGD
INTCON,GIE
EECON1,RD
INTCON,GIE
;
;
;
;
;
;
;
MOVF
MOVWF
MOVF
MOVWF
EEDATL,W
PROG_DATA_LO
EEDATH,W
PROG_DATA_HI
;
;
;
;
DS40001413D-page 102
PIC12(L)F1822/16(L)F1823
11.3.2
11.3.3
DS40001413D-page 103
PIC12(L)F1822/16(L)F1823
After the BSF EECON1,WR instruction, the processor
requires two cycles to set up the write operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the write
takes place (i.e., the last word of the block write). This
is not Sleep mode as the clocks and peripherals will
FIGURE 11-2:
0 7
EEDATH
EEDATA
14
EEADRL<3:0> = 0000
14
EEADRL<3:0> = 0010
EEADRL<3:0> = 0001
Buffer Register
14
Buffer Register
14
EEADRL<3:0> = 1111
Buffer Register
Buffer Register
Program Memory
DS40001413D-page 104
PIC12(L)F1822/16(L)F1823
EXAMPLE 11-4:
Required
Sequence
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BSF
BCF
BSF
BSF
INTCON,GIE
EEADRL
ADDRL,W
EEADRL
ADDRH,W
EEADRH
EECON1,EEPGD
EECON1,CFGS
EECON1,FREE
EECON1,WREN
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
55h
EECON2
0AAh
EECON2
EECON1,WR
NOP
;
;
;
;
;
;
;
;
EECON1,WREN
INTCON,GIE
; Disable writes
; Enable interrupts
DS40001413D-page 105
PIC12(L)F1822/16(L)F1823
EXAMPLE 11-5:
;
;
;
;
;
;
;
INTCON,GIE
EEADRH
ADDRH,W
EEADRH
ADDRL,W
EEADRL
LOW DATA_ADDR
FSR0L
HIGH DATA_ADDR
FSR0H
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
EECON1,LWLO
;
;
;
;
;
;
;
;
;
;
;
;
;
;
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
EEDATL
FSR0++
EEDATH
MOVF
XORLW
ANDLW
BTFSC
GOTO
EEADRL,W
0x07
0x07
STATUS,Z
START_WRITE
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
55h
EECON2
0AAh
EECON2
EECON1,WR
;
;
;
;
;
;
;
;
Required
Sequence
LOOP
NOP
Required
Sequence
START_WRITE
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
EEADRL,F
LOOP
EECON1,LWLO
55h
EECON2
0AAh
EECON2
EECON1,WR
;
;
;
;
;
;
;
;
NOP
BCF
BSF
DS40001413D-page 106
EECON1,WREN
INTCON,GIE
PIC12(L)F1822/16(L)F1823
11.4
TABLE 11-2:
11.5
Address
Function
8000h-8003h
8006h
8007h-8008h
Read Access
Write Access
Yes
Yes
Yes
Yes
No
No
User IDs
Device ID/Revision ID
Configuration Words 1 and 2
EXAMPLE 11-3:
* This code block will read 1 word of program memory at the memory address:
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
CLRF
EEADRL
PROG_ADDR_LO
EEADRL
EEADRH
BSF
BCF
BSF
NOP
NOP
BSF
EECON1,CFGS
INTCON,GIE
EECON1,RD
INTCON,GIE
;
;
;
;
;
;
MOVF
MOVWF
MOVF
MOVWF
EEDATL,W
PROG_DATA_LO
EEDATH,W
PROG_DATA_HI
;
;
;
;
DS40001413D-page 107
PIC12(L)F1822/16(L)F1823
11.6
Write Verify
EXAMPLE 11-6:
BANKSEL EEDATL
MOVF
EEDATL, W
BSF
XORWF
BTFSS
GOTO
:
;
;EEDATL not changed
;from previous write
EECON1, RD ;YES, Read the
;value written
EEDATL, W ;
STATUS, Z ;Is data the same
WRITE_ERR ;No, handle error
;Yes, continue
DS40001413D-page 108
PIC12(L)F1822/16(L)F1823
REGISTER 11-1:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
EEDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory
REGISTER 11-2:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
EEDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 11-3:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
EEADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address
REGISTER 11-4:
U-1
R/W-0/0
(1)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
EEADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 1
bit 6-0
Note
EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address
1:
Unimplemented, read as 1.
DS40001413D-page 109
PIC12(L)F1822/16(L)F1823
REGISTER 11-5:
R/W-0/0
R/W-0/0
R/W-0/0
R/W/HC-0/0
R/W-x/q
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
EEPGD
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001413D-page 110
PIC12(L)F1822/16(L)F1823
REGISTER 11-6:
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
TABLE 11-3:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
EECON1
EEPGD
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
110
EECON2
EEADRL
EEADRL<7:0>
EEADRH
(2)
111*
109
EEADRH<6:0>
EEDATL
109
EEDATL<7:0>
109
EEDATH
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE2
OSFIE
C2IE(1)
C1IE
EEIE
BCL1IE
88
PIR2
OSFIF
C2IF(1)
C1IF
EEIF
BCL1IF
90
Legend:
*
Note 1:
2:
EEDATH<5:0>
109
= unimplemented location, read as 0. Shaded cells are not used by Data EEPROM module.
Page provides register information.
PIC16(L)F1823 only.
Unimplemented. Read as 1.
DS40001413D-page 111
PIC12(L)F1822/16(L)F1823
12.0
I/O PORTS
FIGURE 12-1:
Read LATx
Write LATx
Write PORTx
CK
VDD
Data Register
Data Bus
I/O pin
Read PORTx
To peripherals
ANSELx
VSS
Device
PIC12(L)F1822
PIC16(L)F1823
PORTC
TABLE 12-1:
TRISx
DS40001413D-page 112
PIC12(L)F1822/16(L)F1823
12.1
RX/DT
TX/CK
SDO
SS (Slave Select)
T1G
P1B
CCP1/P1A
DS40001413D-page 113
PIC12(L)F1822/16(L)F1823
REGISTER 12-1:
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
RXDTSEL
SDOSEL
SSSEL
T1GSEL
TXCKSEL
P1BSEL(1)
CCP1SEL(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Note 1:
PIC12(L)F1822 only.
DS40001413D-page 114
PIC12(L)F1822/16(L)F1823
12.2
PORTA Registers
12.2.1
ANSELA REGISTER
EXAMPLE 12-1:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
INITIALIZING PORTA
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<5:3> as inputs
;and set RA<2:0> as
;outputs
DS40001413D-page 115
PIC12(L)F1822/16(L)F1823
12.2.2
ICSPDAT
ICDDAT
DACOUT (DAC)
MDOUT (PIC12(L)F1822 only)
TX/CK (EUSART)
SDO (PIC12(L)F1822 only)
P1B (PIC12(L)F1822 only)
RA3
No output priorities. Input only pin.
RA4
1.
2.
3.
4.
5.
6.
7.
OSC2
CLKOUT
T1OSO (Timer1 Oscillator)
CLKR
TX/CK (PIC12(L)F1822 only)
SDO
P1B (PIC12(L)F1822 only)
RA5
1.
2.
3.
4.
5.
OSC1
T1OSI (Timer1 Oscillator)
SRNQ (PIC12(L)F1822 only)
RX/DT (PIC12(L)F1822 only)
CCP1/P1A (PIC12(L)F1822 only)
RA1
1.
2.
3.
4.
5.
ICSPCLK
ICDCLK
SCL (PIC12(L)F1822 only)
RX/DT (EUSART)
SCK (PIC12(L)F1822 only)
RA2
1.
2.
3.
4.
SRQ
C1OUT (Comparator)
SDA (PIC12(L)F1822 only)
CCP1/P1A (PIC12(L)F1822 only)
DS40001413D-page 116
PIC12(L)F1822/16(L)F1823
REGISTER 12-2:
U-0
U-0
R/W-x/x
R/W-x/x
R-x/x
R/W-x/x
R/W-x/x
R/W-x/x
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 12-3:
U-0
U-0
R/W-1/1
R/W-1/1
R-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
bit 2-0
DS40001413D-page 117
PIC12(L)F1822/16(L)F1823
REGISTER 12-4:
U-0
U-0
R/W-x/u
R/W-x/u
U-0
R/W-x/u
R/W-x/u
R/W-x/u
LATA5
LATA4
LATA2
LATA1
LATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 12-5:
U-0
U-0
U-0
R/W-1/1
U-0
R/W-1/1
R/W-1/1
R/W-1/1
ANSA4
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 3
Unimplemented: Read as 0
bit 2-0
ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
DS40001413D-page 118
PIC12(L)F1822/16(L)F1823
REGISTER 12-6:
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
2:
Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
TABLE 12-2:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA2
ANSA1
ANSA0
118
ANSELA
ANSA4
APFCON
RXDTSEL
SDOSEL
SSSEL
T1GSEL
LATA5
LATA4
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PORTA
RA5
RA4
RA3
RA2
RA1
RA0
117
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
WPUA
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
119
LATA
OPTION_REG
Legend:
Note 1:
CONFIG1
Legend:
LATA2
LATA1
LATA0
PS<2:0>
114
118
164
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTA.
PIC12F1822 only.
TABLE 12-3:
Name
Bits
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
FCMEN
7:0
CP
MCLRE
PWRTE
Bit 10/2
WDTE<1:0>
Bit 9/1
Bit 8/0
BOREN<1:0>
CPD
FOSC<2:0>
Register
on Page
46
DS40001413D-page 119
PIC12(L)F1822/16(L)F1823
12.3
PORTC Registers
(PIC16(L)F1823 only)
12.3.2
SCL (MSSP)
SCK (MSSP)
RC1
12.3.1
RC3
ANSELC REGISTER
EXAMPLE 12-2:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
1.
SDA (MSSP)
RC2
1.
2.
SDO (MSSP)
P1D
1.
P1C
RC4
1.
2.
3.
4.
5.
MDOUT
SRNQ
C2OUT
TX/CK
P1B
RC5
1.
2.
RX/DT
CCP1/P1A
INITIALIZING PORTC
PORTC
;
PORTC
;Init PORTC
LATC
;Data Latch
LATC
;
ANSELC
ANSELC
;Make RC<5:0> digital
TRISB
;
B00110000;Set RC<5:4> as inputs
;and RC<3:0> as outputs
TRISC
;
DS40001413D-page 120
PIC12(L)F1822/16(L)F1823
REGISTER 12-7:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 12-8:
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 12-9:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
DS40001413D-page 121
PIC12(L)F1822/16(L)F1823
REGISTER 12-10: ANSELC: PORTC ANALOG SELECT REGISTER
U-0
U-0
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
ANSC3
ANSC2
ANSC1
ANSC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3-0
ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
2:
Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
TABLE 12-4:
Name
ANSELC
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSC3
ANSC2
ANSC1
ANSC0
122
LATC2
LATC1
LATC0
LATC5
LATC4
LATC3
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PORTC
RC5
RC4
RC3
RC2
RC1
RC0
121
TRISC
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
WPUC
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
122
LATC
OPTION_REG
Legend:
Note 1:
PS<2:0>
121
164
x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by PORTC.
PIC16(L)F1823 only.
DS40001413D-page 122
PIC12(L)F1822/16(L)F1823
13.0
INTERRUPT-ON-CHANGE
13.1
13.2
13.3
13.4
EXAMPLE 13-1:
Interrupt Flags
MOVLW
XORWF
ANDWF
13.5
CLEARING
INTERRUPT FLAGS
(PORTA EXAMPLE)
0xff
IOCAF, W
IOCAF, F
Operation in Sleep
DS40001413D-page 123
PIC12(L)F1822/16(L)F1823
FIGURE 13-1:
IOCBNx
Q4Q1
CK
edge
detect
RBx
IOCBPx
data bus =
0 or 1
write IOCBFx
CK
to data bus
IOCBFx
CK
IOCIE
R
Q2
from all other
IOCBFx individual
pin detectors
Q1
Q3
Q4
Q4Q1
DS40001413D-page 124
Q1
Q1
Q2
Q2
Q2
Q3
Q4
Q4Q1
IOC interrupt
to CPU core
Q3
Q4
Q4
Q4Q1
Q4Q1
PIC12(L)F1822/16(L)F1823
REGISTER 13-1:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 13-2:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 13-3:
U-0
U-0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
DS40001413D-page 125
PIC12(L)F1822/16(L)F1823
TABLE 13-1:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
118
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
IOCAF
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
125
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
125
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
125
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
Name
IOCAP
IOCAP5
TRISA
TRISA5
Legend: = unimplemented location, read as 0. Shaded cells are not used by Interrupt-on-Change.
DS40001413D-page 126
PIC12(L)F1822/16(L)F1823
14.0
14.1
14.2
FIGURE 14-1:
CDAFVR<1:0>
FVREN
FVRRDY
2
X1
X2
X4
FVR BUFFER1
(To ADC Module)
X1
X2
X4
FVR BUFFER2
(To Comparators, DAC, CPS)
+
_
1.024V Fixed
Reference
DS40001413D-page 127
PIC12(L)F1822/16(L)F1823
REGISTER 14-1:
R/W-0/0
R-q/q
R/W-0/0
R/W-0/0
FVREN
FVRRDY(1)
TSEN
TSRNG
R/W-0/0
R/W-0/0
R/W-0/0
CDAFVR<1:0>
R/W-0/0
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3-2
bit 1-0
Note 1:
2:
TABLE 14-1:
Name
FVRCON
Legend:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR1
CDAFVR0
ADFVR1
ADFVR0
128
DS40001413D-page 128
PIC12(L)F1822/16(L)F1823
15.0
TEMPERATURE INDICATOR
MODULE
FIGURE 15-1:
VDD
TSEN
TSRNG
15.1
TEMPERATURE CIRCUIT
DIAGRAM
VOUT
ADC
MUX
ADC
n
CHS bits
(ADCON0 register)
Circuit Operation
EQUATION 15-1:
VOUT RANGES
15.2
TABLE 15-1:
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 14.0 Fixed Voltage Reference (FVR) for
more information.
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.
3.6V
1.8V
15.3
Temperature Output
15.3.1
DS40001413D-page 129
PIC12(L)F1822/16(L)F1823
16.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
FIGURE 16-1:
VDD
ADPREF = 00
ADPREF = 11
VREF+
AN0
00000
AN1
00001
AN2
00010
AN3
00011
AN4(2)
00100
AN5(2)
00101
AN6(2)
00110
AN7(2)
00111
ADPREF = 10
ADC
10
GO/DONE
Temp Indicator
DAC_output
11101
11110
FVR Buffer1
11111
CHS<4:0>
Note 1:
2:
ADFM
0 = Left Justify
1 = Right Justify
ADON(1)
16
VSS
ADRESH
ADRESL
DS40001413D-page 130
PIC12(L)F1822/16(L)F1823
16.1
ADC Configuration
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Result formatting
16.1.1
PORT CONFIGURATION
16.1.2
CHANNEL SELECTION
16.1.4
CONVERSION CLOCK
The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
16.1.3
VREF+ pin
VDD
FVR 2.048V
FVR 4.096V (Not available on LF devices)
DS40001413D-page 131
PIC12(L)F1822/16(L)F1823
TABLE 16-1:
ADC
Clock Source
ADCS<2:0>
32 MHz
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
Fosc/2
000
62.5ns(2)
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0 s
Fosc/4
100
125 ns
(2)
(2)
(2)
(2)
Fosc/8
001
0.5 s(2)
400 ns(2)
0.5 s(2)
Fosc/16
101
800 ns
800 ns
1.0 s
Fosc/32
1.0 s
010
200 ns
1.6 s
250 ns
2.0 s
Fosc/64
110
2.0 s
3.2 s
4.0 s
FRC
x11
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
Legend:
Note 1:
2:
3:
4:
1.0 s
4.0 s
1.0 s
2.0 s
8.0 s(3)
2.0 s
4.0 s
16.0 s(3)
500 ns
(3)
4.0 s
8.0 s
(3)
8.0 s
1.0-6.0 s(1,4)
16.0 s
(3)
1.0-6.0 s(1,4)
32.0 s(3)
64.0 s(3)
1.0-6.0 s(1,4)
FIGURE 16-2:
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b4
b1
b0
b6
b7
b2
b9
b8
b3
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
DS40001413D-page 132
PIC12(L)F1822/16(L)F1823
16.1.5
INTERRUPTS
16.1.6
RESULT FORMATTING
FIGURE 16-3:
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
bit 0
Unimplemented: Read as 0
MSB
(ADFM = 1)
bit 7
Unimplemented: Read as 0
LSB
bit 0
bit 7
bit 0
10-bit A/D Result
DS40001413D-page 133
PIC12(L)F1822/16(L)F1823
16.2
16.2.1
ADC Operation
STARTING A CONVERSION
16.2.2
COMPLETION OF A CONVERSION
16.2.3
TERMINATING A CONVERSION
DS40001413D-page 134
16.2.4
16.2.5
TABLE 16-2:
Device
CCP1/ECCP1
PIC12(L)F1822/16(L)F1823
CCP1
PIC12(L)F1822/16(L)F1823
16.2.6
2.
3.
4.
5.
6.
7.
8.
Configure Port:
Disable pin output driver (Refer to the TRIS
register)
Configure pin as analog (Refer to the ANSEL
register)
Configure the ADC module:
Select ADC conversion clock
Configure voltage reference
Select ADC input channel
Turn on ADC module
Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 16-1:
A/D CONVERSION
DS40001413D-page 135
PIC12(L)F1822/16(L)F1823
16.2.7
REGISTER 16-1:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CHS<4:0>
R/W-0/0
R/W-0/0
R/W-0/0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-2
bit 1
bit 0
Note 1:
2:
3:
4:
DS40001413D-page 136
PIC12(L)F1822/16(L)F1823
REGISTER 16-2:
R/W-0/0
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
ADCS<2:0>
U-0
U-0
R/W-0/0
R/W-0/0
ADPREF<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
bit 3-2
Unimplemented: Read as 0
bit 1-0
Note 1:
When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a
minimum voltage specification exists. See Section 30.0 Electrical Specifications for details.
DS40001413D-page 137
PIC12(L)F1822/16(L)F1823
REGISTER 16-3:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 16-4:
R/W-x/u
R/W-x/u
ADRES<1:0>
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
DS40001413D-page 138
PIC12(L)F1822/16(L)F1823
REGISTER 16-5:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
bit 1-0
REGISTER 16-6:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
DS40001413D-page 139
PIC12(L)F1822/16(L)F1823
16.3
EQUATION 16-1:
Assumptions:
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + Temperature - 25C 0.05s/C
The value for TC can be approximated with the following equations:
1
= V CHOLD
V AP P LI ED 1 -------------------------n+1
2
1
TC
----------
RC
V AP P LI ED 1 e = V CHOLD
Tc
---------
1
RC
;combining [1] and [2]
V AP P LI ED 1 e = V A PP LIE D 1 -------------------------n+1
2
1
T C = C HOLD R IC + R SS + R S ln(1/2047)
= 12.5pF 1k + 7k + 10k ln(0.0004885)
= 1.72 s
Therefore:
T ACQ = 2s + 1.72s + 50C- 25C 0.05s/C
= 4.97s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS40001413D-page 140
PIC12(L)F1822/16(L)F1823
FIGURE 16-4:
Analog
Input
pin
Rs
VT 0.6V
CPIN
5 pF
VA
RIC 1k
Sampling
Switch
SS Rss
I LEAKAGE(1)
VT 0.6V
CHOLD = 12.5 pF
VSS/VREF-
Legend: CHOLD
CPIN
6V
5V
VDD 4V
3V
2V
= Sample/Hold Capacitance
= Input Capacitance
RSS
= Sampling Switch
VT
= Threshold Voltage
5 6 7 8 9 10 11
Sampling Switch
(k)
FIGURE 16-5:
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
3FBh
03h
02h
01h
00h
VSS/VREF-
Zero-Scale
Transition
1.5 LSB
Full-Scale
Transition
VREF+
DS40001413D-page 141
PIC12(L)F1822/16(L)F1823
TABLE 16-3:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ADCON0
CHS4
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
136
ADCON1
ADFM
ADCS2
ADCS1
ADCS0
ADPREF1
ADPREF0
137
ADRESH
130*
ADRESL
130*
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
118
ANSELC(1)
ANSC3
ANSC2
ANSC1
ANSC0
122
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
213
DACCON0
DACEN
DACLPS
DACOE
DACPSS1
DACPSS0
146
DACCON1
FVRCON
INTCON
DACR4
DACR3
DACR2
DACR1
DACR0
146
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR1
CDAFVR0
ADFVR1
ADFVR0
128
GIE
PEIE
TMR0IE
INTE
IOCE
TMR0IF
INTF
IOCF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
89
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
TRISA
TRISC(1)
Legend:
*
Note 1:
= unimplemented read as 0. Shaded cells are not used for ADC module.
Page provides register information.
PIC16(L)F1823 only.
DS40001413D-page 142
PIC12(L)F1822/16(L)F1823
17.0
DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
17.1
EQUATION 17-1:
IF DACEN = 1
DACR 4:0
VOUT = VSOURCE+ VSOURCE- ----------------------------+ VSOURCE5
2
IF DACEN = 0 & DACLPS = 1 & DACR[4:0] = 11111
V OUT = V SOURCE +
IF DACEN = 0 & DACLPS = 0 & DACR[4:0] = 00000
V OUT = V SOURCE
VSOURCE+ = VDD or FVR BUFFER 2
VSOURCE- = VSS
17.2
17.3
DS40001413D-page 143
PIC12(L)F1822/16(L)F1823
FIGURE 17-1:
VSOURCE+
VDD
VREF+
R
R
2
R
DACEN
DACLPS
R
R
32
Steps
R
32-to-1 MUX
DACPSS<1:0>
DACR<4:0>
DAC_output
(To Comparator, CPS and
ADC Modules)
DACOUT
DACOE
VSOURCE-
FIGURE 17-2:
DAC
Module
R
Voltage
Reference
Output
Impedance
DS40001413D-page 144
DACOUT
PIC12(L)F1822/16(L)F1823
17.4
17.4.1
FIGURE 17-3:
17.4.2
VSOURCE+
VSOURCE+
R
DACR<4:0> = 11111
R
DACEN = 0
DACLPS = 1
R
DAC Voltage Ladder
(see Figure 17-1)
DACEN = 0
DACLPS = 0
VSOURCE-
17.5
DACR<4:0> = 00000
VSOURCE-
17.6
Effects of a Reset
DS40001413D-page 145
PIC12(L)F1822/16(L)F1823
REGISTER 17-1:
R/W-0/0
R/W-0/0
R/W-0/0
U-0
DACEN
DACLPS
DACOE
R/W-0/0
R/W-0/0
DACPSS<1:0>
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 3-2
00 =
01 =
10 =
11 =
bit 1-0
Unimplemented: Read as 0
REGISTER 17-2:
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DACR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
TABLE 17-1:
Name
Bit 6
FVRCON
FVREN
DACCON0
DACEN
DACCON1
Legend:
Register
on page
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FVRRDY
TSEN
TSRNG
CDAFVR1
CDAFVR0
ADFVR1
ADFVR0
128
DACLPS
DACOE
DACPSS1
DACPSS0
146
DACR4
DACR3
DACR2
DACR1
DACR0
146
DS40001413D-page 146
PIC12(L)F1822/16(L)F1823
18.0
SR LATCH
The SR latch can be used in a variety of analog applications, including oscillator circuits, one-shot circuit,
hysteretic controllers, and analog timing applications.
18.1
Latch Operation
18.2
Latch Output
The SRQEN and SRNQEN bits of the SRCON0 register control the Q and Q latch outputs. Both of the SR
latch outputs may be directly output to an I/O pin at the
same time.
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
18.3
Effects of a Reset
Upon any device Reset, the SR latch output is not initialized to a known state. The users firmware is
responsible for initializing the latch output before
enabling the output pins.
DS40001413D-page 147
PIC12(L)F1822/16(L)F1823
FIGURE 18-1:
SRPS
Pulse
Gen(2)
SRLEN
SRQEN
SRI
S
SRSPE
SRCLK
Q
SRQ
SRSCKE
(3, 4)
SYNC_C2OUT
SRSC2E(4)
SYNC_C1OUT
(3)
SR
Latch(1)
SRSC1E
SRPR
Pulse
Gen(2)
SRI
SRRPE
SRCLK
SRRCKE
(3, 4)
SYNC_C2OUT
SRRC2E(4)
SYNC_C1OUT
Q
SRNQ
SRLEN
SRNQEN
(3)
SRRC1E
Note 1:
2:
3:
4:
DS40001413D-page 148
If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
Pulse generator causes a 1 Q-state pulse width.
Name denotes the connection point at the comparator output.
PIC16(L)F1823 only.
PIC12(L)F1822/16(L)F1823
TABLE 18-1:
SRCLK
Divider
FOSC = 32 MHz
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 4 MHz
FOSC = 1 MHz
111
512
110
256
62.5 kHz
39.0 kHz
31.3 kHz
7.81 kHz
1.95 kHz
125 kHz
78.1 kHz
62.5 kHz
15.6 kHz
3.90 kHz
101
100
128
250 kHz
156 kHz
125 kHz
31.25 kHz
7.81 kHz
64
500 kHz
313 kHz
250 kHz
62.5 kHz
15.6 kHz
011
32
1 MHz
625 kHz
500 kHz
125 kHz
31.3 kHz
010
16
2 MHz
1.25 MHz
1 MHz
250 kHz
62.5 kHz
001
4 MHz
2.5 MHz
2 MHz
500 kHz
125 kHz
000
8 MHz
5 MHz
4 MHz
1 MHz
250 kHz
REGISTER 18-1:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/S-0/0
R/S-0/0
SRLEN
SRCLK2
SRCLK1
SRCLK0
SRQEN
SRNQEN
SRPS
SRPR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
DS40001413D-page 149
PIC12(L)F1822/16(L)F1823
REGISTER 18-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SRSPE
SRSCKE
SRSC2E(1)
SRSC1E
SRRPE
SRRCKE
SRRC2E(1)
SRRC1E
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
PIC16(L)F1823 only.
DS40001413D-page 150
PIC12(L)F1822/16(L)F1823
TABLE 18-2:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
118
SRCON0
SRLEN
SRCLK2
SRCLK1
SRCLK0
SRQEN
SRNQEN
SRPS
SRPR
149
SRCON1
SRSPE
SRSCKE
SRSC2E(1)
SRSC1E
SRRPE
SRRCKE
SRRC2E(1)
SRRC1E
150
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISA
Legend:
Note 1:
DS40001413D-page 151
PIC12(L)F1822/16(L)F1823
19.0
COMPARATOR MODULE
19.1
Comparator Overview
FIGURE 19-1:
SINGLE COMPARATOR
VIN+
VIN-
Output
VINVIN+
Output
Note:
DS40001413D-page 152
PIC12(L)F1822/16(L)F1823
FIGURE 19-2:
CxNCH<1:0>
C1ON(1)
C1INTP
Interrupt
det
C1IN0-
Set C1IF
0
(2)
C1IN1-
det
C1POL
C1VN
Cx(3)
C1VP
DAC_output
0
MUX
1 (2)
FVR Buffer2
C1IN+
C1OUT
MC1OUT
To Data Bus
+
EN
Q1
C1HYS
C1SP
C1SYNC
C1ON
VSS
C1INTN
Interrupt
MUX
C1PCH<1:0>
C1OE
TRIS bit
C1OUT
2
D
(from Timer1)
T1CLK
1
To Timer1 or SR Latch
sync_C1OUT
Note
1:
2:
3:
DS40001413D-page 153
PIC12(L)F1822/16(L)F1823
FIGURE 19-3:
CxNCH<1:0>
CxON(1)
CxINTP
Interrupt
det
C12IN0-
C12IN1-
1
MUX
2 (2)
C12IN2C12IN3-
Set CxIF
det
CXPOL
CxVN
Cx(3)
CxVP
DAC_output
0
MUX
1 (2)
FVR Buffer2
CXIN+
CXOUT
MCXOUT
To Data Bus
+
EN
Q1
CxHYS
CxSP
CXSYNC
CxON
VSS
CxINTN
Interrupt
CXPCH<1:0>
CXOE
TRIS bit
CXOUT
2
D
(from Timer1)
T1CLK
Note
1:
2:
3:
1
To Timer1 or SR Latch
sync_CxOUT
DS40001413D-page 154
PIC12(L)F1822/16(L)F1823
19.2
Comparator Control
Enable
Output selection
Output polarity
Speed/Power selection
Hysteresis enable
Output synchronization
Interrupt enable
Interrupt edge polarity
Positive input channel selection
Negative input channel selection
19.2.1
COMPARATOR ENABLE
19.2.2
COMPARATOR OUTPUT
SELECTION
19.2.3
TABLE 19-1:
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition
CxPOL
CxOUT
19.2.4
COMPARATOR SPEED/POWER
SELECTION
The trade-off between speed or power can be optimized during program execution with the CxSP control
bit. The default state for this bit is 1 which selects the
normal speed mode. Device power consumption can
be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to 0.
DS40001413D-page 155
PIC12(L)F1822/16(L)F1823
19.3
Comparator Hysteresis
19.5
Comparator Interrupt
When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt
Flag bit (CxIF bit of the PIR2 register) will be set.
19.4
19.4.1
COMPARATOR OUTPUT
SYNCHRONIZATION
19.6
DS40001413D-page 156
PIC12(L)F1822/16(L)F1823
19.7
19.8
19.9
DS40001413D-page 157
PIC12(L)F1822/16(L)F1823
FIGURE 19-4:
Rs < 10K
Analog
Input
pin
VT 0.6V
RIC
To Comparator
VA
CPIN
5 pF
VT 0.6V
ILEAKAGE(1)
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
= Interconnect Resistance
RIC
= Source Impedance
RS
= Analog Voltage
VA
= Threshold Voltage
VT
Note 1:
DS40001413D-page 158
PIC12(L)F1822/16(L)F1823
REGISTER 19-1:
R/W-0/0
R-0/0
R/W-0/0
R/W-0/0
U-0
R/W-1/1
R/W-0/0
R/W-0/0
CxON
CxOUT
CxOE
CxPOL
CxSP
CxHYS
CxSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
DS40001413D-page 159
PIC12(L)F1822/16(L)F1823
REGISTER 19-2:
R/W-0/0
R/W-0/0
CxINTP
R/W-0/0
CxINTN
R/W-0/0
CxPCH<1:0>
U-0
U-0
R/W-0/0
(1)
CxNCH1
bit 7
R/W-0/0
CxNCH0
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
bit 3-2
Unimplemented: Read as 0
bit 1-0
PIC12(L)F1822:
0 = C1VN connects to C1IN0- pin
1 = C1VN connects to C1IN1- pin
PIC16(L)F1823:
00 = CxVN connects to C12IN0- pin
01 = CxVN connects to C12IN1- pin
10 = CxVN connects to C12IN2- pin
11 = CxVN connects to C12IN3- pin
Note 1:
PIC16(L)F1823 only.
REGISTER 19-3:
U-0
U-0
U-0
U-0
U-0
U-0
R-0/0
R-0/0
MC2OUT(1)
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
Unimplemented: Read as 0
bit 1
bit 0
Note 1:
PIC16(L)F1823 only.
DS40001413D-page 160
PIC12(L)F1822/16(L)F1823
TABLE 19-2:
Name
ANSELA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
118
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1SP
C1HYS
C1SYNC
159
CM1CON1
C1INTP
C1INTN
C1PCH1
C1PCH0
C1NCH1(1)
C1NCH0
160
CM2CON0(1)
C2ON
C2OUT
C2OE
C2POL
C2SP
C2HYS
C2SYNC
159
CM2CON1(1)
C2INTP
C2INTN
C2PCH1
C2PCH0
C2NCH1
C2NCH0
160
CMOUT
MC2OUT(1)
MC1OUT
160
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE2
OSFIE
C2IE(1)
C1IE
EEIE
BCL1IE
87
PIR2
OSFIF
C2IF(1)
C1IF
EEIF
BCL1IF
90
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
TRISA
TRISC(1)
Legend:
Note 1:
DS40001413D-page 161
PIC12(L)F1822/16(L)F1823
20.0
TIMER0 MODULE
20.1.2
20.1
Timer0 Operation
20.1.1
FIGURE 20-1:
FOSC/4
Data Bus
0
T0CKI
1
0
From CPSCLK
8
Sync
2 TCY
TMR0
0
1 TMR0SE
TMR0CS
8-bit
Prescaler
PSA
T0XCS
PS<2:0>
DS40001413D-page 162
PIC12(L)F1822/16(L)F1823
20.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be disabled by setting the
PSA bit of the OPTION register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
20.1.4
TIMER0 INTERRUPT
20.1.5
20.1.6
DS40001413D-page 163
PIC12(L)F1822/16(L)F1823
REGISTER 20-1:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
R/W-1/1
R/W-1/1
R/W-1/1
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TABLE 20-1:
Name
CPSCON0
INTCON
TRISA
Timer0 Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit 6
Bit 5
Bit 4
CPSON
CPSRM
GIE
PEIE
TMR0IE
INTE
OPTION_REG WPUEN
TMR0
Bit Value
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
T0XCS
302
IOCIE
TMR0IF
INTF
IOCIF
86
PSA
PS2
PS1
PS0
164
TRISA3
TRISA2
TRISA1
TRISA0
TRISA5
162*
TRISA4
117
Legend: = Unimplemented locations, read as 0. Shaded cells are not used by the Timer0 module.
* Page provides register information.
DS40001413D-page 164
PIC12(L)F1822/16(L)F1823
21.0
FIGURE 21-1:
T1GSS<1:0>
T1GSPM
00
T1G
From Timer0
Overflow
01
Comparator 1
sync_C1OUT
10
Comparator 2
sync_C2OUT
11
T1GVAL
0
Single Pulse
TMR1ON
T1GPOL
T1G_IN
CK
R
Acq. Control
Q1
Data Bus
D
Q
RD
T1GCON
EN
Interrupt
T1GGO/DONE
Set
TMR1GIF
det
T1GTM
TMR1GE
TMR1ON
To Comparator Module
TMR1(2)
TMR1H
EN
TMR1L
T1CLK
Synchronized
clock input
0
1
TMR1CS<1:0>
T1OSO
OUT
T1OSC
T1OSI
Cap. Sensing
Oscillator
T1SYNC
11
Synchronize(3)
Prescaler
1, 2, 4, 8
det
10
EN
0
T1OSCEN
(1)
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
2
T1CKPS<1:0>
FOSC/2
Internal
Clock
Sleep input
T1CKI
To Clock Switching Modules
DS40001413D-page 165
PIC12(L)F1822/16(L)F1823
21.1
Timer1 Operation
21.2
21.2.1
TABLE 21-1:
TIMER1 ENABLE
SELECTIONS
Timer1
Operation
TMR1ON
TMR1GE
Off
Off
21.2.2
Always On
Count Enabled
TABLE 21-2:
TMR1CS1
TMR1CS0
T1OSCEN
DS40001413D-page 166
Clock Source
PIC12(L)F1822/16(L)F1823
21.3
Timer1 Prescaler
21.4
Timer1 Oscillator
21.5
Timer1 Operation in
Asynchronous Counter Mode
21.5.1
21.6
Timer1 Gate
21.6.1
TABLE 21-3:
T1CLK
T1GPOL
T1G
Counts
Holds Count
Holds Count
Counts
21.6.2
Timer1 Operation
TABLE 21-4:
T1GSS
00
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
11
DS40001413D-page 167
PIC12(L)F1822/16(L)F1823
21.6.2.1
21.6.2.2
21.6.2.3
21.6.2.4
21.6.3
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
The Timer1 Gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 21-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note:
21.6.4
21.6.5
21.6.6
When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
Gate is not enabled (TMR1GE bit is cleared).
DS40001413D-page 168
PIC12(L)F1822/16(L)F1823
21.7
Timer1 Interrupt
Note:
21.8
21.9
Section 24.0
FIGURE 21-2:
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
DS40001413D-page 169
PIC12(L)F1822/16(L)F1823
FIGURE 21-3:
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
Timer1
FIGURE 21-4:
N+1
N+2
N+3
N+4
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
Timer1
DS40001413D-page 170
N+4
N+8
PIC12(L)F1822/16(L)F1823
FIGURE 21-5:
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
TMR1GIF
Cleared by software
N+1
N+2
Set by hardware on
falling edge of T1GVAL
Cleared by
software
DS40001413D-page 171
PIC12(L)F1822/16(L)F1823
FIGURE 21-6:
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
TMR1GIF
DS40001413D-page 172
Cleared by software
N+1
N+2
N+3
Set by hardware on
falling edge of T1GVAL
N+4
Cleared by
software
PIC12(L)F1822/16(L)F1823
21.11 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 21-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 21-1:
R/W-0/u
R/W-0/u
R/W-0/u
TMR1CS<1:0>
R/W-0/u
T1CKPS<1:0>
R/W-0/u
R/W-0/u
U-0
R/W-0/u
T1OSCEN
T1SYNC
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3
bit 2
TMR1CS<1:0> = 0X
This bit is ignored.
bit 1
Unimplemented: Read as 0
bit 0
DS40001413D-page 173
PIC12(L)F1822/16(L)F1823
21.12 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON), shown in
Register 21-2, is used to control Timer1 Gate.
REGISTER 21-2:
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W/HC-0/u
R-x/x
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
R/W-0/u
R/W-0/u
T1GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
DS40001413D-page 174
PIC12(L)F1822/16(L)F1823
TABLE 21-5:
Name
ANSELA
CCP1CON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
118
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
213
86
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
89
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
INTCON
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
T1CON
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
169*
169*
TRISA1
TRISA0
117
TMR1ON
173
T1GSS1
T1GSS0
174
Legend: = unimplemented, read as 0. Shaded cells are not used by the Timer1 module.
* Page provides register information.
Note 1: PIC16(L)F1823 only.
DS40001413D-page 175
PIC12(L)F1822/16(L)F1823
22.0
TIMER2 MODULE
FIGURE 22-1:
FOSC/4
Prescaler
1:1, 1:4, 1:16, 1:64
2
TMR2
Comparator
Sets Flag
bit TMR2IF
Reset
EQ
Postscaler
1:1 to 1:16
T2CKPS<1:0>
PR2
4
T2OUTPS<3:0>
DS40001413D-page 176
PIC12(L)F1822/16(L)F1823
22.1
Timer2 Operation
22.3
Timer2 Output
22.4
22.2
Timer2 Interrupt
DS40001413D-page 177
PIC12(L)F1822/16(L)F1823
REGISTER 22-1:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
T2OUTPS<3:0>
R/W-0/0
R/W-0/0
TMR2ON
bit 7
R/W-0/0
T2CKPS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-3
bit 2
bit 1-0
DS40001413D-page 178
PIC12(L)F1822/16(L)F1823
TABLE 22-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
89
PR2
PIE1
T2CON
TMR2
T2OUTPS<3:0>
176*
TMR2ON T2CKPS1 T2CKPS0
178
176*
Legend: = unimplemented location, read as 0. Shaded cells are not used for Timer2 module.
* Page provides register information.
DS40001413D-page 179
PIC12(L)F1822/16(L)F1823
23.0
The modulated output signal is generated by performing a logical AND operation of both the carrier and
modulator signals and then provided to the MDOUT pin.
The carrier signal is comprised of two distinct and separate signals. A carrier high (CARH) signal and a carrier low (CARL) signal. During the time in which the
modulator (MOD) signal is in a logic high state, the
DSM mixes the carrier high signal with the modulator
signal. When the modulator signal is in a logic low
state, the DSM mixes the carrier low signal with the
modulator signal.
FIGURE 23-1:
Carrier Synchronization
Carrier Source Polarity Select
Carrier Source Pin Disable
Programmable Modulator Data
Modulator Source Pin Disable
Modulated Output Polarity Select
Slew Rate Control
MDCH<3:0>
VSS
MDCIN1
MDCIN2
CLKR
CCP1
CCP2
CCP3
CCP4
Reserved
No Channel
Selected
0000
0001
0010
0011
0100
0101 CARH
0110
0111
1000
*
*
1111
MDEN
EN
Data Signal
Modulator
MDCHPOL
D
SYNC
MDMS<3:0>
MDBIT
MDMIN
CCP1
CCP2
CCP3
CCP4
Comparator C1
Comparator C2
MSSP1 SDO1
MSSP2 SDO2
EUSART
Reserved
No Channel
Selected
Q
0000
0001
0010
0011
0100
0101
0110 MOD
0111
1000
1001
1010
0011
*
*
1111
0
MDCHSYNC
MDOUT
MDOPOL
MDOE
D
SYNC
MDCL<3:0>
VSS
MDCIN1
MDCIN2
CLKR
CCP1
CCP2
CCP3
CCP4
Reserved
No Channel
Selected
0000
0001
0010
0011
0100
0101 CARL
0110
0111
1000
*
*
1111
DS40001413D-page 180
0
MDCLSYNC
MDCLPOL
PIC12(L)F1822/16(L)F1823
23.1
DSM Operation
23.2
CCP1 Signal
MSSP1 SDO1 Signal (SPI mode Only)
Comparator C1 Signal
Comparator C2 Signal (PIC16(L)F1823 only)
EUSART TX Signal
External Signal on MDMIN pin
MDBIT bit in the MDCON register
23.3
CCP1 Signal
Reference Clock Module Signal
External Signal on MDCIN1 pin
External Signal on MDCIN2 pin
VSS
23.4
Carrier Synchronization
During the time when the DSM switches between carrier high and carrier low signal sources, the carrier data
in the modulated output signal can become truncated.
To prevent this, the carrier signal can be synchronized
to the modulator signal. When synchronization is
enabled, the carrier pulse that is being mixed at the
time of the transition is allowed to transition low before
the DSM switches over to the next carrier source.
Synchronization is enabled separately for the carrier
high and carrier low signal sources. Synchronization for
the carrier high signal can be enabled by setting the
MDCHSYNC bit in the MDCARH register. Synchronization for the carrier low signal can be enabled by setting
the MDCLSYNC bit in the MDCARL register.
Figure 23-1 through Figure 23-5 show timing diagrams
of using various synchronization methods.
DS40001413D-page 181
PIC12(L)F1822/16(L)F1823
FIGURE 23-2:
EXAMPLE 23-1:
FIGURE 23-3:
CARH
CARL
CARH
CARL
DS40001413D-page 182
CARH
both
CARL
CARH
both
CARL
PIC12(L)F1822/16(L)F1823
FIGURE 23-4:
FIGURE 23-5:
CARH
CARL
CARH
CARL
Falling edges
used to sync
MDCHSYNC = 1
MDCLSYNC = 1
Active Carrier
State
CARH
CARL
CARH
CARL
DS40001413D-page 183
PIC12(L)F1822/16(L)F1823
23.5
23.6
Some peripherals assert control over their corresponding output pin when they are enabled. For example,
when the CCP1 module is enabled, the output of CCP1
is connected to the CCP1 pin.
This default connection to a pin can be disabled by setting the MDCHODIS bit in the MDCARH register for the
carrier high source and the MDCLODIS bit in the
MDCARL register for the carrier low source.
23.7
23.8
23.9
DS40001413D-page 184
PIC12(L)F1822/16(L)F1823
REGISTER 23-1:
R/W-0/0
R/W-0/0
R/W-1/1
R/W-0/0
R-0/0
U-0
U-0
R/W-0/0
MDEN
MDOE
MDSLR
MDOPOL
MDOUT
MDBIT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
Unimplemented: Read as 0
bit 0
Note 1:
2:
The modulated output frequency can be greater and asynchronous from the clock that updates this
register bit, the bit value may not be valid for higher speed modulator or carrier signals.
MDBIT must be selected as the modulation source in the MDSRC register for this operation.
DS40001413D-page 185
PIC12(L)F1822/16(L)F1823
REGISTER 23-2:
R/W-x/u
U-0
U-0
U-0
MDMSODIS
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
MDMS<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
Unimplemented: Read as 0
bit 3-0
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
DS40001413D-page 186
PIC12(L)F1822/16(L)F1823
REGISTER 23-3:
R/W-x/u
R/W-x/u
R/W-x/u
U-0
MDCHODIS
MDCHPOL
MDCHSYNC
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
MDCH<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3-0
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
DS40001413D-page 187
PIC12(L)F1822/16(L)F1823
REGISTER 23-4:
R/W-x/u
R/W-x/u
R/W-x/u
U-0
MDCLODIS
MDCLPOL
MDCLSYNC
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
MDCL<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3-0
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
DS40001413D-page 188
PIC12(L)F1822/16(L)F1823
TABLE 23-1:
Name
Bit 6
Bit 5
Bit 4
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
118
ANSELC(1)
ANSC3
ANSC2
ANSC1
ANSC0
122
MDCARH
MDCHODIS
MDCHPOL
MDCHSYNC
MDCH<3:0>
187
MDCARL
MDCLODIS
MDCLPOL
MDCLSYNC
MDCL<3:0>
188
MDCON
MDEN
MDOE
MDSLR
MDOPOL
MDSRC
MDMSODIS
MDOUT
Bit 2
Bit 1
Bit 0
Register
on Page
Bit 7
MDBIT
MDMS<3:0>
185
186
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
WPUA
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
119
WPUC(1)
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
122
Legend:
Note 1:
= unimplemented, read as 0. Shaded cells are not used in the Data Signal Modulator mode.
PIC16(L)F1823 only.
DS40001413D-page 189
PIC12(L)F1822/16(L)F1823
24.0
CAPTURE/COMPARE/PWM
MODULES
TABLE 24-1:
PWM RESOURCES
Device Name
ECCP1
PIC12(L)F1822
PIC16(L)F1823
DS40001413D-page 190
PIC12(L)F1822/16(L)F1823
24.1
Capture Mode
24.1.2
24.1.3
Note:
FIGURE 24-1:
Prescaler
1, 4, 16
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Set Flag bit CCP1IF
(PIR1 register)
CCP1
pin
24.1.4
CCP1 PRESCALER
EXAMPLE 24-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCP1CON
CCPR1H
and
Edge Detect
24.1.1
CCPR1L
Capture
Enable
TMR1H
CCP1M<3:0>
System Clock (FOSC)
TMR1L
CLRF
MOVLW
MOVWF
DS40001413D-page 191
PIC12(L)F1822/16(L)F1823
24.1.5
24.1.6
TABLE 24-2:
Name
APFCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXDTSEL
SDOSEL
SSSEL
T1GSEL
TXCKSEL
P1BSEL(2)
CCP1SEL(2)
CCP1CON
P1M<1:0>
DC1B<1:0>
CCPR1L
CCPR1H
CCP1M<3:0>
Register on
Page
114
213
191
191
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIE2
OSFIE
C2IE(1)
C1IE
EEIE
BCL1IE
88
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
89
PIR2
OSFIF
C2IF(1)
C1IF
EEIF
BCL1IF
90
T1OSCEN
T1SYNC
TMR1ON
173
T1GGO/DONE
T1GVAL
INTCON
T1CON
T1GCON
TMR1CS<1:0>
TMR1GE
T1GPOL
T1CKPS<1:0>
T1GTM
T1GSPM
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
T1GSS<1:0>
174
169
169
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
Legend: = Unimplemented location, read as 0. Shaded cells are not used by Capture mode.
Note 1:
PIC16(L)F1823 only.
2:
PIC12(L)F1822 only.
DS40001413D-page 192
PIC12(L)F1822/16(L)F1823
24.2
Compare Mode
24.2.2
24.2.3
FIGURE 24-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCP1M<3:0>
Mode Select
Set CCP1IF Interrupt Flag
(PIR1)
4
CCPR1H CCPR1L
CCP1
Pin
S
R
Output
Logic
Match
TRIS
Output Enable
Comparator
TMR1H
TMR1L
24.2.1
24.2.4
TABLE 24-3:
Device
CCP1/ECCP1
PIC12(L)F1822/16(L)F1823
CCP1
DS40001413D-page 193
PIC12(L)F1822/16(L)F1823
24.2.5
24.2.6
TABLE 24-4:
Name
APFCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
RXDTSEL
SDOSEL
SSSEL
T1GSEL
TXCKSEL
P1BSEL(2)
CCP1SEL(2)
114
CCP1CON
P1M<1:0>
DC1B<1:0>
CCPR1L
CCPR1H
CCP1M<3:0>
213
191
191
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIE2
OSFIE
C2IE(1)
C1IE
EEIE
BCL1IE
88
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
89
PIR2
OSFIF
C2IF(1)
C1IF
EEIF
BCL1IF
90
T1OSCEN
T1SYNC
TMR1ON
173
T1GGO/DONE
T1GVAL
INTCON
PIE1
T1CON
T1GCON
TMR1CS<1:0>
TMR1GE
T1GPOL
T1CKPS<1:0>
T1GTM
T1GSPM
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
T1GSS<1:0>
174
169
169
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
Legend: = Unimplemented location, read as 0. Shaded cells are not used by Compare mode.
Note 1:
PIC16(L)F1823 only.
2:
PIC12(L)F1822 only.
DS40001413D-page 194
PIC12(L)F1822/16(L)F1823
24.3
PWM Overview
FIGURE 24-3:
Period
Pulse Width
TMR2 = PR2
TMR2 = CCPR1H:CCP1CON<5:4>
TMR2 = 0
FIGURE 24-4:
CCPR1H(2) (Slave)
CCP1CON<5:4>
CCPR1L
CCP1
R
Comparator
TMR2
(1)
TRIS
Comparator
24.3.1
PR2 registers
T2CON registers
CCPR1L registers
CCP1CON registers
PR2
Note 1:
2:
Clear Timer,
toggle CCP1 pin and
latch duty cycle
DS40001413D-page 195
PIC12(L)F1822/16(L)F1823
24.3.2
4.
5.
6.
24.3.3
24.3.4
EQUATION 24-2:
PULSE WIDTH
PWM PERIOD
EQUATION 24-1:
PWM PERIOD
TOSC = 1/FOSC
EQUATION 24-3:
CCPRxL:CCPxCON<5:4>
Duty Cycle Ratio = ----------------------------------------------------------------------4 PRx + 1
DS40001413D-page 196
PIC12(L)F1822/16(L)F1823
24.3.5
PWM RESOLUTION
EQUATION 24-4:
PWM RESOLUTION
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
Note:
TABLE 24-5:
PWM Frequency
1.95 kHz
TABLE 24-6:
31.25 kHz
125 kHz
250 kHz
333.3 kHz
16
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
TABLE 24-7:
7.81 kHz
PWM Frequency
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
0x65
0x65
0x65
0x19
0x0C
0x09
DS40001413D-page 197
PIC12(L)F1822/16(L)F1823
24.3.6
24.3.9
24.3.7
24.3.8
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 24-8:
Name
APFCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
RXDTSEL
SDOSEL
SSSEL
T1GSEL
TXCKSEL
P1BSEL(2)
CCP1SEL(2)
114
CCP1CON
CCPR1L
INTCON
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
213
191
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
89
PR2
T2CON
TMR2
86
176*
T2OUTPS<3:0>
TMR2ON
T2CKPS<:0>1
178
176*
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
Legend: = Unimplemented location, read as 0. Shaded cells are not used by the PWM.
* Page provides register information.
Note 1:
PIC16(L)F1823 only.
2:
PIC12(L)F1822 only.
DS40001413D-page 198
PIC12(L)F1822/16(L)F1823
24.4
The PWM outputs are multiplexed with I/O pins and are
designated P1A, P1B, P1C and P1D. The polarity of the
PWM pins is configurable and is selected by setting the
bits CCP1M<3:0> in the CCP1CON register
appropriately.
PR2 registers
T2CON registers
CCPR1L registers
CCP1CON registers
CCP1AS registers
PSTR1CON registers
PWM1CON registers
Single PWM
Half-Bridge PWM
Full-Bridge PWM (PIC16(L)F1823 only)
Single PWM with PWM Steering mode
FIGURE 24-5:
DC1B<1:0>
CCP1M<3:0>
4
P1M<1:0>
2
CCPR1L
CCP1/P1A
CCP1/P1A
TRISx
CCPR1H (Slave)
P1B
R
Comparator
Output
Controller
P1B
TRISx
P1C(2)
TMR2
Comparator
PR2
Note
(1)
P1C(2)
TRISx
S
P1D(2)
Clear Timer,
toggle PWM pin and
latch duty cycle
P1D(2)
TRISx
PWM1CON
1:
The 8-bit timer TMR1 register is concatenated with the 2-bit internal Q clock, or two bits of the prescaler to create the 10-bit time
base.
2:
PIC16(L)F1823 only.
DS40001413D-page 199
PIC12(L)F1822/16(L)F1823
TABLE 24-9:
ECCP Mode
Single
Half-Bridge
P1M<1:0>
CCP1/P1A
P1B
P1C(2)
P1D(2)
00
Yes(1)
Yes(1)
Yes(1)
Yes(1)
10
Yes
Yes
No
No
Forward(2)
01
Yes
Yes
Yes
Yes
Full-Bridge, Reverse(2)
11
Yes
Yes
Yes
Yes
Full-Bridge,
Note 1:
2:
FIGURE 24-6:
PxM<1:0>
Signal
PRX+1
Pulse
Width
Period
00
(Single Output)
PxA Modulated
Delay
Delay
PxA Modulated
10
(Half-Bridge)
PxB Modulated
PxA Active
01
(Full-Bridge,
Forward)
PxB Inactive
PxC Inactive
PxD Modulated
PxA Inactive
11
(Full-Bridge,
Reverse)
PxB Modulated
PxC Active
PxD Inactive
Relationships:
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
DS40001413D-page 200
PIC12(L)F1822/16(L)F1823
FIGURE 24-7:
PxM<1:0>
Signal
PRx+1
Pulse
Width
Period
00
(Single Output)
PxA Modulated
PxA Modulated
10
(Half-Bridge)
Delay
Delay
PxB Modulated
PxA Active
01
(Full-Bridge,
Forward)
PxB Inactive
PxC Inactive
PxD Modulated
PxA Inactive
11
(Full-Bridge,
Reverse)
PxB Modulated
PxC Active
PxD Inactive
Relationships:
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
DS40001413D-page 201
PIC12(L)F1822/16(L)F1823
24.4.1
HALF-BRIDGE MODE
FIGURE 24-8:
Period
Period
Pulse Width
P1A(2)
td
td
P1B(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
2:
FIGURE 24-9:
P1A
Load
FET
Driver
P1B
FET
Driver
FET
Driver
P1A
FET
Driver
Load
FET
Driver
P1B
DS40001413D-page 202
PIC12(L)F1822/16(L)F1823
24.4.2
FULL-BRIDGE MODE
(PIC16(L)F1823 ONLY)
FIGURE 24-10:
FET
Driver
QC
QA
FET
Driver
P1A
Load
P1B
FET
Driver
P1C
FET
Driver
QD
QB
VP1D
DS40001413D-page 203
PIC12(L)F1822/16(L)F1823
FIGURE 24-11:
Forward Mode
Period
P1A
(2)
Pulse Width
P1B(2)
P1C(2)
P1D(2)
(1)
(1)
Reverse Mode
Period
Pulse Width
P1A(2)
P1B(2)
P1C(2)
P1D(2)
(1)
Note 1:
2:
(1)
DS40001413D-page 204
PIC12(L)F1822/16(L)F1823
24.4.2.1
FIGURE 24-12:
Signal
Period
P1A (Active-High)
P1B (Active-High)
Pulse Width
P1C (Active-High)
(2)
P1D (Active-High)
Pulse Width
Note 1:
2:
The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle.
When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The
modulated P1B and P1D signals are inactive at this time. The length of this time is four Timer counts.
DS40001413D-page 205
PIC12(L)F1822/16(L)F1823
FIGURE 24-13:
t1
Reverse Period
P1A
P1B
PW
P1C
P1D
PW
TON
External Switch C
TOFF
External Switch D
Potential
Shoot-Through Current
Note 1:
T = TOFF TON
2:
3:
DS40001413D-page 206
PIC12(L)F1822/16(L)F1823
24.4.3
FIGURE 24-14:
Timer
Overflow
Missing Pulse
(CCP1ASE not clear)
Timer
Overflow
Timer
Overflow
Timer
Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCP1ASE bit
Shutdown
Event Occurs
Shutdown
Event Clears
PWM
Resumes
CCP1ASE
Cleared by
Firmware
DS40001413D-page 207
PIC12(L)F1822/16(L)F1823
24.4.4
AUTO-RESTART MODE
The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the P1RSEN bit in the PWM1CON register.
If auto-restart is enabled, the CCP1ASE bit will remain
set as long as the auto-shutdown condition is active.
When the auto-shutdown condition is removed, the
CCP1ASE bit will be cleared via hardware and normal
operation will resume.
FIGURE 24-15:
Timer
Overflow
Missing Pulse
(CCP1ASE not clear)
Timer
Overflow
Timer
Overflow
Timer
Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCP1ASE bit
PWM
Resumes
Shutdown
Event Occurs
Shutdown
Event Clears
DS40001413D-page 208
CCP1ASE
Cleared by
Hardware
PIC12(L)F1822/16(L)F1823
24.4.5
PROGRAMMABLE DEAD-BAND
DELAY MODE
FIGURE 24-16:
Period
Period
Pulse Width
P1A(2)
td
td
P1B(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
2:
In Half-Bridge mode, a digitally programmable deadband delay is available to avoid shoot-through current
from destroying the bridge power switches. The delay
occurs at the signal transition from the non-active state
to the active state. See Figure 24-16 for illustration.
The lower seven bits of the associated PWM1CON
register (Register 24-3) sets the delay period in terms
of microcontroller instruction cycles (TCY or 4 TOSC).
FIGURE 24-17:
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
DS40001413D-page 209
PIC12(L)F1822/16(L)F1823
24.4.6
FIGURE 24-18:
SIMPLIFIED STEERING
BLOCK DIAGRAM
STR1A
P1A Signal
CCP1M1
PORT Data
STR1B
CCP1M0
PORT Data
PORT Data
PORT Data
P1B pin
TRIS
P1C pin(3)
1
0
TRIS
STR1D
CCP1M0
TRIS
STR1C
CCP1M1
P1A pin
P1D pin(3)
1
0
TRIS
DS40001413D-page 210
Note 1:
2:
3:
PIC16(L)F1823 only.
PIC12(L)F1822/16(L)F1823
24.4.6.1
Steering Synchronization
24.4.7
START-UP CONSIDERATIONS
FIGURE 24-19:
PWM
STR1
P1<D:A>
PORT Data
PORT Data
P1n = PWM
FIGURE 24-20:
PWM
STR1
P1<D:A>
PORT Data
PORT Data
P1n = PWM
DS40001413D-page 211
PIC12(L)F1822/16(L)F1823
24.4.8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXDTSEL
SDOSEL
SSSEL
T1GSEL
TXCKSEL
P1BSEL(2)
CCP1SEL(2)
CCP1CON
P1M<1:0>
DC1B<1:0>
PSS1AC<1:0>
114
213
CCP1AS
CCP1ASE
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
PR2
CCP1AS<2:0>
CCP1M<3:0>
Register
on Page
PSS1BD<1:0>
PSTR1CON
PWM1CON
P1RSEN
T2CON
TMR2
STR1SYNC
STR1D(1)
STR1C(1)
STR1B
STR1A
T2OUTPS<3:0>
(1)
TRISC
216
215
TMR2ON
T2CKPS<:0>1
TRISA
89
176*
P1DC<6:0>
214
178
176*
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
Legend: = Unimplemented location, read as 0. Shaded cells are not used by the PWM.
* Page provides register information.
Note 1:
PIC16(L)F1823 only.
2:
PIC12(L)F1822 only.
DS40001413D-page 212
PIC12(L)F1822/16(L)F1823
REGISTER 24-1:
R/W-00
R/W-0/0
R/W-0/0
P1M<1:0>(1)
R/W-0/0
R/W-0/0
DC1B<1:0>
R/W-0/0
R/W-0/0
R/W-0/0
CCP1M<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3-0
0100 =
0101 =
0110 =
0111 =
1000 =
1001 =
1010 =
1011 =
Compare mode: initialize ECCP1 pin low; set output on compare match (set CCP1IF)
Compare mode: initialize ECCP1 pin high; clear output on compare match (set CCP1IF)
Compare mode: generate software interrupt only; ECCP1 pin reverts to I/O state
Compare mode: Special Event Trigger (CCP1 resets Timer, sets CCP1IF bit, and starts A/D conversion
if A/D module is enabled)
PWM mode:
1100 = PWM mode: P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode: P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode: P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode: P1A, P1C active-low; P1B, P1D active-low
Note 1:
PIC16(L)F1823 only.
DS40001413D-page 213
PIC12(L)F1822/16(L)F1823
REGISTER 24-2:
R/W-0/0
R/W-0/0
CCP1ASE
R/W-0/0
R/W-0/0
CCP1AS<2:0>
R/W-0/0
R/W-0/0
R/W-0/0
PSS1AC<1:0>
R/W-0/0
PSS1BD<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
bit 3-2
bit 1-0
Note 1:
2:
DS40001413D-page 214
PIC12(L)F1822/16(L)F1823
REGISTER 24-3:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
P1RSEN
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
P1DC<6:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-0
Note 1:
Bit resets to 0 with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
DS40001413D-page 215
PIC12(L)F1822/16(L)F1823
PSTR1CON: PWM STEERING CONTROL REGISTER(1)
REGISTER 24-4:
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-1/1
STR1SYNC
STR1D
STR1C
STR1B
STR1A
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> = 11 and
P1M<1:0> = 00.
PIC16(L)F1823 only.
DS40001413D-page 216
PIC12(L)F1822/16(L)F1823
25.0
MASTER SYNCHRONOUS
SERIAL PORT MODULE
25.1
Master mode
Slave mode
Clock Parity
Slave Select Synchronization (Slave mode only)
Daisy-chain connection of slave devices
FIGURE 25-1:
Write
SSP1BUF Reg
SDI
SSP1SR Reg
SDO
bit 0
SS
SS Control
Enable
Shift
Clock
2 (CKP, CKE)
Clock Select
Edge
Select
SSP1M<3:0>
4
SCK
Edge
Select
TRIS bit
( TMR22Output )
Prescaler TOSC
4, 16, 64
Baud rate
generator
(SSP1ADD)
DS40001413D-page 217
PIC12(L)F1822/16(L)F1823
The I2C interface supports the following modes and
features:
Master mode
Slave mode
Byte NACKing (Slave mode)
Limited Multi-master support
7-bit and 10-bit addressing
Start and Stop interrupts
Interrupt masking
Clock stretching
Bus collision detection
General call address matching
Address masking
Address Hold and Data Hold modes
Selectable SDA hold times
Figure 25-2 is a block diagram of the I2C interface module in Master mode. Figure 25-3 is a diagram of the I2C
interface module in Slave mode.
[SSP1M 3:0]
Write
SSP1BUF
Baud rate
generator
(SSP1ADD)
SDA in
SCL
SCL in
Bus Collision
DS40001413D-page 218
LSb
Clock Cntl
SSP1SR
MSb
Shift
Clock
SDA
FIGURE 25-2:
PIC12(L)F1822/16(L)F1823
FIGURE 25-3:
Write
SSP1BUF Reg
SCL
Shift
Clock
SSP1SR Reg
SDA
MSb
LSb
SSP1MSK Reg
Match Detect
Addr Match
SSP1ADD Reg
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSP1STAT Reg)
DS40001413D-page 219
PIC12(L)F1822/16(L)F1823
25.2
DS40001413D-page 220
PIC12(L)F1822/16(L)F1823
FIGURE 25-4:
SPI Master
SCK
SCK
SDO
SDI
SDI
SDO
General I/O
General I/O
SS
General I/O
SCK
SDI
SDO
SPI Slave
#1
SPI Slave
#2
SS
SCK
SDI
SDO
SPI Slave
#3
SS
25.2.1
25.2.2
DS40001413D-page 221
PIC12(L)F1822/16(L)F1823
The MSSP1 consists of a transmit/receive shift register
(SSP1SR) and a buffer register (SSP1BUF). The
SSP1SR shifts the data in and out of the device, MSb
first. The SSP1BUF holds the data that was written to
the SSP1SR until the received data is ready. Once the
eight bits of data have been received, that byte is
moved to the SSP1BUF register. Then, the Buffer Full
Detect bit, BF of the SSP1STAT register, and the
interrupt flag bit, SSP1IF, are set. This double-buffering
of the received data (SSP1BUF) allows the next byte to
start reception before reading the data that was just
received. Any write to the SSP1BUF register during
transmission/reception of data will be ignored and the
write collision detect bit, WCOL, of the SSP1CON1
register, will be set. User software must clear the
WCOL bit to allow the following write(s) to the
SSP1BUF register to complete successfully.
FIGURE 25-5:
SDO
SDI
Shift Register
(SSP1SR)
MSb
LSb
SCK
General I/O
Processor 1
DS40001413D-page 222
SDO
Serial Clock
Slave Select
(optional)
Shift Register
(SSP1SR)
MSb
LSb
SCK
SS
Processor 2
PIC12(L)F1822/16(L)F1823
25.2.3
FIGURE 25-6:
Write to
SSP1BUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 7
bit 0
Input
Sample
(SMP = 1)
SSP1IF
SSP1SR to
SSP1BUF
DS40001413D-page 223
PIC12(L)F1822/16(L)F1823
25.2.4
25.2.4.1
Daisy-Chain Configuration
25.2.5
SLAVE SELECT
SYNCHRONIZATION
The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the
master device is ready to communicate. When the
Slave Select line is pulled low, the slave knows that a
new transmission is starting.
If the slave fails to receive the communication properly,
it will be reset at the end of the transmission, when the
Slave Select line returns to a high state. The slave is
then ready to receive a new transmission when the
Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave
misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave
and master to align themselves at the beginning of
each transmission.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSP1CON1<3:0> = 0100).
When the SS pin is low, transmission and reception are
enabled and the SDO pin is driven.
When the SS pin goes high, the SDO pin is no longer
driven, even if in the middle of a transmitted byte and
becomes a floating output. External pull-up/pull-down
resistors may be desirable depending on the application.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSP1CON1<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: When the SPI is used in Slave mode with
CKE set; the user must enable SS pin
control.
3: While operated in SPI Slave mode the
SMP bit of the SSP1STAT register must
remain clear.
DS40001413D-page 224
PIC12(L)F1822/16(L)F1823
FIGURE 25-7:
SPI Master
SCK
SCK
SDO
SDI
SDI
SPI Slave
#1
SDO
General I/O
SS
SCK
SDI
SPI Slave
#2
SDO
SS
SCK
SDI
SPI Slave
#3
SDO
SS
FIGURE 25-8:
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSP1BUF
SSP1BUF to
SSP1SR
SDO
bit 7
bit 6
bit 7
SDI
bit 6
bit 0
bit 0
bit 7
bit 7
Input
Sample
SSP1IF
Interrupt
Flag
SSP1SR to
SSP1BUF
DS40001413D-page 225
PIC12(L)F1822/16(L)F1823
FIGURE 25-9:
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSP1BUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 0
bit 7
Input
Sample
SSP1IF
Interrupt
Flag
SSP1SR to
SSP1BUF
Write Collision
detection active
FIGURE 25-10:
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSP1BUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 7
bit 0
Input
Sample
SSP1IF
Interrupt
Flag
SSP1SR to
SSP1BUF
Write Collision
detection active
DS40001413D-page 226
PIC12(L)F1822/16(L)F1823
25.2.6
TABLE 25-1:
Name
ANSELA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
118
ANSELC
ANSC3
ANSC2
ANSC1
ANSC0
122
APFCON
RXDTSEL
SDOSEL
SSSEL
T1GSEL
TXCKSEL
P1BSEL(2)
CCP1SEL(2)
114
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
89
SSP1BUF
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SSP1STAT
221*
SSPM<3:0>
SDAHT
SBCDE
AHEN
264
DHEN
266
263
SMP
CKE
D/A
R/W
UA
BF
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
Legend:
Note
*
1:
2:
= Unimplemented location, read as 0. Shaded cells are not used by the MSSP1 in SPI mode.
Page provides register information.
PIC16(L)F1823 only.
PIC12(L)F1822 only.
DS40001413D-page 227
PIC12(L)F1822/16(L)F1823
25.3
VDD
SCL
DS40001413D-page 228
I2C MASTER/
SLAVE CONNECTION
FIGURE 25-11:
SCL
VDD
Master
Slave
SDA
SDA
PIC12(L)F1822/16(L)F1823
When one device is transmitting a logical one, or letting
the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on the SCL line, is called clock stretching.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on
the SDA line, it is called arbitration. Arbitration ensures
that there is only one master device communicating at
any single time.
25.3.1
Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.
CLOCK STRETCHING
25.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a transmission on or about the same time. When this occurs,
the process of arbitration begins. Each transmitter
checks the level of the SDA data line and compares it
to the level that it expects to find. The first transmitter to
observe that the two levels dont match, loses arbitration, and must stop transmitting on the SDA line.
For example, if one transmitter holds the SDA line to a
logical one (lets it float) and a second transmitter holds
it to a logical zero (pulls it low), the result is that the
SDA line will be low. The first transmitter then observes
that the level of the line is different than expected and
concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDA
line. If this transmitter is also a master device, it also
must stop driving the SCL line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission. It can do so without any complications, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
If two master devices are sending a message to two different slave devices at the address stage, the master
sending the lower slave address always wins arbitration. When two master devices send messages to the
same slave address, and addresses can sometimes
refer to multiple slaves, the arbitration process must
continue into the data stage.
25.4
25.4.1
BYTE FORMAT
25.4.2
25.4.3
25.4.4
DS40001413D-page 229
PIC12(L)F1822/16(L)F1823
TABLE 25-2:
TERM
Transmitter
Description
DS40001413D-page 230
25.4.5
START CONDITION
25.4.6
STOP CONDITION
25.4.7
RESTART CONDITION
25.4.8
START/STOP CONDITION
INTERRUPT MASKING
PIC12(L)F1822/16(L)F1823
FIGURE 25-12:
SDA
SCL
S
Start
P
Change of
Change of
Data Allowed
Data Allowed
Condition
FIGURE 25-13:
Stop
Condition
Sr
Change of
Change of
Data Allowed
Restart
Data Allowed
Condition
25.4.9
ACKNOWLEDGE SEQUENCE
I2C
DS40001413D-page 231
PIC12(L)F1822/16(L)F1823
25.5
25.5.1
25.5.1.1
25.5.1.2
DS40001413D-page 232
25.5.2
SLAVE RECEPTION
25.5.2.1
PIC12(L)F1822/16(L)F1823
25.5.2.2
DS40001413D-page 233
DS40001413D-page 234
SSP1OV
BF
SSP1IF
A7
A6
A5
A4
A3
A2
A1
ACK
D7
D6
D4
D3
D2
D1
SSP1BUF is read
Cleared by software
D5
Receiving Data
D6
First byte
of data is
available
in SSP1BUF
D0 ACK D7
D4
D3
D2
D1
D0
Cleared by software
D5
Receiving Data
ACK = 1
FIGURE 25-14:
SCL
SDA
Receiving Address
PIC12(L)F1822/16(L)F1823
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
CKP
SSP1OV
BF
SSP1IF
SCL
A7
A6
A5
A4
A3
A2
A1
R/W=0 ACK
SEN
2
D6
D5
D4
D3
D2
D1
D0
SSP1BUF is read
Cleared by software
D7
Receive Data
ACK
SEN
3
D5
D4
D3
First byte
of data is
available
in SSP1BUF
D2
D1
Cleared by software
D6
D7
Receive Data
D0
ACK
FIGURE 25-15:
SDA
Receive Address
PIC12(L)F1822/16(L)F1823
DS40001413D-page 235
DS40001413D-page 236
ACKTIM
CKP
ACKDT
BF
SSP1IF
Receiving Address
Slave software
clears ACKDT to
Address is
read from
SSBUF
If AHEN = 1:
SSP1IF is set
When AHEN = 1:
CKP is cleared by hardware
and SCL is stretched
A7 A6 A5 A4 A3 A2 A1
Receiving Data
9
2
ACKTIM cleared by
hardware in 9th
rising edge of SCL
When DHEN = 1:
CKP is cleared by
hardware on 8th falling
edge of SCL
SSP1IF is set on
9th falling edge of
SCL, after ACK
ACK D7 D6 D5 D4 D3 D2 D1 D0
Received Data
Slave software
sets ACKDT to
not ACK
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
No interrupt
after not ACK
from Slave
ACK= 1
Master sends
Stop condition
FIGURE 25-16:
SCL
SDA
PIC12(L)F1822/16(L)F1823
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
ACKTIM
CKP
ACKDT
BF
SSP1IF
Receiving Address
4
5
6 7
When AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
Received
address is loaded into
SSP1BUF
2 3
A7 A6 A5 A4 A3 A2 A1
ACK
Receive Data
2 3
6 7
When DHEN = 1;
on the 8th falling edge
of SCL of a received
data byte, CKP is cleared
Received data is
available on SSP1BUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Receive Data
1
3 4
6 7
Set by software,
release SCL
Slave sends
not ACK
SSP1BUF can be
read any time before
next byte is loaded
D7 D6 D5 D4 D3 D2 D1 D0
ACK
No interrupt after
if not ACK
from Slave
Master sends
Stop condition
FIGURE 25-17:
SCL
SDA
R/W = 0
Master releases
SDA to slave for ACK sequence
PIC12(L)F1822/16(L)F1823
DS40001413D-page 237
PIC12(L)F1822/16(L)F1823
25.5.3
SLAVE TRANSMISSION
25.5.3.2
7-bit Transmission
1.
25.5.3.1
DS40001413D-page 238
D/A
R/W
ACKSTAT
CKP
BF
SSP1IF
Receiving Address
Indicates an address
has been received
R/W = 1 Automatic
ACK
Received address
is read from SSP1BUF
A7 A6 A5 A4 A3 A2 A1
Transmitting Data
Automatic
Set by software
Data to transmit is
loaded into SSP1BUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting Data
CKP is not
held for not
ACK
BF is automatically
cleared after 8th falling
edge of SCL
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
FIGURE 25-18:
SCL
SDA
Master sends
Stop condition
PIC12(L)F1822/16(L)F1823
DS40001413D-page 239
PIC12(L)F1822/16(L)F1823
25.5.3.3
DS40001413D-page 240
D/A
R/W
ACKTIM
CKP
ACKSTAT
ACKDT
BF
SSP1IF
Receiving Address
Slave clears
ACKDT to ACK
address
ACK
When R/W = 1;
CKP is always
cleared after ACK
R/W = 1
Received address
is read from SSP1BUF
When AHEN = 1;
CKP is cleared by hardware
after receiving matching
address.
A7 A6 A5 A4 A3 A2 A1
3
Cleared by software
Set by software,
releases SCL
Data to transmit is
loaded into SSP1BUF
Transmitting Data
Automatic
D7 D6 D5 D4 D3 D2 D1 D0 ACK
ACKTIM is cleared
on 9th rising edge of SCL
Automatic
Transmitting Data
Masters ACK
response is copied
to SSP1STAT
BF is automatically
cleared after 8th falling
edge of SCL
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
Master sends
Stop condition
FIGURE 25-19:
SCL
SDA
PIC12(L)F1822/16(L)F1823
DS40001413D-page 241
PIC12(L)F1822/16(L)F1823
25.5.4
3.
4.
5.
6.
7.
8.
25.5.5
9.
DS40001413D-page 242
CKP
UA
BF
SSP1IF
1
5
0 A9 A8
Set by hardware
on 9th falling edge
When UA = 1;
SCL is held low
ACK
If address matches
SSP1ADD it is loaded into
SSP1BUF
A7 A6 A5 A4 A3 A2 A1 A0 ACK
9
1
Data is read
from SSP1BUF
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
Set by software,
When SEN = 1;
releasing SCL
CKP is cleared after
9th falling edge of received byte
Receive address is
read from SSP1BUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
FIGURE 25-20:
SCL
SDA
Master sends
Stop condition
PIC12(L)F1822/16(L)F1823
DS40001413D-page 243
DS40001413D-page 244
ACKTIM
CKP
UA
ACKDT
BF
A9
A8
Set by hardware
on 9th falling edge
If when AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
R/W = 0
ACK
UA
A6
A5
A4
A3
A2
A1
Update to SSP1ADD is
not allowed until 9th
falling edge of SCL
SSP1BUF can be
read anytime before
the next received byte
Cleared by software
A7
A0
ACK
UA
D6
D5
D4
D2
D1
Update of SSP1ADD,
clears UA and releases
SCL
D3
Receive Data
Cleared by software
D7
Received data
is read from
SSP1BUF
D6 D5
Receive Data
D0 ACK D7
FIGURE 25-21:
SSP1IF
SCL
SDA
PIC12(L)F1822/16(L)F1823
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
D/A
R/W
ACKSTAT
CKP
UA
BF
SSP1IF
Set by hardware
Indicates an address
has been received
UA indicates SSP1ADD
must be updated
SSP1BUF loaded
with received address
SCL
1
3
7 8
After SSP1ADD is
updated, UA is cleared
and SCL is released
Cleared by software
A7 A6 A5 A4 A3 A2 A1 A0 ACK
1
4
7 8
Set by hardware
2 3
When R/W = 1;
CKP is cleared on
9th falling edge of SCL
Received address is
read from SSP1BUF
Sr
1 1 1 1 0 A9 A8
ACK
Set by software
releases SCL
Data to transmit is
loaded into SSP1BUF
D7 D6 D5 D4 D3 D2 D1 D0
Master sends
Stop condition
ACK = 1
Master sends
not ACK
FIGURE 25-22:
SDA
Master sends
Restart event
PIC12(L)F1822/16(L)F1823
DS40001413D-page 245
PIC12(L)F1822/16(L)F1823
25.5.6
CLOCK STRETCHING
25.5.6.2
25.5.6.1
FIGURE 25-23:
25.5.6.3
Byte NACKing
25.5.7
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an
external I2C master device has already asserted the
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I2C bus have
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see Figure 25-23).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX 1
DX
SCL
CKP
Master device
asserts clock
Master device
releases clock
WR
SSP1CON1
DS40001413D-page 246
PIC12(L)F1822/16(L)F1823
25.5.8
respond.
reception
FIGURE 25-24:
and
call
SDA
SCL
S
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
SSP1IF
BF (SSP1STAT<0>)
Cleared by software
GCEN (SSP1CON2<7>)
SSP1BUF is read
1
25.5.9
DS40001413D-page 247
PIC12(L)F1822/16(L)F1823
25.6
DS40001413D-page 248
25.6.1
25.6.2
CLOCK ARBITRATION
PIC12(L)F1822/16(L)F1823
FIGURE 25-25:
SDA
DX 1
DX
03h
02h
01h
03h
02h
25.6.3
25.6.4
FIGURE 25-26:
SDA = 1,
SCL = 1
TBRG
TBRG
SDA
1st bit
2nd bit
TBRG
SCL
S
TBRG
DS40001413D-page 249
PIC12(L)F1822/16(L)F1823
25.6.5
FIGURE 25-27:
Write to SSP1CON2
occurs here
SDA = 1,
SCL (no change)
SDA = 1,
SCL = 1
TBRG
TBRG
TBRG
1st bit
SDA
Sr
TBRG
Repeated Start
25.6.6
DS40001413D-page 250
PIC12(L)F1822/16(L)F1823
25.6.6.1
BF Status Flag
25.6.6.2
25.6.6.3
25.6.6.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
DS40001413D-page 251
DS40001413D-page 252
S
R/W
PEN
SEN
BF (SSP1STAT<0>)
SSP1IF
SCL
SDA
A6
A5
A4
A3
A2
A1
Cleared by software
SSP1BUF written
D7
1
SCL held low
while CPU
responds to SSP1IF
ACK = 0
R/W = 0
A7
D5
D4
D3
D2
D1
D0
D6
Cleared by software
ACK
ACKSTAT in
SSP1CON2 = 1
FIGURE 25-28:
SEN = 0
PIC12(L)F1822/16(L)F1823
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
PIC12(L)F1822/16(L)F1823
25.6.7
25.6.7.1
8.
9.
10.
11.
12.
13.
14.
15.
User sets the RCEN bit of the SSP1CON2 register and the Master clocks in a byte from the slave.
After the 8th falling edge of SCL, SSP1IF and
BF are set.
Master clears SSP1IF and reads the received
byte from SSP1UF, clears BF.
Master sets ACK value sent to slave in ACKDT
bit of the SSP1CON2 register and initiates the
ACK by setting the ACKEN bit.
Masters ACK is clocked out to the Slave and
SSP1IF is set.
User clears SSP1IF.
Steps 8-13 are repeated for each received byte
from the slave.
Master sends a not ACK or Stop to end
communication.
BF Status Flag
25.6.7.2
25.6.7.3
25.6.7.4
1.
2.
3.
4.
5.
6.
7.
DS40001413D-page 253
DS40001413D-page 254
RCEN
ACKEN
SSP1OV
BF
(SSP1STAT<0>)
SDA = 0, SCL = 1
while CPU
responds to SSP1IF
SSP1IF
A7
4
5
Cleared by software
A6 A5 A4 A3 A2
7
8
ACK
D0
ACK
RCEN cleared
automatically
5
6
Cleared by software
Cleared in
software
ACK
RCEN cleared
automatically
P
Set SSP1IF interrupt
at end of Acknowledge sequence
Bus master
terminates
transfer
Set P bit
(SSP1STAT<4>)
and SSP1IF
PEN bit = 1
written here
D0
RCEN cleared
automatically
D7 D6 D5 D4 D3 D2 D1
Cleared by software
Cleared by software
D7 D6 D5 D4 D3 D2 D1
A1 R/W
RCEN = 1, start
next receive
FIGURE 25-29:
SCL
SDA
Write to SSP1CON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSP1CON2<5>) = 0
PIC12(L)F1822/16(L)F1823
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
PIC12(L)F1822/16(L)F1823
25.6.8
ACKNOWLEDGE SEQUENCE
TIMING
25.6.9
25.6.8.1
25.6.9.1
FIGURE 25-30:
TBRG
SDA
ACK
D0
SCL
SSP1IF
SSP1IF set at
the end of receive
Cleared in
software
Cleared in
software
SSP1IF set at the end
of Acknowledge sequence
FIGURE 25-31:
Write to SSP1CON2,
set PEN
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
DS40001413D-page 255
PIC12(L)F1822/16(L)F1823
25.6.10
SLEEP OPERATION
25.6.13
25.6.11
EFFECTS OF A RESET
25.6.12
MULTI-MASTER MODE
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a 1 on SDA, by letting SDA float high and
another master asserts a 0. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a 1 and the data sampled on the SDA pin is 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCL1IF, and reset the
I2C port to its Idle state (Figure 25-32).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSP1BUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSP1CON2
register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free,
the user can resume communication by asserting a Start
condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSP1IF bit will be set.
A write to the SSP1BUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSP1STAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 25-32:
SDA
SCL
BCL1IF
DS40001413D-page 256
PIC12(L)F1822/16(L)F1823
25.6.13.1
FIGURE 25-33:
The reason that bus collision is not a factor during a Start condition is that no two
bus masters can assert a Start condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address following the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SDA
SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN
BCL1IF
SSP1IF
SSP1IF and BCL1IF are
cleared by software
DS40001413D-page 257
PIC12(L)F1822/16(L)F1823
FIGURE 25-34:
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCL1IF.
BCL1IF
Interrupt cleared
by software
SSP1IF 0
FIGURE 25-35:
SDA
SCL
TBRG
SEN
BCL1IF
Set SSP1IF
SSP1IF
SDA = 0, SCL = 1,
set SSP1IF
DS40001413D-page 258
Interrupts cleared
by software
PIC12(L)F1822/16(L)F1823
25.6.13.2
FIGURE 25-36:
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCL1IF and release SDA and SCL.
RSEN
BCL1IF
Cleared by software
S
SSP1IF
FIGURE 25-37:
TBRG
SDA
SCL
BCL1IF
RSEN
S
SSP1IF
DS40001413D-page 259
PIC12(L)F1822/16(L)F1823
25.6.13.3
b)
FIGURE 25-38:
TBRG
TBRG
SDA
SDA sampled
low after TBRG,
set BCL1IF
SSP1IF
FIGURE 25-39:
TBRG
TBRG
SDA
Assert SDA
SCL
PEN
BCL1IF
P
SSP1IF
DS40001413D-page 260
PIC12(L)F1822/16(L)F1823
TABLE 25-3:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIE2
OSFIE
C2IE(1)
C1IE
EEIE
BCL1IE
88
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
PIR2
OSFIF
C2IF(1)
C1IF
EEIF
BCL1IF
90
SSP1ADD
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
267
SSP1BUF
SSP1CON1
89
221*
WCOL
SSPOV
SSPEN
CKP
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
265
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
266
SSP1MSK
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
267
SSP1STAT
SMP
CKE
D/A
R/W
UA
BF
263
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
TRISA
(1)
TRISC
Legend:
*
Note 1:
SSPM<3:0>
264
= unimplemented location, read as 0. Shaded cells are not used by the MSSP module in I2C mode.
Page provides register information.
PIC16(L)F1823 only.
DS40001413D-page 261
PIC12(L)F1822/16(L)F1823
25.7
The MSSP1 module has a Baud Rate Generator available for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSP1ADD register (Register 25-6).
When a write occurs to SSP1BUF, the Baud Rate Generator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
EQUATION 25-1:
FOSC
FCLOCK = ------------------------------------------------ SSPxADD + 1 4
FIGURE 25-40:
SSP1M<3:0>
Reload
SCL
Control
SSP1CLK
SSP1ADD<7:0>
Reload
FOSC/2
TABLE 25-4:
Note 1:
FOSC
FCY
BRG Value
FCLOCK
(2 Rollovers of BRG)
32 MHz
8 MHz
13h
400 kHz
32 MHz
8 MHz
19h
308 kHz
32 MHz
8 MHz
4Fh
100 kHz
16 MHz
4 MHz
09h
400 kHz
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
Refer to the I/O port electrical and timing specifications in Table 30-4 and Figure 30-7 to ensure the
system is designed to support the I/O requirements.
DS40001413D-page 262
PIC12(L)F1822/16(L)F1823
REGISTER 25-1:
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
P: Stop bit
(I2C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is 0 on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit
(I2C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is 0 on Reset)
0 = Start bit was not detected last
bit 2
bit 1
bit 0
DS40001413D-page 263
PIC12(L)F1822/16(L)F1823
REGISTER 25-2:
R/C/HS-0/0
R/C/HS-0/0
R/W-0/0
R/W-0/0
WCOL
SSP1OV
SSP1EN
CKP
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSP1M<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
C = User cleared
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note
1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF
register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDA and SCL pins must be configured as inputs.
SSP1ADD values of 0, 1 or 2 are not supported for I2C Mode.
SSP1ADD value of 0 is not supported. Use SSP1M = 0000 instead.
DS40001413D-page 264
PIC12(L)F1822/16(L)F1823
REGISTER 25-3:
R/W-0/0
R-0/0
R/W-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/W/HS-0/0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
HC = Cleared by hardware
S = User set
bit 7
GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSP1SR
0 = General call address disabled
bit 6
bit 5
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
bit 3
bit 2
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCK Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enabled bit (in I2C Master mode only)
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).
DS40001413D-page 265
PIC12(L)F1822/16(L)F1823
REGISTER 25-4:
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the
BCL1IF bit of the PIR2 register is set, and bus goes Idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1
bit 0
Note 1:
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSP1OV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSP1BUF.
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
DS40001413D-page 266
PIC12(L)F1822/16(L)F1823
REGISTER 25-5:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
MSK<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-1
bit 0
REGISTER 25-6:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADD<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
Master mode:
bit 7-0
bit 7-3
Not used: Unused for Most Significant Address byte. Bit state of this register is a dont care. Bit pattern sent by master is fixed by I2C specification and must be equal to 11110. However, those bits are
compared by hardware and are not affected by the value in this register.
bit 2-1
bit 0
bit 7-0
bit 7-1
bit 0
DS40001413D-page 267
PIC12(L)F1822/16(L)F1823
26.0
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
FIGURE 26-1:
TXIE
Interrupt
TXIF
TXREG Register
8
MSb
TX/CK pin
LSb
(8)
Pin Buffer
and Control
TRMT
SPEN
TXEN
Baud Rate Generator
FOSC
TX9
BRG16
+1
SPBRGH
SPBRGL
DS40001413D-page 268
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
TX9D
PIC12(L)F1822/16(L)F1823
FIGURE 26-2:
CREN
RX/DT pin
Data
Recovery
FOSC
BRG16
SPBRGH
SPBRGL
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
Stop
RCIDL
RSR Register
MSb
Pin Buffer
and Control
+1
OERR
(8)
LSb
0 START
RX9
FERR
RX9D
RCREG Register
8
FIFO
Data Bus
RCIF
RCIE
Interrupt
DS40001413D-page 269
PIC12(L)F1822/16(L)F1823
26.1
26.1.1
EUSART ASYNCHRONOUS
TRANSMITTER
26.1.1.1
26.1.1.2
Transmitting Data
26.1.1.3
DS40001413D-page 270
PIC12(L)F1822/16(L)F1823
26.1.1.4
TSR Status
26.1.1.6
26.1.1.5
1.
2.
3.
5.
6.
7.
FIGURE 26-3:
Write to TXREG
BRG Output
(Shift Clock)
ASYNCHRONOUS TRANSMISSION
Word 1
TX/CK
pin
Start bit
FIGURE 26-4:
bit 1
bit 7/8
Stop bit
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
bit 0
1 TCY
Word 1
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
Word 1
TX/CK
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
Word 2
Start bit
bit 0
1 TCY
bit 1
Word 1
bit 7/8
Stop bit
Start bit
bit 0
Word 2
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
DS40001413D-page 271
PIC12(L)F1822/16(L)F1823
TABLE 26-1:
Name
Bit 6
ABDOVF
GIE
PIE1
PIR1
BAUDCON
INTCON
RCSTA
TRISC
TXREG
TXSTA
Legend:
*
Note 1:
Bit 0
Register on
Page
BRG16
WUE
ABDEN
279
IOCIE
TMR0IF
INTF
IOCIF
86
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
87
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
89
CREN
ADDEN
FERR
OERR
RX9D
Bit 3
RCIDL
SCKP
PEIE
TMR0IE
INTE
TMR1GIE
ADIE
RCIE
TMR1GIF
ADIF
RCIF
SPEN
RX9
SREN
BRG<7:0>
SPBRGH
(1)
Bit 1
Bit 4
SPBRGL
TRISA
Bit 2
Bit 5
BRG<15:8>
280*
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
TX9
TXEN
278
280*
117
121
270*
SYNC
SENDB
BRGH
TRMT
TX9D
277
= unimplemented location, read as 0. Shaded cells are not used for Asynchronous Transmission.
Page provides register information.
PIC16(L)F1823 only.
DS40001413D-page 272
PIC12(L)F1822/16(L)F1823
26.1.2
EUSART ASYNCHRONOUS
RECEIVER
26.1.2.1
26.1.2.2
Receiving Data
26.1.2.3
Receive Interrupts
DS40001413D-page 273
PIC12(L)F1822/16(L)F1823
26.1.2.4
26.1.2.5
26.1.2.7
Address Detection
26.1.2.6
DS40001413D-page 274
PIC12(L)F1822/16(L)F1823
26.1.2.8
26.1.2.9
1.
FIGURE 26-5:
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX/DT pin
bit 1
Rcv Shift
Reg
Rcv Buffer Reg.
RCIDL
Start
bit
Word 1
RCREG
bit 0
Start
bit
Word 2
RCREG
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS40001413D-page 275
PIC12(L)F1822/16(L)F1823
TABLE 26-2:
Name
Bit 6
ABDOVF
GIE
PIE1
PIR1
BAUDCON
INTCON
Bit 1
Bit 0
Register
on Page
BRG16
WUE
ABDEN
279
IOCIE
TMR0IF
INTF
IOCIF
86
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
87
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
87
OERR
RX9D
Bit 4
Bit 3
RCIDL
SCKP
PEIE
TMR0IE
INTE
TMR1GIE
ADIE
RCIE
TMR1GIF
ADIF
RCIF
SPEN
RX9
SREN
RCREG
RCSTA
Bit 2
Bit 5
ADDEN
273*
FERR
278
SPBRGL
BRG<7:0>
280*
SPBRGH
BRG<15:8>
280*
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
277
TXSTA
Legend:
*
Note 1:
= unimplemented location, read as 0. Shaded cells are not used for Asynchronous Reception.
Page provides register information.
PIC16(L)F1823 only.
DS40001413D-page 276
PIC12(L)F1822/16(L)F1823
26.2
The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may
drift as VDD or temperature changes, and this directly
affects the asynchronous baud rate. Two methods may
be used to adjust the baud rate clock, but both require
a reference clock source of some kind.
REGISTER 26-1:
R/W-/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-1/1
R/W-0/0
CSRC
TX9
TXEN(1)
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
DS40001413D-page 277
PIC12(L)F1822/16(L)F1823
RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
REGISTER 26-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-x/x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001413D-page 278
PIC12(L)F1822/16(L)F1823
REGISTER 26-3:
R-0/0
R-1/1
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
DS40001413D-page 279
PIC12(L)F1822/16(L)F1823
26.3
EXAMPLE 26-1:
CALCULATING BAUD
RATE ERROR
DS40001413D-page 280
PIC12(L)F1822/16(L)F1823
TABLE 26-3:
Configuration Bits
BRG/EUSART Mode
8-bit/Asynchronous
FOSC/[64 (n+1)]
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
SYNC
BRG16
BRGH
1
Legend:
Name
BAUDCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
279
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
278
SPBRGL
BRG<7:0>
SPBRGH
BRG<15:8>
TXSTA
FOSC/[4 (n+1)]
TABLE 26-4:
RCSTA
FOSC/[16 (n+1)]
CSRC
TX9
TXEN
SYNC
SENDB
280*
280*
BRGH
TRMT
TX9D
277
Legend: = unimplemented location, read as 0. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
DS40001413D-page 281
PIC12(L)F1822/16(L)F1823
TABLE 26-5:
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
1200
1221
1.73
255
1200
0.00
239
1200
0.00
143
2400
2404
0.16
207
2404
0.16
129
2400
0.00
119
2400
0.00
71
9600
9615
0.16
51
9470
-1.36
32
9600
0.00
29
9600
0.00
17
10417
10417
0.00
47
10417
0.00
29
10286
-1.26
27
10165
-2.42
16
19.2k
19.23k
0.16
25
19.53k
1.73
15
19.20k
0.00
14
19.20k
0.00
57.6k
55.55k
-3.55
57.60k
0.00
57.60k
0.00
115.2k
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
300
0.16
207
300
0.00
191
300
0.16
51
1200
1202
0.16
103
1202
0.16
51
1200
0.00
47
1202
0.16
12
2400
2404
0.16
51
2404
0.16
25
2400
0.00
23
9600
9615
0.16
12
9600
0.00
10417
10417
0.00
11
10417
0.00
19.2k
19.20k
0.00
57.6k
57.60k
0.00
115.2k
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
1200
2400
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
9600
0.00
71
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.82k
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.64k
2.12
16
113.64k
-1.36
10
115.2k
0.00
115.2k
0.00
DS40001413D-page 282
PIC12(L)F1822/16(L)F1823
TABLE 26-5:
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
1202
0.16
207
1200
0.00
191
300
1202
0.16
0.16
207
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19231
0.16
25
19.23k
0.16
12
19.2k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
300.0
0.00
6666
300.0
-0.01
4166
300.0
0.00
3839
300.0
0.00
2303
1200
1200
-0.02
3332
1200
-0.03
1041
1200
0.00
959
1200
0.00
575
2400
2401
-0.04
832
2399
-0.03
520
2400
0.00
479
2400
0.00
287
71
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
9600
0.00
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.818
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.6k
2.12
16
113.636
-1.36
10
115.2k
0.00
115.2k
0.00
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
299.9
-0.02
1666
300.1
0.04
832
300.0
0.00
767
300.5
0.16
207
1200
1199
-0.08
416
1202
0.16
207
1200
0.00
191
1202
0.16
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19.23k
0.16
25
19.23k
0.16
12
19.20k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
DS40001413D-page 283
PIC12(L)F1822/16(L)F1823
TABLE 26-5:
BAUD
RATE
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
300.0
1200
0.00
0.00
26666
6666
300.0
1200
0.00
-0.01
16665
4166
300.0
1200
0.00
0.00
15359
3839
300.0
1200
0.00
0.00
9215
2303
2400
2400
0.01
3332
2400
0.02
2082
2400
0.00
1919
2400
0.00
1151
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
9600
9604
0.04
832
9597
-0.03
520
9600
0.00
479
9600
0.00
287
10417
10417
0.00
767
10417
0.00
479
10425
0.08
441
10433
0.16
264
19.2k
19.18k
-0.08
416
19.23k
0.16
259
19.20k
0.00
239
19.20k
0.00
143
57.6k
57.55k
-0.08
138
57.47k
-0.22
86
57.60k
0.00
79
57.60k
0.00
47
115.2k
115.9k
0.64
68
116.3k
0.94
42
115.2k
0.00
39
115.2k
0.00
23
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
832
300
300.0
0.00
6666
300.0
0.01
3332
300.0
0.00
3071
300.1
0.04
1200
1200
-0.02
1666
1200
0.04
832
1200
0.00
767
1202
0.16
207
2400
2401
0.04
832
2398
0.08
416
2400
0.00
383
2404
0.16
103
9600
9615
0.16
207
9615
0.16
103
9600
0.00
95
9615
0.16
25
10417
10417
191
10417
0.00
95
10473
0.53
87
10417
0.00
23
19.2k
19.23k
0.16
103
19.23k
0.16
51
19.20k
0.00
47
19.23k
0.16
12
57.6k
57.14k
-0.79
34
58.82k
2.12
16
57.60k
0.00
15
115.2k
117.6k
2.12
16
111.1k
-3.55
115.2k
0.00
DS40001413D-page 284
PIC12(L)F1822/16(L)F1823
26.3.1
AUTO-BAUD DETECT
FIGURE 26-6:
TABLE 26-6:
BRG16
BRGH
BRG Base
Clock
BRG ABD
Clock
FOSC/64
FOSC/512
FOSC/16
FOSC/128
FOSC/16
FOSC/128
FOSC/4
FOSC/32
1
Note:
BRG Value
0000h
RX pin
001Ch
Start
Edge #1
bit 1
bit 0
Edge #2
bit 3
bit 2
Edge #3
bit 5
bit 4
Edge #4
bit 7
bit 6
Edge #5
Stop bit
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
SPBRGL
XXh
1Ch
SPBRGH
XXh
00h
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
DS40001413D-page 285
PIC12(L)F1822/16(L)F1823
26.3.2
AUTO-BAUD OVERFLOW
26.3.3
AUTO-WAKE-UP ON BREAK
26.3.3.1
Special Considerations
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all 0s. This must be 10 or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
DS40001413D-page 286
PIC12(L)F1822/16(L)F1823
FIGURE 26-7:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Auto Cleared
WUE bit
RX/DT Line
RCIF
Note 1:
FIGURE 26-8:
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
OSC1
Auto Cleared
Note 1
RCIF
Sleep Command Executed
Note 1:
2:
Sleep Ends
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
DS40001413D-page 287
PIC12(L)F1822/16(L)F1823
26.3.4
26.3.4.1
26.3.5
FIGURE 26-9:
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
bit 11
Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB
(send Break
control bit)
DS40001413D-page 288
Auto Cleared
PIC12(L)F1822/16(L)F1823
26.4
26.4.1
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
26.4.1.1
Master Clock
26.4.1.2
Clock Polarity
26.4.1.3
26.4.1.4
1.
2.
3.
4.
5.
6.
7.
8.
DS40001413D-page 289
PIC12(L)F1822/16(L)F1823
FIGURE 26-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
Word 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
1
Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 26-11:
bit 0
bit 2
bit 1
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 26-7:
Name
Bit 6
ABDOVF
GIE
PIE1
PIR1
BAUDCON
INTCON
RCSTA
Bit 2
Bit 1
Bit 0
Register on
Page
BRG16
WUE
ABDEN
279
IOCIE
TMR0IF
INTF
IOCIF
86
SSPIE
CCP1IE
TMR2IE
TMR1IE
87
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
89
CREN
ADDEN
FERR
OERR
RX9D
Bit 5
Bit 4
Bit 3
RCIDL
SCKP
PEIE
TMR0IE
INTE
TMR1GIE
ADIE
RCIE
TXIE
TMR1GIF
ADIF
RCIF
SPEN
RX9
SREN
SPBRGL
SPBRGH
278
BRG<7:0>
280*
BRG<15:8>
280*
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
CSRC
TX9
TXEN
BRGH
TRMT
TX9D
TXREG
TXSTA
Legend:
Note
*
1:
SYNC
SENDB
270*
277
= unimplemented location, read as 0. Shaded cells are not used for Synchronous Master Transmission.
Page provides register information.
PIC16(L)F1823 only.
DS40001413D-page 290
PIC12(L)F1822/16(L)F1823
26.4.1.5
26.4.1.6
Slave Clock
26.4.1.7
26.4.1.8
26.4.1.9
1.
DS40001413D-page 291
PIC12(L)F1822/16(L)F1823
FIGURE 26-12:
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit 0
RCIF bit
(Interrupt)
Read
RCREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 26-8:
Name
Bit 6
ABDOVF
GIE
PIE1
PIR1
BAUDCON
INTCON
Bit 1
Bit 0
Register
on Page
BRG16
WUE
ABDEN
279
IOCIE
TMR0IF
INTF
IOCIF
86
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
87
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
Bit 4
Bit 3
RCIDL
SCKP
PEIE
TMR0IE
INTE
TMR1GIE
ADIE
RCIE
TMR1GIF
ADIF
RCIF
RCREG
RCSTA
Bit 2
Bit 5
RX9
SREN
CREN
ADDEN
89
273*
FERR
OERR
RX9D
278
SPBRGL
BRG<7:0>
280*
SPBRGH
BRG<15:8>
280*
TRISA
TRISC
(1)
TXSTA
Legend:
*
Note 1:
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
277
= unimplemented location, read as 0. Shaded cells are not used for Synchronous Master Reception.
Page provides register information.
PIC16(L)F1823 only.
DS40001413D-page 292
PIC12(L)F1822/16(L)F1823
26.4.2
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
1.
2.
3.
4.
26.4.2.1
5.
26.4.2.2
1.
2.
3.
4.
5.
6.
7.
8.
TABLE 26-9:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
279
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
89
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
278
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
TRMT
TX9D
Name
BAUDCON
INTCON
TXREG
TXSTA
Legend:
*
Note 1:
TX9
TXEN
SYNC
SENDB
BRGH
270*
277
= unimplemented location, read as 0. Shaded cells are not used for Synchronous Slave Transmission.
Page provides register information.
PIC16(L)F1823 only.
DS40001413D-page 293
PIC12(L)F1822/16(L)F1823
26.4.2.3
26.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
279
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
89
OERR
RX9D
RCREG
RX9
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
277
TXSTA
Legend:
*
Note 1:
SREN
CREN
ADDEN
273*
RCSTA
FERR
278
= unimplemented location, read as 0. Shaded cells are not used for Synchronous Slave Reception.
Page provides register information.
PIC16(L)F1823 only.
DS40001413D-page 294
PIC12(L)F1822/16(L)F1823
26.5
26.5.1
26.5.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
26.5.3
DS40001413D-page 295
PIC12(L)F1822/16(L)F1823
27.0
FIGURE 27-1:
Timer0 Module
FOSC/4
T0CKI
CPSCH<3:0>
CPSON(2)
Set
TMR0IF
TMR0CS
T0XCS
0
1
TMR0
Overflow
CPSRNG<1:0>
CPSON
CPS0
Capacitive
Sensing
Oscillator
CPS1
CPSOSC
Timer1 Module
T1CS<1:0>
CPS2
CPS3
CPS4(1)
Ref-
(1)
CPS5
0
DAC_output
Int.
Ref.
CPSOUT
CPS6(1)
0
Ref+
CPS7(1)
CPSCLK
1 FVR
Buffer2
FOSC
FOSC/4
T1OSC/
T1CKI
EN
TMR1H:TMR1L
T1GSEL<1:0>
T1G
Timer1 Gate
Control Logic
sync_C1OUT
sync_C2OUT
CPSRM
Note 1:
2:
Reference CPSCON1 register (Register 27-2) for channels implemented on each device.
If CPSON = 0, disabling capacitive sensing, no channel is selected.
DS40001413D-page 296
PIC12(L)F1822/16(L)F1823
FIGURE 27-2:
Oscillator Module
VDD
(1)
(2)
CPSx
(1)
Analog Pin
(2)
CPSCLK
Internal
References
Ref-
0
1
0
Ref+
DAC_output 1
FVR Buffer2
CPSRM
Note 1:
2:
DS40001413D-page 297
PIC12(L)F1822/16(L)F1823
27.1
Analog MUX
27.2
DS40001413D-page 298
27.3
Voltage References
The capacitive sensing oscillator uses voltage references to provide two voltage thresholds for oscillation.
The upper voltage threshold is referred to as Ref+ and
the lower voltage threshold is referred to as Ref-.
The user can elect to use fixed voltage references,
which are internal to the capacitive sensing oscillator,
or variable voltage references, which are supplied by
the Fixed Voltage Reference (FVR) module and the
Digital-to-Analog Converter (DAC) module.
When the fixed voltage references are used, the VSS
voltage determines the lower threshold level (Ref-) and
the VDD voltage determines the upper threshold level
(Ref+).
When the variable voltage references are used, the
DAC voltage determines the lower threshold level
(Ref-) and the FVR voltage determines the upper
threshold level (Ref+). An advantage of using these reference sources is that oscillation frequency remains
constant with changes in VDD.
Different oscillation frequencies can be obtained
through the use of these variable voltage references.
The more the upper voltage reference level is lowered
and the more the lower voltage reference level is
raised, the higher the capacitive sensing oscillator frequency becomes.
Selection between the voltage references is controlled
by the CPSRM bit of the CPSCON0 register. Setting
this bit selects the variable voltage references and
clearing this bit selects the fixed voltage references.
Please see Section 14.0 Fixed Voltage Reference
(FVR) and Section 17.0 Digital-to-Analog Converter
(DAC) Module for more information on configuring the
variable voltage levels.
PIC12(L)F1822/16(L)F1823
27.4
Current Ranges
TABLE 27-1:
CPSRM
Note 1:
Fixed
Variable
CPSRNG<1:0>
Current Range(1)
00
Off
01
Low
10
Medium
11
High
00
Noise Detection
01
Low
10
Medium
11
High
DS40001413D-page 299
PIC12(L)F1822/16(L)F1823
27.5
Timer Resources
27.7
27.6
27.6.1
TIMER0
27.6.2
TIMER1
TABLE 27-2:
TMR1ON
TMR1GE
Timer1 Operation
Off
Off
On
DS40001413D-page 300
Software Control
27.7.1
NOMINAL FREQUENCY
(NO CAPACITIVE LOAD)
27.7.2
REDUCED FREQUENCY
(ADDITIONAL CAPACITIVE LOAD)
PIC12(L)F1822/16(L)F1823
27.7.3
FREQUENCY THRESHOLD
27.8
DS40001413D-page 301
PIC12(L)F1822/16(L)F1823
REGISTER 27-1:
R/W-0/0
R/W-0/0
U-0
U-0
CPSON
CPSRM
R/W-0/0
R/W-0/0
CPSRNG<1:0>
R-0/0
R/W-0/0
CPSOUT
T0XCS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0
bit 3-2
bit 0
DS40001413D-page 302
PIC12(L)F1822/16(L)F1823
REGISTER 27-2:
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0(1)
R/W-0/0
R/W-0/0
CPSCH<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3-0
Note 1:
DS40001413D-page 303
PIC12(L)F1822/16(L)F1823
TABLE 27-3:
Name
ANSA1
ANSA0
118
ANSC1
ANSC0
122
CPSOUT
T0XCS
302
CPSCH1
CPSCH0
303
TMR0IF
INTF
IOCIF
86
Bit 6
Bit 5
Bit 4
ANSELA
ANSA4
ANSA2
ANSELC(1)
ANSC3
ANSC2
CPSCON0
CPSON
CPSRM
CPSRNG1 CPSRNG0
CPSCON1
CPSCH3(1) CPSCH2(1)
GIE
PEIE
TMR0IE
INTE
INTCON
OPTION_REG
Bit 3
Bit 0
Bit 7
IOCIE
Bit 2
Bit 1
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS2
PS1
PS0
164
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1ON
173
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
117
TRISC(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
121
Legend: = Unimplemented locations, read as 0. Shaded cells are not used by the CPS module.
Note 1: PIC16(L)F1823 only.
DS40001413D-page 304
PIC12(L)F1822/16(L)F1823
28.0
IN-CIRCUIT SERIAL
PROGRAMMING (ICSP)
28.1
FIGURE 28-1:
1
VPP
2
VDD
3
VSS
4
ICSP_DATA
5
ICSP_CLOCK
6
NC
RJ11-6PIN
To MPLAB ICD 2
R1
To Target Board
270 Ohm
LM431BCMX
1
2 A
K
3 A U1
6 A
NC 4
7 A
NC 5
R2
VREF
8
10k 1%
Note:
R3
24k 1%
DS40001413D-page 305
PIC12(L)F1822/16(L)F1823
28.2
FIGURE 28-2:
VDD
ICSPDAT
NC
2 4 6
ICSPCLK
1 3 5
VPP/MCLR
VSS
Target
PC Board
Bottom Side
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
28.3
FIGURE 28-3:
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
DS40001413D-page 306
PIC12(L)F1822/16(L)F1823
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 28-4 for more
information.
FIGURE 28-4:
Device to be
Programmed
VDD
VDD
VDD
VPP
MCLR/VPP
VSS
VSS
Data
ICSPDAT
Clock
ICSPCLK
To Normal Connections
DS40001413D-page 307
PIC12(L)F1822/16(L)F1823
29.0
29.1
Read-Modify-Write Operations
Byte Oriented
Bit Oriented
Literal and Control
The literal and control category contains the most varied instruction word format.
TABLE 29-1:
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
mm
TABLE 29-2:
ABBREVIATION
DESCRIPTIONS
Field
PC
Program Counter
TO
Time-out bit
C
DC
Z
PD
DS40001413D-page 308
Description
Carry bit
Digit carry bit
Zero bit
Power-down bit
PIC12(L)F1822/16(L)F1823
FIGURE 29-1:
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
k (literal)
k (literal)
0
k (literal)
5 4
0
k (literal)
0
k (literal)
6
n
0
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSR Increment instructions
13
OPCODE
2 1
0
n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
DS40001413D-page 309
PIC12(L)F1822/16(L)F1823
TABLE 29-3:
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
1(2)
1(2)
00
00
1, 2
1, 2
01
01
2
2
1, 2
1, 2
f, b
f, b
1 (2)
1 (2)
01
01
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
DS40001413D-page 310
PIC12(L)F1822/16(L)F1823
TABLE 29-3:
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
k
k
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
ADDFSR
MOVIW
n, k
n mm
MOVWI
k[n]
n mm
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
00
00
00
00
00
00
0000
0000
0000
0000
0000
0000
0110
0000
0110
0000
0110
0110
0100 TO, PD
0000
0010
0001
0011 TO, PD
0fff
INHERENT OPERATIONS
1
1
1
1
1
1
C-COMPILER OPTIMIZED
k[n]
1
1
11
00
2, 3
1
1
11
00
2
2, 3
11
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
DS40001413D-page 311
PIC12(L)F1822/16(L)F1823
29.2
Instruction Descriptions
ADDFSR
ANDLW
Syntax:
Syntax:
[ label ] ANDLW
Operands:
-32 k 31
n [ 0, 1]
Operands:
0 k 255
Operation:
Operation:
FSR(n) + k FSR(n)
Status Affected:
Status Affected:
None
Description:
Description:
AND W with f
FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds
will cause the FSR to wrap-around.
ADDLW
ANDWF
Syntax:
[ label ] ADDLW
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d 0,1
Operation:
Operands:
0 k 255
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Description:
ADDWF
Add W and f
f,d
Status Affected:
Description:
ASRF
Syntax:
[ label ] ADDWF
Syntax:
[ label ] ASRF
Operands:
0 f 127
d 0,1
Operands:
0 f 127
d [0,1]
Operation:
Operation:
(f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
f,d
Status Affected:
C, DC, Z
Description:
ADDWFC
Syntax:
[ label ] ADDWFC
Operands:
0 f 127
d [0,1]
Operation:
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data memory location f. If d is 0, the result is
placed in W. If d is 1, the result is
placed in data memory location f.
DS40001413D-page 312
f {,d}
Status Affected:
C, Z
Description:
f {,d}
PIC12(L)F1822/16(L)F1823
BCF
Bit Clear f
Syntax:
[ label ] BCF
BTFSC
f,b
Syntax:
Operands:
0 f 127
0b7
Operands:
Operation:
0 (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
BRA
Relative Branch
BTFSS
Syntax:
Syntax:
Operands:
0 f 127
0b<7
Operands:
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k PC
Status Affected:
None
Status Affected:
None
Description:
Description:
BRW
Syntax:
[ label ] BRW
Operands:
None
Operation:
(PC) + (W) PC
Status Affected:
None
Description:
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 127
0b7
f,b
Operation:
1 (f<b>)
Status Affected:
None
Description:
DS40001413D-page 313
PIC12(L)F1822/16(L)F1823
CALL
Call Subroutine
CLRWDT
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 k 2047
Operands:
None
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Operation:
Status Affected:
None
00h WDT
0 WDT prescaler,
1 TO
1 PD
Description:
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
CALLW
COMF
Complement f
Syntax:
[ label ] CALLW
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
(PC) +1 TOS,
(W) PC<7:0>,
(PCLATH<6:0>) PC<14:8>
0 f 127
d [0,1]
Operation:
(f) (destination)
Status Affected:
Description:
DECF
Decrement f
Syntax:
f,d
Status Affected:
None
Description:
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0 f 127
Operands:
Operation:
00h (f)
1Z
0 f 127
d [0,1]
Operation:
(f) - 1 (destination)
Status Affected:
Status Affected:
Description:
Description:
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h (W)
1Z
Status Affected:
Description:
DS40001413D-page 314
PIC12(L)F1822/16(L)F1823
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
GOTO
Unconditional Branch
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
GOTO k
INCFSZ f,d
IORLW k
Operands:
0 k 2047
Operands:
0 k 255
Operation:
k PC<10:0>
PCLATH<4:3> PC<12:11>
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
INCF f,d
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
Status Affected:
Status Affected:
Description:
Description:
IORWF
f,d
DS40001413D-page 315
PIC12(L)F1822/16(L)F1823
LSLF
MOVF
Syntax:
[ label ] LSLF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<7>) C
(f<6:0>) dest<7:1>
0 dest<0>
Operation:
(f) (dest)
f {,d}
Status Affected:
C, Z
Description:
register f
Description:
Words:
Cycles:
Syntax:
[ label ] LSRF
Operands:
0 f 127
d [0,1]
Operation:
0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
C, Z
Description:
DS40001413D-page 316
MOVF
FSR, 0
After Instruction
W = value in FSR register
Z = 1
LSRF
f {,d}
register f
MOVF f,d
Status Affected:
Example:
Move f
PIC12(L)F1822/16(L)F1823
MOVIW
Move INDFn to W
MOVLP
Syntax:
Syntax:
[ label ] MOVLP k
Operands:
0 k 127
Operands:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
Operation:
INDFn W
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
Status Affected:
Operation:
k PCLATH
Status Affected:
None
Description:
MOVLW
Move literal to W
Syntax:
[ label ]
0 k 255
Operation:
k (W)
Status Affected:
None
Description:
The 8-bit literal k is loaded into W register. The dont cares will assemble as
0s.
Words:
1
1
Mode
Syntax
mm
Cycles:
Preincrement
++FSRn
00
Example:
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
MOVLB
Syntax:
[ label ] MOVLB k
Operands:
0 k 15
Operation:
k BSR
Status Affected:
None
Description:
MOVLW k
Operands:
Predecrement
MOVLW
0x5A
After Instruction
W =
MOVWF
Move W to f
Syntax:
[ label ]
0x5A
MOVWF
Operands:
0 f 127
Operation:
(W) (f)
Status Affected:
None
Description:
Words:
Cycles:
Example:
MOVWF
OPTION
Before Instruction
OPTION
W
After Instruction
OPTION
W
=
=
0xFF
0x4F
=
=
0x4F
0x4F
DS40001413D-page 317
PIC12(L)F1822/16(L)F1823
MOVWI
Move W to INDFn
NOP
No Operation
Syntax:
Syntax:
[ label ]
Operands:
None
n [0,1]
mm [00,01, 10, 11]
-32 k 31
Description:
No operation.
Words:
Cycles:
Operands:
Operation:
Status Affected:
W INDFn
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
None
Mode
Syntax
mm
Preincrement
++FSRn
00
Predecrement
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
NOP
Operation:
No operation
Status Affected:
None
Example:
NOP
OPTION
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W) OPTION_REG
Status Affected:
None
Description:
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
None
Operation:
Status Affected:
None
Description:
DS40001413D-page 318
PIC12(L)F1822/16(L)F1823
RETFIE
RETURN
Syntax:
[ label ]
Syntax:
[ label ]
None
RETFIE
RETURN
Operands:
None
Operands:
Operation:
TOS PC,
1 GIE
Operation:
TOS PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Words:
Cycles:
Example:
RETFIE
After Interrupt
PC =
GIE =
TOS
1
RETLW
Syntax:
[ label ]
Operands:
0 k 255
Operation:
k (W);
TOS PC
Status Affected:
None
Description:
Words:
Cycles:
Example:
TABLE
RETLW k
RLF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
RLF
Operation:
Status Affected:
Description:
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
f,d
Words:
Cycles:
Example:
RLF
Register f
REG1,0
Before Instruction
REG1
C
After Instruction
REG1
W
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0x07
value of k8
DS40001413D-page 319
PIC12(L)F1822/16(L)F1823
SUBLW
Syntax:
[ label ]
RRF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
Status Affected:
C, DC, Z
Status Affected:
Description:
Description:
The W register is subtracted (2s complement method) from the 8-bit literal
k. The result is placed in the W register.
RRF f,d
SUBLW k
Operands:
0 k 255
Operation:
k - (W) W)
Register f
C=0
Wk
C=1
Wk
DC = 0
W<3:0> k<3:0>
DC = 1
W<3:0> k<3:0>
SLEEP
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
Status Affected:
C, DC, Z
Description:
SLEEP
Operands:
None
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected:
TO, PD
Description:
DS40001413D-page 320
SUBWF f,d
C=0
Wf
C=1
Wf
DC = 0
W<3:0> f<3:0>
DC = 1
W<3:0> f<3:0>
SUBWFB
Syntax:
SUBWFB
Operands:
0 f 127
d [0,1]
Operation:
f {,d}
Status Affected:
C, DC, Z
Description:
PIC12(L)F1822/16(L)F1823
SWAPF
Swap Nibbles in f
XORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Operation:
(W) .XOR. k W)
Status Affected:
Description:
Operation:
SWAPF f,d
Status Affected:
None
Description:
TRIS
Syntax:
[ label ] TRIS f
XORWF
XORLW k
Exclusive OR W with f
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
XORWF
f,d
Operands:
5f7
Operation:
Operation:
Status Affected:
None
Status Affected:
Description:
Description:
DS40001413D-page 321
PIC12(L)F1822/16(L)F1823
30.0
ELECTRICAL SPECIFICATIONS
Power dissipation is calculated as follows: PDIS = VDD x {IDD IOH} + {(VDD VOH) x IOH} + (VOl x IOL).
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.
DS40001413D-page 322
PIC12(L)F1822/16(L)F1823
PIC12F1822/16F1823 VOLTAGE FREQUENCY GRAPH, -40C TA +125C
FIGURE 30-1:
VDD (V)
5.5
2.5
1.8
4
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-1 for each Oscillator modes supported frequencies.
VDD (V)
FIGURE 30-2:
3.6
2.5
1.8
0
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-1 for each oscillator modes supported frequencies.
DS40001413D-page 323
PIC12(L)F1822/16(L)F1823
FIGURE 30-3:
125
5%
Temperature (C)
85
3%
60
2%
25
0
-20
-40
1.8
5%
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001413D-page 324
PIC12(L)F1822/16(L)F1823
30.1
PIC12LF1822/16LF1823
PIC12F1822/16F1823
Param.
No.
D001
Sym.
VDD
D001
D002*
VDR
D002*
Characteristic
Min.
Typ
Max.
Units
Conditions
PIC12LF1822/16LF1823
1.8
2.5
3.6
3.6
V
V
FOSC 16 MHz:
FOSC 32 MHz (Note 2)
PIC12F1822/16F1823
1.8
2.5
5.5
5.5
V
V
FOSC 16 MHz:
FOSC 32 MHz (Note 2)
Supply Voltage
1.5
PIC12F1822/16F1823
1.7
1.6
PIC12LF1822/16LF1823
0.8
PIC12F1822/16F1823
1.4
VPOR*
VPORR*
D003
VADFVR
-8
-8
-8
6
6
6
D003A
VCDAFVR
-11
-11
-11
7
7
7
D003C* TCVFVR
-114
ppm/
C
D003D* VFVR/
VIN
0.225
%/V
D004*
0.05
V/ms
SVDD
Note
DS40001413D-page 325
PIC12(L)F1822/16(L)F1823
FIGURE 30-4:
VDD
VPOR
VPORR
VSS
NPOR(1)
POR REARM
VSS
TVLOW(2)
Note 1:
2:
3:
DS40001413D-page 326
TPOR(3)
PIC12(L)F1822/16(L)F1823
30.2
PIC12LF1822/16LF1823
PIC12F1822/16F1823
Param
No.
Device
Characteristics
Units
Conditions
Min.
Typ
Max.
5.0
15
1.8
8.0
19
3.0
24
36
1.8
30
48
3.0
32
66
5.0
D010A
5.0
21
1.8
7.5
25
3.0
D010A
24
60
1.8
30
70
3.0
32
80
5.0
60
115
1.8
111
200
3.0
82
135
1.8
141
225
3.0
200
320
5.0
D012
145
280
1.8
260
460
3.0
D012
165
300
1.8
290
500
3.0
368
700
5.0
34
170
1.8
59
250
3.0
60
200
1.8
92
260
3.0
126
350
5.0
118
250
1.8
210
420
3.0
VDD
Note
D011
D011
D013
D013
D014
Note 1:
2:
3:
4:
5:
FOSC = 1 MHz
XT Oscillator mode
FOSC = 1 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
FOSC = 1 MHz
EC Oscillator mode, Medium-power mode
FOSC = 1 MHz
EC Oscillator mode
Medium-power mode
FOSC = 4 MHz
EC Oscillator mode,
Medium-power mode
DS40001413D-page 327
PIC12(L)F1822/16(L)F1823
30.2
PIC12LF1822/16LF1823
PIC12F1822/16F1823
Param
No.
Device
Characteristics
Conditions
Min.
Typ
Max.
Units
143
260
1.8
240
450
3.0
300
550
5.0
D015
2.0
20
1.8
4.0
22
3.0
D015
21
45
1.8
27
50
3.0
28
60
5.0
110
250
1.8
150
280
3.0
132
190
1.8
165
230
3.0
D014
D016
D016
VDD
210
280
5.0
0.55
0.8
mA
1.8
0.8
1.25
mA
3.0
D017*
0.6
0.9
mA
1.8
0.9
1.4
mA
3.0
1.0
1.5
mA
5.0
0.8
1.2
mA
1.8
1.3
1.9
mA
3.0
0.8
1.2
mA
1.8
1.3
1.8
mA
3.0
D018
1.5
2.0
mA
5.0
D019
2.2
3.3
mA
3.0
2.3
3.6
mA
3.6
D019
2.2
3.3
mA
3.0
2.3
3.6
mA
5.0
Note 1:
2:
3:
4:
5:
FOSC = 4 MHz
EC Oscillator mode
Medium-power mode
(1, 2)
D017*
D018
Note
FOSC = 31 kHz
LFINTOSC mode
FOSC = 31 kHz
LFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode
FOSC = 32 MHz
HFINTOSC mode (Note 3)
FOSC = 32 MHz
HFINTOSC mode (Note 3)
DS40001413D-page 328
PIC12(L)F1822/16(L)F1823
30.2
PIC12LF1822/16LF1823
PIC12F1822/16F1823
Param
No.
Device
Characteristics
Max.
Units
Conditions
Min.
Typ
2.0
3.1
mA
3.0
2.5
3.5
mA
3.6
2.0
3.1
mA
3.0
2.5
3.5
mA
5.0
210
425
1.8
470
800
3.0
350
435
1.8
550
800
3.0
620
850
5.0
VDD
Note
Note 1:
2:
3:
4:
5:
FOSC = 32 MHz
HS Oscillator mode (Note 4)
FOSC = 32 MHz
HS Oscillator mode (Note 4)
FOSC = 4 MHz
EXTRC mode (Note 5)
FOSC = 4 MHz
EXTRC mode (Note 5)
DS40001413D-page 329
PIC12(L)F1822/16(L)F1823
30.3
PIC12LF1822/16LF1823
PIC12F1822/16F1823
Param
No.
Device Characteristics
Power-down Base Current
Min.
Typ
Max.
+85C
Max.
+125C
Units
Conditions
VDD
D022
0.02
1.0
4.0
0.03
1.8
4.8
3.0
D022
20
40
50
1.8
22
45
55
3.0
24
50
60
5.0
0.3
1.8
10.5
1.8
0.5
2.0
16
3.0
20
41
56
1.8
22
46
61
3.0
D023
D023
D023A
D023A
Note
(IPD)(2)
1.8
24
51
71
5.0
12
25
35
1.8
13
27
37
3.0
32
65
70
1.8
38
75
80
3.0
68
115
120
5.0
D024
8.0
15
20
3.0
D024
30
55
65
3.0
33
75
85
5.0
D025
0.65
4.0
7.0
1.8
2.3
4.5
7.5
3.0
D025
20
42
55
1.8
23
45
60
3.0
25
48
70
5.0
0.1
1.8
4.0
1.8
0.1
2.0
5.0
3.0
20
40
55
1.8
22
45
60
3.0
24
50
70
5.0
D026
D026
Note 1:
2:
3:
DS40001413D-page 330
PIC12(L)F1822/16(L)F1823
30.3
PIC12LF1822/16LF1823
PIC12F1822/16F1823
Param
No.
Device Characteristics
Max.
+85C
Max.
+125C
Units
250
1.8
250
3.0
280
1.8
280
3.0
Conditions
Typ
Min.
VDD
280
5.0
D027
2.2
7.0
10
1.8
4.2
9.0
12
3.0
D027
21
41
45
1.8
23
47
55
3.0
24
53
68
5.0
6.3
16
1.8
7.9
12
21
3.0
21
45
50
1.8
23
55
60
3.0
D027A
D027A
D027B
D027B
D028
D028
D028A
D028A
Note 1:
2:
3:
Note
(2)
25
60
75
5.0
16
25
35
1.8
41
45
45
3.0
23
62
100
1.8
25
90
105
3.0
26
100
115
5.0
8.0
17
22
1.8
8.1
20
25
3.0
30
50
55
1.8
33
60
65
3.0
35
65
85
5.0
8.2
18
24
1.8
8.3
21
27
3.0
30
51
56
1.8
32
61
66
3.0
33
67
87
5.0
DS40001413D-page 331
PIC12(L)F1822/16(L)F1823
30.3
PIC12LF1822/16LF1823
PIC12F1822/16F1823
Param
No.
Device Characteristics
Typ
Max.
+85C
Max.
+125C
Units
30
50
60
31
55
70
60
85
62
64
Min.
VDD
Note
1.8
3.0
90
1.8
90
95
3.0
95
100
5.0
31
51
61
1.8
32
56
71
3.0
61
85
90
1.8
63
90
95
3.0
65
95
100
5.0
D028B
D028C
D028C
Note 1:
2:
3:
Conditions
(2)
DS40001413D-page 332
PIC12(L)F1822/16(L)F1823
30.4
DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E
DC CHARACTERISTICS
Param
No.
Sym.
VIL
Characteristic
Typ
Max.
Units
Conditions
0.8
0.15 VDD
0.2 VDD
0.3 VDD
D030
D030A
D031
0.8
0.2 VDD
0.3 VDD
2.0
0.25 VDD +
0.8
0.8 VDD
0.7 VDD
D040
D040A
D041
2.1
D042
MCLR
0.8 VDD
D043A
0.7 VDD
D043B
0.9 VDD
IIL
D060
I/O ports
125
nA
1000
nA
D061
MCLR(3)
50
200
nA
25
25
100
140
200
300
0.6
VDD - 0.7
15
pF
50
pF
IPUR
D070*
VOL
D080
VOH
D090
D101A* CIO
*
Note 1:
2:
3:
4:
DS40001413D-page 333
PIC12(L)F1822/16(L)F1823
30.5
DC CHARACTERISTICS
Param
No.
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
VIHH
8.0
9.0
D111
IDDVPP
10
mA
D112
VBE
2.7
VDD
max.
D113
VPEW
VDD
min.
VDD
max.
D114
1.0
mA
D115
5.0
mA
D116
ED
Byte Endurance
100K
E/W
D117
VDRW
VDD
min.
VDD
max.
(Note 3, Note 4)
D118
TDEW
4.0
5.0
ms
D119
TRETD
Characteristic Retention
40
Year
Provided no other
specifications are violated
D120
TREF
1M
10M
E/W
-40C to +85C
D121
EP
Cell Endurance
10K
E/W
D122
VPR
VDD
min.
VDD
max.
D123
TIW
2.5
ms
D124
TRETD
Characteristic Retention
40
Year
Note 1:
2:
3:
4:
Provided no other
specifications are violated
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Self-write and Block Erase.
Refer to Section 11.2 Using the Data EEPROM for a more detailed discussion on data EEPROM endurance.
Required only if single-supply programming is disabled.
The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the MPLAB ICD 2 VPP voltage must be placed
between the MPLAB ICD 2 and target system when programming or debugging with the MPLAB ICD 2.
DS40001413D-page 334
PIC12(L)F1822/16(L)F1823
30.6
Thermal Considerations
TH02
TH03
TH04
TH05
Sym.
Characteristic
JA
JC
TJMAX
PD
Typ.
Units
Conditions
89.3
C/W
149.5
C/W
56.7
C/W
39.4
C/W
70.0
C/W
95.3
C/W
100
C/W
45.7
C/W
31.8
C/W
43.1
C/W
39.9
C/W
9.0
C/W
40.3
C/W
32.0
C/W
31.0
C/W
24.4
C/W
6.3
C/W
24.4
C/W
150
PD = PINTERNAL + PI/O
TH06
PI/O
TH07
PDER
Derated Power
Legend:
TBD = To Be Determined
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature. TJ = Junction Temperature.
DS40001413D-page 335
PIC12(L)F1822/16(L)F1823
30.7
FIGURE 30-5:
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCKx
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
DS40001413D-page 336
PIC12(L)F1822/16(L)F1823
30.8
AC Characteristics: PIC12(L)F1822/16(L)F1823-I/E
FIGURE 30-6:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1/CLKIN
OS02
OS04
OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 30-1:
Sym.
FOSC
Characteristic
External CLKIN Frequency(1)
Oscillator Frequency(1)
OS02
TOSC
Oscillator Period(1)
OS03
TCY
OS04*
TosH,
TosL
TosR,
TosF
OS05*
Min.
Typ
Max.
Units
Conditions
DC
0.5
MHz
DC
MHz
DC
32
MHz
32.768
kHz
LP Oscillator mode
0.1
MHz
XT Oscillator mode
MHz
20
MHz
DC
MHz
RC Oscillator mode
27
LP Oscillator mode
250
ns
XT Oscillator mode
50
ns
HS Oscillator mode
31.25
ns
EC Oscillator mode
30.5
LP Oscillator mode
250
10,000
ns
XT Oscillator mode
50
1,000
ns
HS Oscillator mode
250
ns
RC Oscillator mode
200
DC
ns
TCY = FOSC/4
LP oscillator
100
ns
XT oscillator
20
ns
HS oscillator
ns
LP oscillator
ns
XT oscillator
ns
HS oscillator
DS40001413D-page 337
PIC12(L)F1822/16(L)F1823
TABLE 30-2:
OSCILLATOR PARAMETERS
Sym.
HFOSC
OS08A MFOSC
Characteristic
Internal Calibrated HFINTOSC
Frequency(2)
OS09
LFOSC
OS10*
TIOSC ST HFINTOSC
Wake-up from Sleep Start-up Time
MFINTOSC
Wake-up from Sleep Start-up Time
Freq.
Tolerance
Min.
Typ
Max.
Units
Conditions
2%
16.0
MHz
3%
16.0
MHz
5%
16.0
MHz
-40C TA +125C
2%
500
kHz
3%
500
kHz
5%
500
kHz
-40C TA +125C
25%
31
kHz
-40C TA +125C
3.2
24
35
TABLE 30-3:
Param
No.
Sym.
F10
Typ
Max.
Units
MHz
F11
FSYS
16
32
MHz
F12
TRC
ms
CLK
-0.25%
+0.25%
F13*
Characteristic
Conditions
DS40001413D-page 338
PIC12(L)F1822/16(L)F1823
FIGURE 30-7:
Cycle
Fetch
Read
Execute
Q4
Q1
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS16
OS13
OS18
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
DS40001413D-page 339
PIC12(L)F1822/16(L)F1823
TABLE 30-4:
OS11
OS12
Sym.
TosH2ckL
Characteristic
Min.
Typ
Max.
Units
Conditions
70
ns
VDD = 3.0-5.0V
72
ns
VDD = 3.0-5.0V
(1)
(1)
OS13
TckL2ioV
OS14
OS15
OS16
TioV2ckH
TosH2ioV
TosH2ioI
OS17
TioV2osH
OS18* TioR
OS19* TioF
20
ns
TOSC + 200 ns
50
50
70*
ns
ns
ns
20
ns
25
25
40
15
28
15
72
32
55
30
ns
OS20* Tinp
OS21* Tioc
FIGURE 30-8:
ns
VDD = 3.0-5.0V
VDD = 3.0-5.0V
VDD = 1.8V
VDD = 3.0-5.0V
VDD = 1.8V
VDD = 3.0-5.0V
ns
ns
VDD
MCLR
30
Internal
POR
PWRT
Time-out
33
32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
34
31
34
I/O pins
Note 1: Asserted low.
DS40001413D-page 340
PIC12(L)F1822/16(L)F1823
FIGURE 30-9:
VDD
VBOR and VHYST
VBOR
37
Reset
(due to BOR)
33(1)
DS40001413D-page 341
PIC12(L)F1822/16(L)F1823
TABLE 30-5:
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
30
TMCL
31
12
16
20
ms
32
TOST
1024
Tosc
33*
TPWRT
40
65
140
ms
34*
TIOZ
2.0
35
VBOR
2.55
1.80
2.7
1.9
2.85
2.11
36*
VHYST
20
35
75
mV
-40C to +85C
37*
35
VDD VBOR
VDD = 3.3V-5V,
1:16 Prescaler used
BORV= 0
BORV= 1
FIGURE 30-10:
T0CKI
40
41
42
T1CKI
45
46
47
49
TMR0 or
TMR1
DS40001413D-page 342
PIC12(L)F1822/16(L)F1823
TABLE 30-6:
Sym.
TT0H
40*
Characteristic
T0CKI High Pulse Width
Min.
No Prescaler
TT0L
No Prescaler
TT0P
T0CKI Period
45*
TT1H
ns
ns
0.5 TCY + 20
ns
10
ns
Greater of:
20 or TCY + 40
N
ns
0.5 TCY + 20
ns
15
ns
Asynchronous
TT1L
46*
T1CKI Low
Time
30
ns
Synchronous, No Prescaler
0.5 TCY + 20
ns
15
ns
Asynchronous
30
ns
Greater of:
30 or TCY + 40
N
ns
47*
TT1P
48
FT1
49*
Asynchronous
Units
10
With Prescaler
42*
Max.
0.5 TCY + 20
With Prescaler
41*
Typ
60
ns
32.4
32.768
33.1
kHz
2 TOSC
7 TOSC
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
Timers in Sync
mode
FIGURE 30-11:
CCP
(Capture mode)
CC01
CC02
CC03
Note:
TABLE 30-7:
Characteristic
CCP Input Low Time
CCP Input High Time
CCP Input Period
Min.
Typ
Max.
Units
No Prescaler
0.5TCY + 20
ns
With Prescaler
20
ns
No Prescaler
0.5TCY + 20
ns
With Prescaler
20
ns
3TCY + 40
N
ns
Conditions
DS40001413D-page 343
PIC12(L)F1822/16(L)F1823
TABLE 30-8:
Characteristic
Min.
Typ
Max.
Units
Conditions
AD01
NR
Resolution
10
AD02
EIL
Integral Error
1.7
AD03
EDL
Differential Error
AD04
2.5
AD05
EGN
AD06
AD07
VAIN
Full-Scale Range
AD08
ZAIN
Recommended Impedance of
Analog Voltage Source
Note 1:
2:
3:
4:
Gain Error
bit
LSb VREF = 3.0V
LSb No missing codes
VREF = 3.0V
2.0
1.8
VDD
VSS
VREF
10
TABLE 30-9:
Sym.
AD130* TAD
AD131
TCNV
AD132* TACQ
Characteristic
Min.
Typ
Max.
Units
Conditions
1.0
9.0
TOSC-based
1.0
2.5
6.0
11
TAD
Acquisition Time
5.0
DS40001413D-page 344
PIC12(L)F1822/16(L)F1823
FIGURE 30-12:
BSF ADCON0, GO
AD134
1 TCY
(TOSC/2(1))
AD131
Q4
AD130
A/D CLK
7
A/D Data
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
Sample
DONE
Sampling Stopped
AD132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
FIGURE 30-13:
BSF ADCON0, GO
AD134
(TOSC/2 + TCY(1))
1 TCY
AD131
Q4
AD130
A/D CLK
7
A/D Data
OLD_DATA
ADRES
0
NEW_DATA
ADIF
1 TCY
GO
DONE
Sample
AD132
Sampling Stopped
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
DS40001413D-page 345
PIC12(L)F1822/16(L)F1823
TABLE 30-10: COMPARATOR SPECIFICATIONS
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA 25C
Param
No.
Sym.
Characteristics
Min.
Typ.
Max.
Units
Comments
VICM = VDD/2,
High-Power mode
CM01
VIOFF
7.5
60
mV
CM02
VICM
VDD
CM03
CMRR
50
dB
CM04A
400
800
ns
High-Power mode
CM04B
200
400
ns
High-Power mode
CM04C
TRESP(1)
CM04D
1200
ns
Low-Power mode
550
ns
Low-Power mode
10
45
mV
CM05
TMC2OV
CM06
*
Note 1:
2:
Hysteresis on
Sym.
Characteristics
Min.
Typ.
Max.
Units
DAC01*
CLSB
Step Size
VDD/32
DAC02*
CACC
Absolute Accuracy
1/2
LSb
DAC03*
CR
5K
DAC04*
CST
Settling Time(1)
10
*
Note 1:
Comments
FIGURE 30-14:
CK
US121
US121
DT
US120
Note:
US122
DS40001413D-page 346
PIC12(L)F1822/16(L)F1823
TABLE 30-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40C TA +125C
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
80
ns
3.0-5.5V
1.8-5.5V
100
ns
US121 TCKRF
3.0-5.5V
45
ns
1.8-5.5V
50
ns
US122 TDTRF
3.0-5.5V
45
ns
1.8-5.5V
50
ns
FIGURE 30-15:
Conditions
US125
DT
US126
Note: Refer to Figure 30-5 for load conditions.
Symbol
Characteristic
Min.
Max.
Units
10
ns
15
ns
Conditions
DS40001413D-page 347
PIC12(L)F1822/16(L)F1823
FIGURE 30-16:
SSx
SP70
SCKx
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SP78
SCKx
(CKP = 1)
SP80
bit 6 - - - - - -1
MSb
SDOx
LSb
SP75, SP76
SDIx
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 30-5 for load conditions.
FIGURE 30-17:
SSx
SP81
SCKx
(CKP = 0)
SP71
SP72
SP79
SP73
SCKx
(CKP = 1)
SP80
SDOx
MSb
bit 6 - - - - - -1
SP78
LSb
SP75, SP76
SDIx
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 30-5 for load conditions.
DS40001413D-page 348
PIC12(L)F1822/16(L)F1823
FIGURE 30-18:
SSx
SP70
SCKx
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SP78
SCKx
(CKP = 1)
SP80
MSb
SDOx
LSb
bit 6 - - - - - -1
SP77
SP75, SP76
SDIx
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 30-5 for load conditions.
FIGURE 30-19:
SSx
SCKx
(CKP = 0)
SP71
SP72
SCKx
(CKP = 1)
SP80
SDOx
MSb
bit 6 - - - - - -1
LSb
SP77
SP75, SP76
SDIx
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 30-5 for load conditions.
DS40001413D-page 349
PIC12(L)F1822/16(L)F1823
TABLE 30-14: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min.
Typ
2.25 TCY
ns
SP71* TSCH
TCY + 20
ns
SP72* TSCL
TCY + 20
ns
100
ns
100
ns
3.0-5.5V
10
25
ns
1.8-5.5V
25
50
ns
10
25
ns
SP75* TDOR
SP76* TDOF
SP77* TSSH2DOZ
10
50
ns
SP78* TSCR
10
25
ns
SP79* TSCF
3.0-5.5V
25
50
ns
10
25
ns
3.0-5.5V
50
ns
1.8-5.5V
145
ns
Tcy
ns
50
ns
1.5TCY + 40
ns
SP82* TSSL2DOV
1.8-5.5V
FIGURE 30-20:
SCLx
SP93
SP91
SP90
SP92
SDAx
Start
Condition
Stop
Condition
DS40001413D-page 350
PIC12(L)F1822/16(L)F1823
FIGURE 30-21:
SCLx
SP100
SP90
SP102
SP101
SP106
SP107
SP92
SP91
SDAx
In
SP110
SP109
SP109
SDAx
Out
Note: Refer to Figure 30-5 for load conditions.
Symbol
SP90*
TSU:STA
SP91*
THD:STA
SP92*
TSU:STO
SP93
Characteristic
Start condition
Typ
4700
Max. Units
Setup time
600
Start condition
4000
Hold time
600
Stop condition
4700
Setup time
Hold time
*
Min.
600
4000
600
Conditions
ns
ns
ns
ns
DS40001413D-page 351
PIC12(L)F1822/16(L)F1823
TABLE 30-16: I2C BUS DATA REQUIREMENTS
Param.
No.
Symbol
SP100* THIGH
SP101* TLOW
SP102* TR
SP103* TF
SP106* THD:DAT
SP107* TSU:DAT
SP109* TAA
SP110*
SP111
*
Note 1:
2:
TBUF
CB
Characteristic
Min.
Max.
Units
Conditions
4.0
0.6
SSPx module
1.5TCY
4.7
1.3
SSPx module
1.5TCY
1000
ns
20 + 0.1CB
300
ns
250
ns
20 + 0.1CB
250
ns
ns
0.9
250
ns
100
ns
3500
ns
ns
4.7
1.3
400
pF
CB is specified to be from
10-400 pF
CB is specified to be from
10-400 pF
(Note 2)
(Note 1)
DS40001413D-page 352
PIC12(L)F1822/16(L)F1823
TABLE 30-17: CAP SENSE OSCILLATOR SPECIFICATIONS
Param.
No.
CS01
CS02
Symbol
ISRC
ISNK
Characteristic
Current Source
Current Sink
Min.
Typ
Max.
Units
High
-8
Medium
-1.5
Low
-0.3
High
7.5
Medium
1.5
Low
0.25
CS03
VCTH
Cap Threshold
0.8
mV
CS04
VCTL
Cap Threshold
0.4
mV
CS05
High
525
mV
Medium
375
mV
Low
300
mV
Conditions
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 30-22:
VCTH
VCTL
ISRC
Enabled
ISNK
Enabled
DS40001413D-page 353
PIC12(L)F1822/16(L)F1823
31.0
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
Typical represents the mean of the distribution at 25C. MAXIMUM, Max., MINIMUM or Min. represents
(mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range.
DS40001413D-page 354
PIC12(L)F1822/16(L)F1823
FIGURE 31-1:
25
Max.
Max: 85C + 3
Typical: 25C
IDD (A)
20
15
10
Typical
5
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-2:
80
Max: 85C + 3
Typical: 25C
70
Max.
60
IDD (A)
50
40
Typical
30
20
10
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 355
PIC12(L)F1822/16(L)F1823
FIGURE 31-3:
600
Typical: 25C
500
4 MHz EXTRC
400
IDD (A)
4 MHz XT
300
1 MHz EXTRC
200
100
1 MHz XT
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-4:
1000
Max: 85C + 3
900
800
4 MHz EXTRC
IDD (A)
700
600
4 MHz XT
500
400
1 MHz EXTRC
300
200
1 MHz XT
100
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
DS40001413D-page 356
PIC12(L)F1822/16(L)F1823
FIGURE 31-5:
800
Typical: 25C
700
4 MHz EXTRC
600
IDD (A)
500
400
4 MHz XT
300
1 MHz EXTRC
200
100
1 MHz XT
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-6:
900
Max: 85C + 3
800
4 MHz EXTRC
700
4 MHz XT
IDD (A)
600
500
1 MHz EXTRC
400
300
1 MHz XT
200
100
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 357
PIC12(L)F1822/16(L)F1823
FIGURE 31-7:
18
Max: 85C + 3
Typical: 25C
16
Max.
14
IDD (A)
12
10
8
6
Typical
4
2
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-8:
45
Max: 85C + 3
Typical: 25C
40
Max.
35
IDD (A)
30
Typical
25
20
15
10
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 358
PIC12(L)F1822/16(L)F1823
FIGURE 31-9:
80
Max: 85C + 3
Typical: 25C
70
Max.
60
IDD (A)
50
40
Typical
30
20
10
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-10:
50
Max: 85C + 3
Typical: 25C
45
Max.
40
IDD (A)
35
30
Typical
25
20
15
10
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 359
PIC12(L)F1822/16(L)F1823
FIGURE 31-11:
400
350
4 MHz
Typical: 25C
300
IDD (A)
250
200
150
100
1 MHz
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-12:
,
450
400
4 MHz
Max: 85C + 3
350
IDD (A)
300
250
200
150
1 MHz
100
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
DS40001413D-page 360
PIC12(L)F1822/16(L)F1823
FIGURE 31-13:
450
400
Typical: 25C
350
4 MHz
IDD (A)
300
250
200
1 MHz
150
100
50
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
5.5
6.0
VDD (V)
FIGURE 31-14:
450
Max: 85C + 3
400
4 MHz
350
IDD (A)
300
250
1 MHz
200
150
100
50
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD (V)
DS40001413D-page 361
PIC12(L)F1822/16(L)F1823
FIGURE 31-15:
3.0
Typical: 25C
2.5
32 MHz (PLL)
IDD (mA)
2.0
1.5
16 MHz
1.0
8 MHz
0.5
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
3.6
3.8
VDD (V)
FIGURE 31-16:
3.5
3.0
32 MHz (PLL)
Max: 85C + 3
IDD (mA)
2.5
2.0
16 MHz
1.5
1.0
8 MHz
0.5
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
VDD (V)
DS40001413D-page 362
PIC12(L)F1822/16(L)F1823
FIGURE 31-17:
2.5
Typical: 25C
32 MHz (PLL)
2.0
IDD (mA)
1.5
16 MHz
1.0
8 MHz
0.5
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
5.5
6.0
VDD (V)
FIGURE 31-18:
3.0
32 MHz (PLL)
Max: 85C + 3
2.5
IDD (mA)
2.0
16 MHz
1.5
1.0
8 MHz
0.5
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD (V)
DS40001413D-page 363
PIC12(L)F1822/16(L)F1823
FIGURE 31-19:
25
Max.
IDD (A)
20
15
10
Max: 85C + 3
Typical: 25C
Typical
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-20:
50
45
Max.
40
IDD (A)
35
30
Typical
25
20
15
10
Max: 85C + 3
Typical: 25C
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 364
PIC12(L)F1822/16(L)F1823
FIGURE 31-21:
IDD, MFINTOSC MODE (FOSC = 500 kHz), PIC12LF1822 AND PIC16LF1823 ONLY
200
Max: 85C + 3
Typical: 25C
180
Max.
160
IDD (A)
140
120
Typical
100
80
60
40
20
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-22:
IDD, MFINTOSC MODE (FOSC = 500 kHz), PIC12F1822 AND PIC16F1823 ONLY
350
Max: 85C + 3
Typical: 25C
300
Max.
IDD (A)
250
Typical
200
150
100
50
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 365
PIC12(L)F1822/16(L)F1823
FIGURE 31-23:
2500
32 MHz (PLL)
Typical: 25C
IDD (A)
2000
16 MHz
1500
1000
8 MHz
500
4 MHz
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-24:
3500
32 MHz (PLL)
Max: 85C + 3
3000
IDD (A)
2500
16 MHz
2000
1500
8 MHz
1000
4 MHz
500
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
DS40001413D-page 366
PIC12(L)F1822/16(L)F1823
FIGURE 31-25:
3000
Typical: 25C
32 MHz (PLL)
2500
IDD (A)
2000
16 MHz
1500
8 MHz
1000
4 MHz
500
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-26:
4000
32 MHz (PLL)
Max: 85C + 3
3500
3000
IDD (A)
2500
16 MHz
2000
8 MHz
1500
4 MHz
1000
500
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 367
PIC12(L)F1822/16(L)F1823
FIGURE 31-27:
2.5
Typical: 25C
2.0
20 MHz
IDD (mA)
1.5
1.0
8 MHz
0.5
4 MHz
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-28:
3.0
Max: 85C + 3
2.5
20 MHz
IDD (mA)
2.0
1.5
8 MHz
1.0
0.5
4 MHz
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
DS40001413D-page 368
PIC12(L)F1822/16(L)F1823
FIGURE 31-29:
2500
Typical: 25C
2000
20 MHz
IDD (A)
1500
8 MHz
1000
500
4 MHz
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-30:
3000
Max: 85C + 3
2500
20 MHz
IDD (A)
2000
1500
8 MHz
1000
500
4 MHz
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 369
PIC12(L)F1822/16(L)F1823
FIGURE 31-31:
1.4
Max: 85C + 3
Typical: 25C
1.2
Max.
IPD (A)
1.0
0.8
0.6
0.4
0.2
Typical
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-32:
50
Max: 85C + 3
M
3
Typical: 25C
45
Max.
40
IPD (A)
35
30
Typical
25
20
15
10
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 370
PIC12(L)F1822/16(L)F1823
FIGURE 31-33:
1.2
Max.
Max: 85C + 3
Typical: 25C
1.0
IPD (A
(A)
0.8
Typical
0.6
0.4
0.2
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-34:
50
Max: 85C + 3
M
3
Typical: 25C
45
Max.
40
IPD (A
A)
35
30
Typical
25
20
15
10
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 371
PIC12(L)F1822/16(L)F1823
FIGURE 31-35:
30
Max.
25
IPD (A
A)
20
Typical
15
10
Max: 85C + 3
Typical: 25C
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-36:
120
Max.
Max: 85C + 3
Typical: 25C
100
80
IPD (A)
Typical
60
40
20
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 372
PIC12(L)F1822/16(L)F1823
FIGURE 31-37:
60
Max: 85C + 3
Typical: 25C
50
Max.
IPD (A)
40
Typical
30
20
10
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 373
PIC12(L)F1822/16(L)F1823
FIGURE 31-38:
6.0
Max: 85C + 3
Typical: 25C
5.0
Max.
IPD (A
A)
4.0
3.0
Typical
2.0
1.0
0.0
16
1.6
1
8
1.8
2
0
2.0
2
2
2.2
2
4
2.4
2
6
2.6
2
8
2.8
3
0
3.0
3
2
3.2
3
4
3.4
3
6
3.6
3
8
3.8
VDD (V)
FIGURE 31-39:
50
Max: 85C + 3
Typical: 25C
45
Max.
40
IPD (A)
35
30
Typical
25
20
15
10
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 374
PIC12(L)F1822/16(L)F1823
FIGURE 31-40:
14
Max.
12
IPD (A)
10
8
Typical
6
4
Max: 85C + 3
Typical: 25C
2
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-41:
60
Max: 85C + 3
Typical: 25C
50
Max.
IPD (A)
40
Typical
30
20
10
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 375
PIC12(L)F1822/16(L)F1823
FIGURE 31-42:
60
Max: 85C + 3
Typical: 25C
50
IPD (A
A)
40
Max.
30
Typical
20
10
0
16
1.6
1
8
1.8
2
0
2.0
2
2
2.2
2
4
2.4
2
6
2.6
2
8
2.8
3
0
3.0
3
2
3.2
3
4
3.4
3
6
3.6
3
8
3.8
VDD (V)
FIGURE 31-43:
70
Max.
60
50
IPD (A
A)
Typical
40
30
20
Max: 85C + 3
Typical: 25C
10
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 376
PIC12(L)F1822/16(L)F1823
FIGURE 31-44:
1.70
1.68
Max.
1.66
Voltage (V)
1.64
Typical
1.62
Min.
1.60
1.58
1.56
Max: Typical + 3
Typical: 25C
Min: Typical - 3
1.54
1.52
1.50
-40
-20
20
40
60
80
100
120
100
120
Temperature (C)
FIGURE 31-45:
1.54
Max: Typical + 3
Typical: 25C
Min: Typical - 3
1.52
1.50
Max.
Voltage (V)
1.48
1.46
1.44
Typical
1.42
1.40
Min.
1.38
1.36
1.34
-40
-20
20
40
60
80
Temperature (C)
DS40001413D-page 377
PIC12(L)F1822/16(L)F1823
FIGURE 31-46:
24
22
Max.
Time (mS)
20
18
Typical
16
14
Min.
Max: Typical + 3 (-40C to +125C)
Typical: statistical mean @ 25C
Min: Typical - 3 (-40C to +125C)
12
10
1.5
2.5
3.5
4.5
5.5
Voltage (V)
FIGURE 31-47:
PWRT PERIOD
110
100
Max.
Time (mS)
90
80
Typical
70
Min.
60
Max: Typical + 3 (-40C to +125C)
Typical: statistical mean @ 25C
Min: Typical - 3 (-40C to +125C)
50
40
1.5
2.5
3.5
4.5
5.5
Voltage (V)
DS40001413D-page 378
PIC12(L)F1822/16(L)F1823
FIGURE 31-48:
80
70
Max.
Hysteresis (mV)
60
Typical
50
40
Min.
30
20
Max: Typical + 3
Typical: 25C
Min: Typical - 3
10
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-49:
16
14
Max.
Hysteresis (mV)
12
Typical
10
8
Min.
6
4
Max: Typical + 3
Typical: 25C
Min: Typical - 3
2
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 379
PIC12(L)F1822/16(L)F1823
FIGURE 31-50:
350
300
Time (nS)
250
Max.
200
Typical
150
100
Max: Typical + 3
Typical: 25C
50
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-51:
400
Graph represents
3 Limits
350
Time (nS)
300
250
125C
200
150
Typical
100
-40C
50
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001413D-page 380
PIC12(L)F1822/16(L)F1823
FIGURE 31-52:
50
40
30
Max.
20
10
Typical
0
Min.
-10
-20
Max: Typical + 3
Typical: 25C
Min: Typical - 3
-30
-40
-50
0.0
1.0
2.0
3.0
4.0
5.0
DS40001413D-page 381
PIC12(L)F1822/16(L)F1823
32.0
DEVELOPMENT SUPPORT
32.1
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
DS40001413D-page 382
PIC12(L)F1822/16(L)F1823
32.2
MPLAB XC Compilers
32.3
MPASM Assembler
32.4
32.5
DS40001413D-page 383
PIC12(L)F1822/16(L)F1823
32.6
32.7
DS40001413D-page 384
32.8
32.9
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineers PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming (ICSP).
PIC12(L)F1822/16(L)F1823
32.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
DS40001413D-page 385
PIC12(L)F1822/16(L)F1823
33.0
PACKAGING INFORMATION
33.1
XXXXXXXX
XXXXXNNN
YYWW
Example
12LF1822
E/P e3 017
1010
Example
12LF1822
E/SN1010
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
DS40001413D-page 386
PIC12(L)F1822/16(L)F1823
33.1
Example
MFLO
1010
017
XXXX
YYWW
NNN
PIN 1
TABLE 33-1:
PIN 1
Part Number
Marking
PIC12F1822T-E/MF
MFLO
PIC12F1822T-I/MF
MFMO
PIC12LF1822T-E/MF
MFPO
PIC12LF1822T-I/MF
MFNO
TABLE 33-2:
Part Number
Marking
PIC12F1822T-E/RF
DABO
PIC12F1822T-I/RF
DAAO
PIC12LF1822T-E/RF
DAHO
PIC12LF1822T-I/RF
DAGO
DS40001413D-page 387
PIC12(L)F1822/16(L)F1823
33.1
Example
PIC16F1823
-E/P e3
0910017
Example
PIC16F1823
-E/SL e3
0910017
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
DS40001413D-page 388
PIC12(L)F1822/16(L)F1823
33.1
Example
F1823EST
XXXXXXXX
YYWW
NNN
0910
017
PIN 1
Example
PIN 1
PIC16
F1823
E/ML e
910017
3
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
DS40001413D-page 389
PIC12(L)F1822/16(L)F1823
33.2
Package Details
3
&'
!&" &4# *!(!!&
4%&
&#&
&&255***'
'54
NOTE 1
E1
2
D
A2
A1
e
eB
b1
b
6&!
'!
9'&!
7"')
%!
7,8.
7
7:
;
<
&
&
&
##4
4!!
-
1!&
&
"# &
"# >#&
-
-
##4>#&
.
<
: 9&
-<
-?
&
&
-
9# 4!!
<
)
?
<
1
6 9#>#&
9
* 9#>#&
:
*+
1,
-
!"#$%&" ' ()"&'"!&)
&#*&&&#
+%&, & !&
- '!
!#.#
&"#'
#%!
& "!
!
#%!
& "!
!!
&$#/ !#
'!
#&
.0
1,21!'!
&$& "!
**&
"&&
!
* ,<1
DS40001413D-page 390
PIC12(L)F1822/16(L)F1823
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001413D-page 391
PIC12(L)F1822/16(L)F1823
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001413D-page 392
PIC12(L)F1822/16(L)F1823
!
""#$%& !'
3
&'
!&" &4# *!(!!&
4%&
&#&
&&255***'
'54
DS40001413D-page 393
PIC12(L)F1822/16(L)F1823
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001413D-page 394
PIC12(L)F1822/16(L)F1823
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001413D-page 395
PIC12(L)F1822/16(L)F1823
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001413D-page 396
PIC12(L)F1822/16(L)F1823
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.10 C
1
2X
TOP VIEW
0.10 C
0.05 C
C
SEATING
PLANE
A1
A
8X
(A3)
0.05 C
SIDE VIEW
0.10
C A B
D2
1
L
0.10
C A B
E2
NOTE 1
8X b
0.10
e
2
C A B
BOTTOM VIEW
Microchip Technology Drawing C04-254A Sheet 1 of 2
DS40001413D-page 397
PIC12(L)F1822/16(L)F1823
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Terminals
N
e
Pitch
A
Overall Height
Standoff
A1
A3
Terminal Thickness
Overall Width
E
E2
Exposed Pad Width
D
Overall Length
D2
Exposed Pad Length
b
Terminal Width
Terminal Length
L
K
Terminal-to-Exposed-Pad
MIN
0.45
0.00
1.40
2.20
0.25
0.35
0.20
MILLIMETERS
NOM
8
0.65 BSC
0.50
0.02
0.065 REF
3.00 BSC
1.50
3.00 BSC
2.30
0.30
0.45
-
MAX
0.55
0.05
1.60
2.40
0.35
0.55
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-254A Sheet 2 of 2
DS40001413D-page 398
PIC12(L)F1822/16(L)F1823
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C
X2
E
Y2
X1
G1
G2
SILK SCREEN
Y1
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
Contact Pad to Contact Pad (X6)
G1
Contact Pad to Center Pad (X8)
G2
MIN
MILLIMETERS
NOM
0.65 BSC
MAX
1.60
2.40
2.90
0.35
0.85
0.20
0.30
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2254A
()
2010-2014 Microchip Technology Inc.
DS40001413D-page 399
PIC12(L)F1822/16(L)F1823
()
3
&'
!&" &4# *!(!!&
4%&
&#&
&&255***'
'54
NOTE 1
E1
D
E
A2
L
A1
b1
b
eB
6&!
'!
9'&!
7"')
%!
7,8.
7
7:
;
&
&
&
##4
4!!
-
1!&
&
"# &
"# >#&
-
-
##4>#&
.
<
: 9&
-
&
&
-
9# 4!!
<
)
?
<
1
6 9#>#&
9
* 9#>#&
:
*+
1,
-
!"#$%&" ' ()"&'"!&)
&#*&&&#
+%&, & !&
- '!
!#.#
&"#'
#%!
& "!
!
#%!
& "!
!!
&$#/ !#
'!
#&
.0
1,21!'!
&$& "!
**&
"&&
!
* ,1
DS40001413D-page 400
PIC12(L)F1822/16(L)F1823
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001413D-page 401
PIC12(L)F1822/16(L)F1823
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001413D-page 402
PIC12(L)F1822/16(L)F1823
3
&'
!&" &4# *!(!!&
4%&
&#&
&&255***'
'54
DS40001413D-page 403
PIC12(L)F1822/16(L)F1823
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001413D-page 404
PIC12(L)F1822/16(L)F1823
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001413D-page 405
PIC12(L)F1822/16(L)F1823
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001413D-page 406
PIC12(L)F1822/16(L)F1823
(*
+,
$ -./)0)0%&+,
3
&'
!&" &4# *!(!!&
4%&
&#&
&&255***'
'54
D2
D
EXPOSED
PAD
e
E2
E
2
TOP VIEW
N
NOTE 1
BOTTOM VIEW
A3
A
A1
6&!
'!
9'&!
7"')
%!
99.
.
7
7:
;
?
&
: 8&
<
&#
%%
,
&&
4!!
-
: >#&
.$
!##>#&
.
: 9&
.$
!##9&
?1,
.3
1,
?
<
1,
?
,
&&>#&
-
-
,
&&9&
-
,
&&&
.$
!##
W
=
!"#$%&" ' ()"&'"!&)
&#*&&&#
4!!*!"&#
- '!
#&
.0
1,2 1!'!
&$& "!
**&
"&&
!
.32 % '!
("!"*&
"&&
(%
%
'&
"
!!
<
* ,1
DS40001413D-page 407
PIC12(L)F1822/16(L)F1823
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001413D-page 408
PIC12(L)F1822/16(L)F1823
16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.20 C
2X
TOP VIEW
0.20 C
SEATING
PLANE
A1
0.10 C
C
A
16X
(A3)
0.08 C
SIDE VIEW
0.10
C A B
D2
0.10
C A B
E2
2
e
2
NOTE 1
K
16X b
0.10
L
e
C A B
BOTTOM VIEW
Microchip Technology Drawing C04-257A Sheet 1 of 2
DS40001413D-page 409
PIC12(L)F1822/16(L)F1823
16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
A
Overall Height
Standoff
A1
A3
Terminal Thickness
Overall Width
E
E2
Exposed Pad Width
D
Overall Length
D2
Exposed Pad Length
b
Terminal Width
Terminal Length
L
K
Terminal-to-Exposed-Pad
MIN
0.45
0.00
2.50
2.50
0.25
0.30
0.20
MILLIMETERS
NOM
16
0.65 BSC
0.50
0.02
0.127 REF
4.00 BSC
2.60
4.00 BSC
2.60
0.30
0.40
-
MAX
0.55
0.05
2.70
2.70
0.35
0.50
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-257A Sheet 2 of 2
DS40001413D-page 410
PIC12(L)F1822/16(L)F1823
16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body
[UQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
16
1
2
C2 Y2
Y1
X1
E
SILK SCREEN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X16)
X1
Contact Pad Length (X16)
Y1
MIN
MILLIMETERS
NOM
0.65 BSC
MAX
2.70
2.70
4.00
4.00
0.35
0.80
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2257A
DS40001413D-page 411
PIC12(L)F1822/16(L)F1823
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A (03/2010)
Original release.
Revision B (10/2010)
Added bits 4 and 5 to FVRCON; Revised Register 6-1;
Added Note 1 to Register 8-1; Revised Section 12.0;
Added Temperature Indicator Module section, renumbering sections; Revised Section 16.1.2; Added Note 4
to Register 16-1; Revised Equation 17-1; Revised bit 0
in Register 23-1; Added Section 24.1.6, Table 24-3,
Section 24.2.6, Section 24.3.9, Section 24.4.8;
Revised Section 24.4.3; Added Note 5 to Register
25-2; Revised Section 26.1.1.1; Revised MOVIW and
MOVWI;
Revised
Section
30.0
Electrical
Specifications.
Revision C (05/2012)
Updated the Family Types table; Updated Figures 1, 2
and 3; Updated Table 3-3; Added section 5.5.3
Fail-Safe Condition Clearing; Replaced Figure 13-1;
Replaced Equation 16-1; Updated Figure 17-1;
Updated the Electrical Specifications section; Added
charts to the DC and AC Characteristics Graphs
section; Updated the Product Identification System
section; Updated the Packaging Information section;
Other minor corrections.
APPENDIX B:
MIGRATING FROM
OTHER PIC
DEVICES
B.1
PIC16F648A to PIC16(L)F1823
TABLE B-1:
FEATURE COMPARISON
Feature
PIC16F648A PIC16(L)F1823
Max. Operating
Speed
20 MHz
32 MHz
Max. Program
Memory (Words)
4K
4K
256
384
Max. EEPROM
(Bytes)
256
256
A/D Resolution
10-bit
10-bit
Timers (8/16-bit)
2/1
4/1
Brown-out Reset
Internal Pull-ups
RB<7:0>
RA<5:0>, RA2
Interrupt-on-change
RB<7:4>
RA<5:0>, Edge
Selectable
1/0
0/2
Extended WDT
Revision D (05/2014)
Software Control
Option of WDT/BOR
INTOSC
Frequencies
48 kHz or
4 MHz
31 kHz 32 MHz
Clock Switching
Capacitive Sensing
CCP/ECCP
DS40001413D-page 412
Comparator
AUSART/EUSART
2/0
2/2
Enhanced PIC16
CPU
MSSPx/SSPx
2/0
Reference Clock
Data Signal
Modulator
SR Latch
Voltage Reference
DAC
PIC12(L)F1822/16(L)F1823
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
DS40001413D-page 413
PIC12(L)F1822/PIC16(L)F1823
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
[X]
/XX
XXX
Temperature
Range
Package
Pattern
PIC12F1822, PIC12LF1822
PIC16F1823, PIC16LF1823
Temperature
Range:
I
E
Package:(2)
JQ
MF
ML
P
RF
SL
SN
ST
Pattern:
=
=
=
=
=
=
=
=
b)
(Industrial)
(Extended)
DS40001413D-page 414
a)
c)
Device:
= -40C to +85C
= -40C to +125C
Examples:
Note 1:
2:
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
2010-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-63276-242-9
== ISO/TS 16949 ==
2010-2014 Microchip Technology Inc.
DS40001413D-page 415
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
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Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
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Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
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Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Austin, TX
Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
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Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
DS40001413D-page 416
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Germany - Pforzheim
Tel: 49-7231-424750
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Poland - Warsaw
Tel: 48-22-3325737
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/25/14