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Guest Lecturer:
Andrei Vladimirescu

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Lecture #9

Midterm

on Friday Febr 19 6:30-8pm in 2060

Valley LSB
Open book
Do not forget your important class material nor
calculator
Covers from start of semester to optimization of
complex logic wires not included!

Review

session tomorrow Th 2/18 at 6:30pm

Room to be announced on web-site

No

lab this week

Hw 4 due next week Friday
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Lecture #9

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Last

lecture

Wiring + first glimpse at transitors

(threshold)
Todays

lecture

Transistor models
Reading

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(Ch 3)

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What do digital IC designers

need to know?

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With positive gate bias, electrons pulled toward the gate

With large enough bias, enough electrons will be pulled to "invert"
the surface (pn type)
Voltage at which surface inverts: magic threshold voltage VT
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Threshold
Depletion charge

Fermi

potential

2F is approximately 0.6V for p-type substrates

is the body factor
VT0 is approximately 0.45V for our process
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0< VGS - VT < VDS

Pinch-off
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For

(VGS VT) < VDS, the effective drain voltage

and current saturate:

Of

course, real drain current isnt totally

independent of VDS
For example, approx. for channel-length modulation:

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Cutoff:
VGS -VT< 0
Linear (Resistive):
VGS-VT > VDS

Saturation:
0 < VGS-VT < VDS

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x 10

-4

VGS= 2.5 V

Resistive

Saturation

ID (A)

VGS= 2.0 V
3

Quadratic
Relationship

VDS = VGS - VT

VGS= 1.5 V

VGS= 1.0 V

0.5

1.5

2.5

VDS (V)
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Lecture #9

2.5

x 10

-4

Early
Saturation

VGS= 2.5 V

VGS= 2.0 V

ID (A)

1.5

VGS= 1.0 V

0.5

Linear
Relationship

VGS= 1.5 V

0.5

1.5

2.5

VDS (V)
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Velocity

saturates due to carrier scattering

n ( m /s)

effects
sat = 105
Constant velocity

Constant mobility "

(slope = )

c
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(V/m)
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Lecture #9

ID
Long-channel device
VGS = VDD
Short-channel device

V DSAT
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VGS - V T
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VDS
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-4

x 10

-4

x 10
2.5

5
2
4
ID (A)

ID (A)

linear

1.5

quadratic

1
2
0.5

1
0
0

0.5

1.5

2.5

0
0

VGS(V)

1.5

2.5

VGS(V)

Long Channel"
(L=2.5m)
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quadratic
0.5

Short Channel"
(L=0.25m)
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Approximate velocity:
Continuity requires that:

Integrating to find the current again:

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x 10

-4

Resistive

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0
0

0.5

1.5

Velocity
Saturation

VGS= 1.0 V

0.5

2.5

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VGS= 2.0 V

VGS= 1.5 V

VDS (V)

Long Channel"
(L=2.5m)

VGS= 2.5 V

Resistive

1.5

VDS = VGS - VT

x 10

Saturation
ID (A)

ID (A)

VGS-VT

VDSAT

-4

2.5

VGS= 2.5 V

0.5

1.5

2.5

VDS (V)

W/L=1.5

Short Channel"
(L=0.25m)

Lecture #9

Exact behavior of transistor in velocity sat. somewhat

challenging if want simple/easy to use models

So, many different models developed over the years

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v-sat, alpha, unified, VT*, etc.

Simple model for manual analysis desirable

Assume velocity perfectly linear until sat
Assume VDSAT constant

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velocity perfectly linear until hit sat

n ( m /s)

Assume

sat = 105
Constant velocity

c = sat/

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(V/m)
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VDSAT = cL when (VGS VT) > cL

VDSAT (V)

Assume

Actual VDSAT

cL

cL

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VGS-VT (V)
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define VGT = VGS VT

for VGT 0: ID = 0

for VGT 0:

ID
B

with VDS,eff = min (VGT, VDS, VD,VSAT)

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Lecture #9

Define

VGT = VGS VT, VD,VSAT = cL

2.5

x 10

-4

VDS = VD,VSAT
2

Velocity
Saturation

Linear
ID (A)

1.5

VGT = VD,VSAT

0.5

VDS = VGT
0

0.5

Saturation
1

1.5

2.5

VDS (V)
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x 10

2.5

-4

VDS=VD,VSAT

ID (A)

1.5

0.5

VDS=VGT
0

0.5

1.5

2.5

VDS (V)

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If

Lecture #9

device always operates in velocity sat.:

VT*

model:

Good
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for first cut, simple analysis

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Textbook: page 103

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-4

x 10

All variables negative

VGS = -1.0V
-0.2

I prefer to work with

absolute values makes
life easier.

VGS = -1.5V

ID (A)

-0.4

-0.6

-0.8

-1
-2.5

VGS = -2.0V

VGS = -2.5V

-2

-1.5

-1

-0.5

VDS (V)

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Lecture #9

= CGCS + CGSO

= CGCD + CGDO

D
= Cdiff

= CGCB

= Cdiff

B
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Capacitance

(per area) from gate across

the oxide is WLCox, where Cox=ox/tox

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Distribution

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between terminals is complex

Capacitance is really distributed

Useful models lump it to the terminals

Several operating regions:

Way off, off, transistor linear, transistor saturated
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When the transistor is off, no carriers in channel

to form the other side of the capacitor.
Substrate acts as the other capacitor terminal
Capacitance becomes series combination of gate
oxide and depletion capacitance
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When |VGS| < |VT|, total CGCB much smaller than

WLCox
Usually just approximate with CGCB = 0 in this region.

(If VGS is very negative (for NMOS), depletion

region shrinks and CGCB goes back to ~WLCox)
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Channel is formed and acts as the other terminal

CGCB drops to zero (shielded by channel)

Model by splitting oxide cap equally between

source and drain
Changing either voltage changes the channel charge
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Changing source voltage doesnt change VGC

uniformly
E.g. VGC at pinch off point still VTH

Bottom line: CGCS 2/3WLCox

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Drain voltage no longer affects channel charge

Set by source and VDS_sat

If change in charge is 0, CGCD = 0

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Cgate vs. VGS

(with VDS = 0)

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Cgate vs. operating region

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Off/Lin/Sat CGSO = CGDO = COW

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Fringing fields

n+

n+
Cross section

COV not just from metallurgic overlap get fringing

fields too
Typical value: ~0.2fFW(in m)/edge
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