Proceedings of 2013 2nd International Conference on Advances in Electrical Engineering (ICAEE 2013)

19-21 December, 2013, Dhaka, Bangladesh

Design of Low Power Pulsed Flip-Flop Using Sleep

Transistor Scheme
G. Mareswara Rao, S. Rajendar
Vardhaman College of Engineering, Hyderabad, India
E-mail: maresh.gangula@gmail.com, s.rajendar@vardhaman.org
Abstract - In this paper, a novel low power pulsed flip-flop (P-FF)
design featuring a sleep transistor scheme is proposed. In order
to improve the leakage robustness for sub-90nm low clock load
dynamic flip-flops, a novel sleep transistor scheme is proposed.
The scheme is implemented using CMOS 90nm technology file in
Synopsis HSPICE. As compared to the conventional pulse
triggered flip-flops, the proposed sleep transistor based P-FF
design features best power-delay-product performance. The
average power and leakage power is reduced without degrading
the overall performance.

separate. Implicit type pulse transition detection method is

considered as more power efficient compared to explicit type
pulse transition detection. Furthermore, the leakage power can
be reduced using sleep transistor scheme.
In this paper, we will present a novel low power pulsed
flip-flop design featuring a sleep transistor scheme. Four
additional transistors are used to support this feature. Inspite of
slight increase in the transistor count and area considerations,
this design gives rise to competitive power and PDP
performance against conventional PTFF designs.
This paper is organized as follows. Section II describes
different conventional pulse triggered flip-flops and their
drawbacks. Section III describes the proposed sleep transistor
based pulsed flip-flop designs. Section IV presents the
discussion on simulation results and comparisons of
performance metrics of the proposed designs with the
conventional designs mentioned in the literature. Finally,
conclusions are presented in section V.

Keywords - leakage power, pulse triggered flip-flop, sleep

transistor, power-delay-product

I.

INTRODUCTION

In synchronous digital systems, clock signals control the

execution process. The operation of the sequential circuit is
controlled by the clock system. Flip-flops (FFs) are the
fundamental building blocks of a sequential digital system.
Nowadays, sequential digital systems adopt pipelining
methods for high throughput, which increases the use of
number of FFs. The power consumption is critically important
in modern integrated circuits especially for low voltage, low
power applications. It is also estimated that in many VLSI
circuits, clock systems consume about 50% of the total system
power [1]. In clock system, power is mostly consumed by flipflops. As a result, reducing the power consumed by flip-flops
will have a deep impact on the total power consumption.
Leakage power is dominant among various contributors to the
total power dissipation in high performance digital systems
[2]-[3]. Therefore, there is a continuing need for leakage
reduction techniques.
Some of the leakage reduction
techniques are based on the use of sleep transistors [4]-[5].
Pulse triggered flip-flop (PTFF) is considered as an
alternative for the conventional transmission gate (TG) based
or master-slave based edge triggered flip-flops. Sleep
transistor scheme with pulsed flip-flop is proposed for leakage
power reduction. Since we are discussing edge triggered flipflops in this paper, the narrow trigger pulse is generated either
implicitly or explicitly. The pulse generator (PG) or pulse
transition detector (PTD) is designed first. Generally,
depending on the pulse transition detection method, PTFF
designs can be classified as implicit or explicit [6]. In an
implicit type, the pulse transition detector is a built-in logic of
the FF design. In an explicit type, the PTD and the latch are

978-1-4799-2465-3/13/$31.00 2013 IEEE

II.

LITERATURE REVIEW

A. Conventional Pulse Triggered Flip-Flop Designs

The conventional pulse triggered flip-flops, which are
used as the reference designs for performance comparisons,
are reviewed first. As shown in Fig. 1, J.Tschanz et.al, in [6],
proposed an implicit type pulsed data closed to output
(ip-DCO) PTFF consisting of an implicit pulse transition
detector based on AND logic and a semi-dynamic structured
latch design. Two practical problems arise in this design. First,
during the positive edge of the clock, nMOS transistors N2
and N3 are turned on. If data remains high, internal node X
will be discharged on every positive edge of the clock. This
leads to a large switching power. The other problem is that
node X controls two large MOS transistors (P2 and N5). The
large capacitive load at node X causes speed and power
performance degradation.
J.Tschanz et.al in [6], proposed an explicit type pulsed
data closed to output (ep-DCO) PTFF which is considered as
one of the fastest flip-flops in its semi-dynamic structure. But
it consumes significant amount of power due to its charging
and discharging of internal node X for every clock cycle. This
produces glitches in the output which leads to increase in

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different modes, active mode and sleep mode (standby mode).

The sleep transistors are turned on during active mode and
turned off during sleep mode [4]-[5].
During active mode, Sleep=0 and Sleepbar=1 are asserted,
and thus all sleep transistors are turned on. This can
potentially reduce circuit delay, as the sleep path achieves
faster switching time. Thus the current flow is immediately
avialble to the low-Vth transistors connected to the output.
During sleep mode (standby mode), Sleep=1 and
Sleepbar=0 are asserted, and so both of the sleep transistors
are turned off. Now, leakage power is suppresed by high-Vth
transistors which are applied to the sleep transistors. The sleep
transistor scheme achieves ultra low leakage power dissipation
during sleep mode.

switching power consumption and system malfunctioning due

to noise problems.
S.H.Rasouli et.al, in [7], proposed an improved PTFF
design, named modified hybrid latch flip-flop (MHLFF), by
employing a static-structured latch. This design eliminates the
discharging problem at internal node X. However, it
encounters a longer D-to-Q delay during 0 to 1 transition
because internal node X is not pre-discharged. To enhance the
discharging capability, larger NMOS transistors are required.
Another disadvantage of this design is that node X becomes
floating when output Q and input data D both equal to 1.

III.

PROPOSED SLEEP TRANSISTOR BASED P-FFS

In this section, we introduce the sleep transistor based

leakage feedback and leakage feed-forward schemes for
leakage power reduction in the pulsed flip-flops.
A. Leakage Feedback Scheme (LFB-PFF)
The circuit diagram of the proposed leakage feedback
scheme with pulsed flip-flop (LFB-PFF) is shown in Fig. 3. In
this flip-flop we make use of implicit type pulse transition
detector (PTD) with any conventional pulse triggered flip-flop
with sleep transistors and sleep helper transistors in pull-up
and pull-down networks. For performance comparison, the
P-FF used is pulse triggered flip-flop with pulse control
scheme [8].

Fig. 1 Conventional PTFF ip-DCO [6]

Yin-Tsung Hwang et.al, in [8], proposed a pulse triggered

flip-flop with conditional pulse enhancement scheme
(CPE-PTFF) shown in Fig. 2, which adopts two measures to
overcome the problems associated with PTFF designs
discussed so far. The first one is reducing the number of
NMOS transistors stacked in the discharging path. The second
one is supporting a mechanism to conditionally enhance the
pull down strength when input data D is 1. The average
power consumption is considerably small, further leakage
power needs to be reduced by employing leakage reduction
techniques.

Fig. 3. P-FF Design Using Sleep Transistor Based

Leakage Feedback Scheme (LFB-PFF)

The proposed leakage feedback scheme consists of two

PMOS transistors MP1 and MP2 in pull-up network and two
NMOS transistors MN1 and MN2 in the pull-down network.
The sleep control signal is given to the input of MP1 and its
complement is given to the input of MN1. The complemented
output of the flip-flop is fed back to the inputs of MP2 and
MN2. Transistors MP1 and MN1 are sleep transistors and
MP2 and MN2 are helper sleep transistors. During sleep
mode, both the sleep transistors are turned off, and any one

Fig. 2. PTFF with Conditional Pulse Enhancement Scheme

(CPE-PTFF) [8]

B.

Sleep Transistor Scheme

The sleep transistor scheme consists of two sleep
transistors and two helper sleep transistors. It works in two

336

IV.

of the two helper sleep transistors are turned on. This makes
the output Q to be driven to any of the appropriate virtual rail
(virtual Vdd or virtual gnd). This scheme is referred to as
leakage feedback scheme since it reduced the leakage power
by operating the flip-flop in sleep mode by retaining the output
to the previous state. When operated in active mode, sleep
transistors are turned on and it works normally.
The operation in sleep mode and active mode is as per the
truth table specified in Table I. In the truth table, some
shorthand notations are used for easy understanding. The
notations are - represents no change in the state value,
? represents any level change (0 or 1), (01) represents
rising edge or positive edge trigger of the signal, and
(10) represents falling edge or negative edge of the signal.

SIMULATION RESULTS

The proposed sleep transistor scheme based pulsed

flip-flop is compared with the conventional pulse triggered
flip-flops to obtain their performance metrics. These designs
include the four conventional PTFF designs ep-DCO,
ip-DCO [6], MHLFF [7], and CPE-PTFF [8]. The target
technology is 90nm CMOS process implemented in HSPICE.
The operating conditions used in simulation is 500MHz/1.0V.
Fig. 5 shows the simulation setup model. Considering the
loading effect of the flip-flop to the previous stage and the
clock tree, the power consumption of the clock and data
buffers are also included. The output of the flip-flop is loaded
with a 20 fF capacitor. An extra capacitance of 3 fF is also
placed after the clock buffer.

B. Leakage Feedforward Scheme (LFF-PFF)

The circuit diagram of leakage feed-forward scheme with
pulsed flip-flop (LFF-PFF) is shown in Fig. 4. In this scheme,
the input to MP2 and MN2 is given from the input signal D.
The same truth table shown in Table I holds good for this
scheme as well.

Fig. 5. Simulation Setup Model

To illustrate the performance of the present work,

Fig. 6 and 7, shows the simulation waveforms of the proposed
P-FF against CPE-PTFF. Table II summarizes some important
performance metrics of the PTFF designs. These include
transistor count, clocked transistor count, minimum D-to-Q
delay, average power consumption and power delay product
(PDP). The power saving of the proposed design against
ep-DCO, ip-DCO, MHLFF and CPE-PTFF are 26.54%,
7.18%, 42.88% and 11.92% respectively. The MHLFF
consumes more power while the proposed design conusmes
less power. The setup time and hold time are computed for the
proposed P-FFs as -50.2ns and 1.5ns respectively with respect
to the clock signal.
To get a more realistic performance, the overall power
consumption for different input patterns is simulated. Consider
five different data sequences to represent various input
switching activities. The sequence of 010101 represents
100% switching activity, 00110011 represents
50% switching activity, and 00010001 represent
25% switching activity. Two other sequences, 11111 and
00000 are used to represent the switching activity of 0%
for all-ones and all zeros respectively. Table III summarizes
the different data swiching activity comparisons of various
PTFFs and Fig. 9 represents its graphical representation. We
compared the minimum D-to-Q delay, average power
consumption and power-delay-product for 50% switching
activity with conventional pulse triggered flip-flop designs as
shown in the Fig. 8. Table IV shows the leakage power
calculations of various PTFF designs in standby mode. The
leakage power of the proposed P-FF design is reduced by
25.22% as compared to the CPE-PTFF design.

Fig. 4. P-FF Design Using Sleep Transistor Based

Leakage Feed forward Scheme (LFF-PFF)

TABLE I
TRUTH TABLE OF PROPOSED P-FF DESIGNS
CLK
?
?
(01)
(10)
?

D
?
(01)/(10)
?
?
?

Sleep
1
1
1
1
0

Q
-

Mode
Sleep
Sleep
Sleep
Sleep
Active

?
(01)
(01)
(10)

(01)/(10)
0
1
?

0
0
0
0

0
1
-

Active
Active
Active
Active

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Fig. 6. Simulation Waveform for the CPE-PTFF [8]

Fig. 7. Simulation Waveform for the Proposed Design (LFB-PFF)

TABLE II
PERFORMANCE METRICS COMPARISON OF VARIOUS PTFF DESIGNS
Type of PTFF
# Transistors
# Clocked Transistors
Min. Data to Q Delay (ns)
Average Power (W)
Power Delay Product (PDP) (fJ)

ep-DCO
[6]
28
15
1.97
28.78
56.69

ip-DCO
[6]
23
10
1.68
22.13
37.17

MHLFF
[7]
19
7
1.83
35.96
65.80

CPE-PTFF
[8]
19
4
1.41
23.32
32.88

Proposed-1
(LFB-PFF)
23
4
1.39
20.54
28.55

Proposed-2
(LFF-PFF)
23
4
1.40
21.01
29.41

Table III
DATA SWITCHING ACTIVITY COMPARISON OF VARIOUS PTFF DESIGNS
Type of PTFF
Average Power (100% Activity, W)
Average Power (50% Activity, W)
Average Power (25% Activity, W)
Average Power (0% all-one, W)
Average Power (0% all-zero, W)

ep-DCO
[6]
32.23
28.78
16.00
34.26
15.47

ip-DCO
[6]
25.52
22.13
11.29
31.72
10.26

338

MHLFF
[7]
36.43
35.96
23.07
14.35
14.42

CPE-PTFF
[8]
25.67
23.32
12.30
8.41
8.42

Proposed-1
(LFB-PFF)
22.23
20.54
13.06
11.59
8.87

Proposed-2
(LFF-PFF)
22.39
21.01
12.98
14.57
8.41

Table IV
LEAKAGE POWER COMPARISON OF VARIOUS PTFF DESIGNS IN STANDBY MODE (nW)
ep-DCO
[6]
0.591
0.654
0.672
0.752

Type of PTFF
(CLK,D) = (0,0)
(CLK,D) = (0,1)
(CLK,D) = (1,0)
(CLK,D) = (1,1)

ip-DCO
[6]
0.313
0.465
0.501
0.481

70

D to Q Delay (ns)

60

Average Power (uW)

50

Power Delay Product

(PDP) (fJ)

40

MHLFF
[7]
0.318
0.302
0.429
0.418

CPE-PTFF
[8]
0.511
0.524
0.537
0.517

Proposed-1
(LFB-PFF)
0.340
0.421
0.366
0.435

Proposed-2
(LFF-PFF)
0.498
0.527
0.524
0.501

designs in its performance metrics such as average power

consumption for 50% data activity, minimum D-to-Q delay
and power delay product. The average power consumption of
proposed LFB-PFF design is reduced by 7.18% as compared
to ip-DCO design and 42.88% as compared to MHLFF design.
Also, the leakage power is reduced by 25.22% as compared to
the CPE-PTFF design. The benefit of the proposed design is
the reduction in leakage power due to shrunken transistor sizes
and variation in the threshold voltages of the sleep transistors.

30
20
10

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Fig. 9. Comparison of Data Switching Activities

V.

CONCLUSION

In this paper, we proposed a novel leakage power

reduction technique for pulse triggered flip-flops. Simulation
results indicate that the proposed design excels conventional

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