S E M I C O N D U C T O R
January 1994
Features
Description
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
PACKAGE
ICL7106CPL
0oC to +70oC
ICL7106RCPL
0oC to +70oC
ICL7106CM44
0oC to +70oC
ICL7107CPL
0 C to +70 C
ICL7107RCPL
0oC to +70oC
ICL7107CM44
0 C to +70 C
Pinouts
(1s)
35 REF LO
G1
34 CREF+
D2
8
9
33 CREF32 COMMON
C2
10
31 IN HI
B2
11
30 IN LO
A2
12
29 A-Z
F2
13
28 BUFF
44 43 42 41 40 39 38 37 36 35 34
33
2
32
NC
TEST
31
C3
OSC 3
30
A3
NC
29
G3
OSC 2
28
BP/GND
OSC 1
27
POL
V+
26
AB4
NC
NC
G2
E2
14
27 INT
D3
15
26 V-
D1
25
E3
B3
16
25 G2 (10s)
C1
10
24
F3
F3
17
24 C3
B1
11
23
12 13 14 15 16 17 18 19 20 21 22
B3
E3
18
23 A3
(1000) AB4
19
22 G3
POL
20
21 BP/GND
(100s)
(MINUS)
(100s)
A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright
V-
36 REF HI
F1
INT
BUFF
37 TEST
A1
A-Z
IN LO
38 OSC 3
B1
IN HI
C1
COMMON
39 OSC 2
CREF+
40 OSC 1
CREF-
REF LO
V+
D1
E1
(10s)
ICL7106, ICL7107
(MQFP)
TOP VIEW
REF HI
ICL7106, ICL7107
(PDIP)
TOP VIEW
2-33
File Number
3082
Thermal Information
Supply Voltage
ICL7106, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
ICL7107, V+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
ICL7107, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V
Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to VReference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to VClock Input
ICL7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+
ICL7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V+
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TEST CONDITIONS
MIN
TYP
MAX
UNIT
-000.0
000.0
+000.0
Digital
Reading
999
999/
1000
1000
Digital
Reading
SYSTEM PERFORMANCE
Zero Input Reading
Ratiometric Reading
Rollover Error
0.2
Counts
Linearity
0.2
Counts
50
V/V
Noise
15
VlN = 0 (Note 5)
10
pA
0.2
V/oC
ppm/oC
End Power Supply Character V+ Supply Cur- VIN = 0 (Does Not Include LED Current for ICL7107)
rent
0.8
1.8
mA
0.6
1.8
mA
2.4
2.8
3.2
80
ppm/oC
2-34
ICL7106, ICL7107
Electrical Specifications (Note 3) (Continued)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
Pin 19 Only
10
16
mA
Pin 20 Only
mA
ICL7107 ONLY
Segment Sinking Current
NOTES:
1. Input voltages may exceed the supply voltages provided the input current is limited to 100A.
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. Unless otherwise noted, specifications apply to both the ICL7106 and ICL7107 at TA = +25oC, fCLOCK = 48kHz. ICL7106 is tested in the
circuit of Figure 1. ICL7107 is tested in the circuit of Figure 2.
4. Back plane drive is in phase with segment drive for off segment, 180o out of phase for on segment. Frequency is 20 times conversion
rate. Average DC component is less than 50mV.
5. Not tested, guaranteed by design.
9V
IN
R5
A3 23
G3 22
BP 21
19 AB4
20 POL
C3 24
18 E3
17 F3
V- 26
G2 25
DISPLAY
16 B3
INT 27
14 E2
A-Z 29
C3
BUFF 28
IN HI 31
IN LO 30
COM 32
C2 R2
15 D3
C5
CREF- 33
CREF+ 34
REF LO 35
TEST 37
R4
REF HI 36
OSC 3 38
C4
OSC 2 39
OSC 1 40
R3
C1
13 F2
R1
12 A2
11 B2
D2
9
10 C2
E1
8
F1
A1
G1
B1
C1
V+
D1
ICL7106
C1 = 0.1F
C2 = 0.47F
C3 = 0.22F
C4 = 100pF
C5 = 0.02F
R1 = 24k
R2 = 47k
R3 = 100k
R4 = 1k
R5 = 1M
DISPLAY
FIGURE 1. ICL7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULLSCALE
+5V
-5V
IN
R5
C3
INT 27
V- 26
G2 25
C3 24
A3 23
G3 22
GND 21
14 E2
15 D3
16 B3
17 F3
18 E3
19 AB4
20 POL
DISPLAY
BUFF 28
A-Z 29
C2 R2
IN LO 30
COM 32
IN HI 31
C5
CREF- 33
CREF+ 34
REF LO 35
REF HI 36
TEST 37
OSC 3 38
C4
OSC 2 39
OSC 1 40
R3
C1
R4
13 F2
R1
12 A2
11 B2
D2
9
10 C2
E1
8
A1
5
F1
B1
4
G1
C1
3
D1
2
V+
1
ICL7107
C1 = 0.1F
C2 = 0.47F
C3 = 0.22F
C4 = 100pF
C5 = 0.02F
R1 = 24k
R2 = 47k
R3 = 100k
R4 = 1k
R5 = 1M
DISPLAY
FIGURE 2. ICL7107 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULLSCALE
2-35
ICL7106, ICL7107
Design Information Summary Sheet
OSCILLATOR FREQUENCY
fOSC = 0.45/RC
COSC > 50pF; ROSC > 50K
fOSC Typ. = 48KHz
DISPLAY COUNT
OSCILLATOR PERIOD
tOSC = RC/0.45
CONVERSION CYCLE
tCYC = tCL0CK x 4000
tCYC = tOSC x 16,000
when fOSC = 48KHz; tCYC = 333ms
COUNT = 1000
V
V
IN
REF
INTEGRATION PERIOD
tINT = 1000 x (4/fOSC)
AUTO-ZERO CAPACITOR
0.01F < CAZ < 1.0F
REFERENCE CAPACITOR
0.1F < CREF < 1.0F
VCOM
Biased between Vi and V-.
INTEGRATE RESISTOR
V
INFS
R
=
INT
I
INT
VCOM V+ - 2.8V
Regulation lost when V+ to V- < 6.8V.
If VCOM is externally pulled down to (V + to V -)/2,
the VCOM circuit will turn off.
INTEGRATE CAPACITOR
(t
) (I
)
INT
INT
C
=
INT
V
INT
SIGNAL INTEGRATE
PHASE FIXED
1000 COUNTS
DE-INTEGRATE PHASE
0 - 1999 COUNTS
2-36
ICL7106, ICL7107
Detailed Description
De-Integrate Phase
Analog Section
STRAY
V
IN .
V REF
DISPLAYCOUNT = 1000
Differential Input
The input can accept differential voltages anywhere within
the common mode range of the input amplifier, or specifically
from 0.5V below the positive supply to 1.0V above the
negative supply. In this range, the system has a CMRR of
86dB typical. However, care must be exercised to assure the
integrator output does not saturate. A worst case condition
would be a large positive common mode voltage with a near
full-scale negative differential input voltage. The negative
input signal drives the integrator positive when most of its
swing has been used up by the positive common mode
voltage. For these critical applications the integrator output
swing can be reduced to less than the recommended 2V fullscale swing with little loss of accuracy. The integrator output
can swing to within 0.3V of either supply without loss of
linearity.
STRAY
CREF
RINT
+
REF HI
34
36
CREF
V+
REF LO
35
A-Z
CREF 33
A-Z
CAZ
BUFFER V+
1
28
CINT
A-Z
INT
29
27
INTEGRATOR
10A
2.8V
31
IN HI
INT
DE-
DE+
6.2V
INPUT
HIGH
A-Z
A-Z
DE+
32
COMPARATOR
DE-
COMMON
INT
30
INPUT
LOW
IN LO
V-
2-37
TO
DIGITAL
SECTION
ICL7106, ICL7107
Differential Reference
The reference voltage can be generated anywhere within the
power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray capacity
on its nodes. If there is a large common mode voltage, the
reference capacitor can gain charge (increase voltage) when
called up to de-integrate a positive signal but lose charge
(decrease voltage) when called up to de-integrate a negative
input signal. This difference in reference for positive or
negative input voltage will give a roll-over error. However, by
selecting the reference capacitor such that it is large enough
in comparison to the stray capacitance, this error can be
held to less than 0.5 count worst case. (See Component
Value Selection.)
V
REF HI
Analog COMMON
6.8V
ZENER
REF LO
IZ
ICL7106
ICL7107
V-
FIGURE 4A.
V+
6.8k
20k
ICL7106
ICL7107
ICL8069
1.2V
REFERENCE
REF HI
REF LO
COMMON
FIGURE 4B.
FIGURE 4. USING AN EXTERNAL REFERENCE
TEST
The TEST pin serves two functions. On the ICL7106 it is
coupled to the internally generated digital supply through a
500 resistor. Thus it can be used as the negative supply for
externally generated segment drivers such as decimal points
or any other presentation the user may want to include on
the LCD display. Figures 5 and 6 show such an application.
No more than a 1mA load should be applied.
2-38
V+
1M
TO LCD
DECIMAL
POINT
ICL7106
BP
TEST
21
37
TO LCD
BACKPLANE
ICL7106, ICL7107
Digital Section
Figures 7 and 8 show the digital section for the ICL7106 and
ICL7107, respectively. In the ICL7106, an internal digital
ground is generated from a 6V Zener diode and a large Pchannel source follower. This supply is made stiff to absorb
the relative large capacitive currents when the back plane
(BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/second this is a
60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and
are in phase with BP when OFF, but out of phase when ON.
In all cases negligible DC voltage exists across the segments.
V+
V+
BP
ICL7106
TO LCD
DECIMAL
POINTS
DECIMAL
POINT
SELECT
TEST
CD4030
GND
a
a
g
b
c
d
b
g
c
d
c
d
BACKPLANE
21
7
SEGMENT
DECODE
7
SEGMENT
DECODE
200
0.5mA
LATCH
SEGMENT
OUTPUT
2.0mA
1000s
COUNTER
100s
COUNTER
10s
COUNTER
1s
COUNTER
1
V+
CLOCK
LOGIC CONTROL
6.2V
500
THREE INVERTERS
ONE INVERTER SHOWN FOR CLARITY
INTERNAL
DIGITAL
GROUND
TEST
VTH = 1V
37
26
40
OSC 1
39
OSC 2
38
OSC 3
2-39
V-
ICL7106, ICL7107
a
a
f
g
a
f
b
g
c
d
c
d
7
SEGMENT
DECODE
TYPICAL SEGMENT OUTPUT
V+
b
g
c
d
7
SEGMENT
DECODE
7
SEGMENT
DECODE
LATCH
0.5mA
TO
SEGMENT
1000s
COUNTER
100s
COUNTER
10s
COUNTER
1s
COUNTER
8.0mA
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
DIGITAL GROUND
V+
1
V+
CLOCK
4
37
LOGIC CONTROL
500
THREE INVERTERS
ONE INVERTER SHOWN FOR CLARITY
27
40
OSC 1
39
OSC 2
TEST
DIGITAL
GROUND
38
OSC 3
System Timing
Figure 9 shows the clocking arrangement used in the
ICL7106 and ICL7107. Two basic clocking arrangements
can be used:
INTERNAL TO PART
CLOCK
CLOCK
2-40
40
39
38
GND ICL7107
TEST ICL7106
INTERNAL TO PART
40
39
38
C
RC OSCILLATOR
ICL7106, ICL7107
Component Value Selection
Reference Voltage
Integrating Resistor
CD4009
V+
OSC 1
IN914
OSC 2
OSC 3
0.047
F
Oscillator Components
ICL7107
For all ranges of frequency a 100k resistor is recommended and the capacitor is selected from the equation
0.45
For48kHzClock(3Readings/second),
f =
RC
+
10
F
-
IN914
GND
V-
V- = 3.3V
C = 100pF
2-41
ICL7106, ICL7107
Typical Applications
Application Notes
the ICL7106
A052 Tips for Using Single Chip 31/2 Digit A/D Converters
Typical Applications
TO PIN 1
TO PIN 1
OSC 1 40
OSC 1 40
100K
OSC 3 38
TEST 37
OSC 3 38
SET VREF
= 100mV
100pF
TEST 37
REF HI 36
REF HI 36
REF LO 35
REF LO 35
CREF 34
CREF 33
1K
22K
CREF 34
0.1F
COMMON 32
CREF 33
1M
A-Z 29
BUFF 28
IN
0.01F
0.47F
IN LO 30
A-Z 29
47K
BUFF 28
9V
A3 23
22K
0.1F
1M
+
IN
0.01F
0.47F
47K
INT 27
0.22F
V - 26
0.22F
-5V
G2 25
G2 25
C3 24
+5V
1K
IN HI 31
INT 27
V - 26
SET VREF
= 100mV
100pF
COMMON 32
IN HI 31
IN LO 30
100K
OSC 2 39
OSC 2 39
C3 24
TO DISPLAY
A3 23
G3 22
G3 22
BP 21
GND 21
TO BACKPLANE
TO DISPLAY
2-42
ICL7106, ICL7107
Typical Applications (Continued)
TO PIN 1
OSC 1 40
TO PIN 1
OSC 1 40
100K
OSC 2 39
OSC 2 39
OSC 3 38
TEST 37
OSC 3 38
SET VREF
= 100mV
100pF
TEST 37
REF HI 36
CREF 33
V+
1K
10K
10K
A-Z 29
BUFF 28
CREF 34
CREF 33
1.2V (ICL8069)
1M
IN LO 30
A3 23
1M
V-
V - 26
C3 24
TO DISPLAY
A3 23
G3 22
GND 21
47K
0.22F
TO DISPLAY
TO PIN 1
TO PIN 1
OSC 1 40
100K
OSC 3 38
OSC 3 38
SET VREF
= 100mV
100pF
TEST 37
25K
CREF 34
24K
0.1F
CREF 33
1M
0.047F
IN LO 30
IN
0.01F
A-Z 29
BUFF 28
470K
A3 23
15K
0.1F
1.2V (ICL8069)
1M
+
IN
0.01F
0.47F
47K
INT 27
0.22F
V - 26
V-
0.22F
G2 25
G2 25
C3 24
10K
IN HI 31
INT 27
V - 26
+5V
1K
COMMON 32
IN HI 31
BUFF 28
REF LO 35
V+
COMMON 32
A-Z 29
SET VREF
= 100mV
100pF
REF HI 36
REF HI 36
REF LO 35
IN LO 30
100k
OSC 2 39
OSC 2 39
CREF 33
-5V
CREF 34
G2 25
G3 22
TEST 37
IN
0.01F
INT 27
0.22F
GND 21
OSC 1 40
0.47F
BUFF 28
G2 25
C3 24
6.8V
0.1F
A-Z 29
47K
INT 27
V - 26
100K
IN HI 31
IN
0.01F
0.47F
1K
COMMON 32
IN HI 31
+5V
REF LO 35
0.1F
COMMON 32
IN LO 30
SET VREF
= 100mV
100pF
REF HI 36
REF LO 35
CREF 34
100K
C3 24
A3 23
TO DISPLAY
TO DISPLAY
G3 22
G3 22
GND 21
BP/GND 21
2-43
ICL7106, ICL7107
Typical Applications (Continued)
TO PIN 1
OSC 1 40
TO PIN 1
V+
OSC 1 40
100K
100K
OSC 2 39
OSC 2 39
OSC 3 38
OSC 3 38
100pF
TEST 37
REF HI 36
REF HI 36
REF LO 35
REF LO 35
CREF 34
CREF 34
0.1F
CREF 33
CREF 33
100k 1M
100k 220k
0.1F
22K
COMMON 32
COMMON 32
IN HI 31
IN HI 31
IN LO 30
IN LO 30
0.47F
47K
BUFF 28
ZERO
ADJUST
0.01F
0.47F
A-Z 29
A-Z 29
SILICON NPN
MPS 3704 OR
SIMILAR
47K
BUFF 28
9V
INT 27
INT 27
0.22F
V - 26
V - 26
0.22F
G2 25
G2 25
C3 24
C3 24
TO DISPLAY
A3 23
A3 23
G3 22
G3 22
GND 21
BP 21
The resistor values within the bridge are determined by the desired
sensitivity.
TO DISPLAY
TO BACKPLANE
V+
TO LOGIC
VCC
1 V+
OSC 1 40
1 V+
OSC 1 40
2 D1
OSC 2 39
2 D1
OSC 2 39
3 C1
OSC 3 38
3 C1
OSC 3 38
4 B1
TEST 37
4 B1
TEST 37
5 A1
REF HI 36
5 A1
REF HI 36
6 F1
REF LO 35
6 F1
REF LO 35
7 G1
CREF 34
7 G1
8 E1
O /RANGE
TO
CREF 34 LOGIC
GND
CREF 33
9 D2
COMMON 32
10 C2
IN HI 31
11 B2
IN LO 30
12 A2
A-Z 29
13 F2
BUFF 28
14 E2
INT 27
15 D3
V- 26
16 B3
G2 25
17 F3
C3 24
18 E3
A3 23
19 AB4
G3 22
20 POL
BP 21
TO LOGIC
VCC
12K
VO /RANGE
+
+
-
U /RANGE
U /RANGE
CD4023 OR
74C10
SCALE
FACTOR
ADJUST
100pF
TEST 37
CD4023 OR
74C10
8 E1
CREF 33
9 D2
COMMON 32
10 C2
IN HI 31
11 B2
IN LO 30
12 A2
A-Z 29
13 F2
BUFF 28
14 E2
INT 27
15 D3
V- 26
16 B3
G2 25
17 F3
C3 24
18 E3
A3 23
19 AB4
G3 22
20 POL
BP 21
V-
33K
CD4077
2-44
ICL7106, ICL7107
Typical Applications (Continued)
TO PIN 1
OSC 1 40
100k
OSC 2 39
10F
OSC 3 38
TEST 37
100pF
5F
CA3140
REF HI 36
REF LO 35
CREF 34
CREF 33
1N914
1K
22K
470K
0.1F
2.2M
COMMON 32
IN LO 30
10K
1F
IN HI 31
1F
10K
BUFF 28
0.47F
0.22F
47K
10F
INT 27
V - 26
1F
4.3K
A-Z 29
9V
100pF
(FOR OPTIMUM BANDWIDTH)
0.22F
G2 25
C3 24
A3 23
TO DISPLAY
G3 22
BP 21
TO BACKPLANE
Test is used as a common-mode reference level to ensure compatibility with most op amps.
FIGURE 21. AC TO DC CONVERTER WITH ICL7106
+5V
LED
SEGMENTS
DM7407
130
ICL7107
130
130
2-45
100k
+
-
AC IN