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Visvesvaraya Technological University

Belgaum, Karnataka-590 014

A Report on

A General Overview on ARM7TDMI


submitted in partial fulfilment of the requirement for the award of the
degree of

Master of Technology in
VLSI Desing and Embedded Sytems
Submitted by
Vasudev S

1RV14LVS33

Under the Guidance of


Prof. Roopa. J

Rashtreeya Vidyalaya College of Engineering


Bengaluru, India

ARM7TDMI
ARR 7 Overview
The ARM7 was introduced the Thumb 16-bit instruction set providing improved code density
compared to previous designs. The most widely used ARM7 designs implement the ARMv4T
architecture, but some implement ARMv3 or ARMv5TEJ. All these designs use a Von
Neumann architecture, thus the few versions comprising a cache do not separate data and
instruction caches.
Some ARM7 cores are obsolete. One historically significant model, the ARM7DI[1] is notable
for having introduced JTAG based on-chip debugging; the preceding ARM6 cores did not
support it. The "D" represented a JTAG TAP for debugging; the "I" denoted an ICEBreaker
debug module supporting hardware breakpoints and watchpoints, and letting the system be
stalled for debugging. Subsequent cores included and enhanced this support.
It is a versatile processor designed for mobile devices and other low power electronics. This
processor architecture is capable of up to 130 MIPS on a typical 0.13 m process. The
ARM7TDMI processor core implements ARM architecture v4T. The processor supports both
32-bit and 16-bit instructions via the ARM and Thumb instruction sets.
ARM licenses the processor to various semiconductor companies, which design full chips
based on the ARM processor architecture.

ARM7TDMI Introduction
The ARM7TDMI processor is a member of the ARM family of general-purpose 32-bit
microprocessors. The ARM family offers high performance for very low-power consumption
and gate count. The ARM architecture is based on Reduced Instruction Set Computer (RISC)
principles. The RISC instruction set, and related decode mechanism are much simpler than
those of Complex Instruction Set Computer (CISC) designs. This simplicity gives:
A high instruction throughput
An excellent real-time interrupt response
A small, cost-effective, processor macrocell

The Instruction Pipeline


The ARM7TDMI-S processor uses a pipeline to increase the speed of the flow of instructions
to the processor. This enables several operations to take place simultaneously, and the
processing, and memory systems to operate continuously. A three-stage pipeline is used, so
instructions are executed in three stages:
Fetch
Decode
Execute.
The three-stage pipeline is shown in Figure

Memory Access
The ARM7TDMI processor has Von Neumann architecture, with a single 32-bit data bus
carrying both instructions and data. Only load, store, and swap instructions can access data
from memory. Data can be 8-bit bytes, 16-bit halfwords, or 32-bit words. Words must be
aligned to 4-byte boundaries. Halfwords must be aligned to 2-byte boundaries.

Memory Interface
The memory interface of the ARM7TDMI processor enables performance potential to be
realized, while minimizing the use of memory. Speed-critical control signals are pipelined to
allow system control functions to be implemented in standard low-power logic. These control
signals facilitate the exploitation of the fast-burst access modes supported by many on-chip
and off-chip memory technologies.

The ARM7TDMI processor has four basic types of memory cycle:


Internal cycle
Non sequential cycle
Sequential cycle
Coprocessor registers transfer cycle.
ARM7TDMI Architecture
The ARM7TDMI processor has two instruction sets:
The 32-bit ARM instruction set
The 16-bit Thumb instruction set.
The ARM7TDMI processor is an implementation of the ARM architecture v4T. For full
details of both the ARM and Thumb instruction sets, see the ARM Architecture Reference
Manual.
Instruction Compression
Microprocessor architectures traditionally had the same width for instructions and data.
Therefore, 32-bit architectures had higher performance manipulating 32-bit data and could
address a large address space much more efficiently than 16-bit architectures. 16-bit
architectures typically had higher code density than 32-bit architectures, and greater than half
the performance.
Thumb implements a 16-bit instruction set on a 32-bit architecture to provide:
Higher performance than a 16-bit architecture
Higher code density than a 32-bit architecture.
The Thumb Instruction Set
The Thumb instruction set is a subset of the most commonly used 32-bit ARM instructions.
Thumb instructions are each 16 bits long, and have a corresponding 32-bit ARM instruction
that has the same effect on the processor model. Thumb instructions operate with the standard
ARM register configuration, allowing excellent interoperability between ARM and Thumb
states.
On execution, 16-bit Thumb instructions are transparently decompressed to full 32-bit ARM
instructions in real time, without performance loss.

Thumb has all the advantages of a 32-bit core:


32-bit address space
32-bit registers
32-bit shifter and Arithmetic Logic Unit (ALU)
32-bit memory transfer.
Thumb therefore offers a long branch range, powerful arithmetic operations, and a large
address space.
Thumb code is typically 65% of the size of the ARM code and provides 160% of the
performance of ARM code when running on a processor connected to a 16-bit memory
system. Thumb, therefore, makes the ARM7TDMI-S processor ideally suited to embedded
applications with restricted memory bandwidth, where code density is important.
The availability of both 16-bit Thumb and 32-bit ARM instruction sets gives designers the
flexibility to emphasize performance, or code size on a subroutine level, according to the
requirements of their applications. For example, critical loops for applications such as fast
interrupts and DSP algorithms can be coded using the full ARM instruction set and linked
with Thumb code.

ARM7TDMI Variants:
ARM&TDMI comes in 2 variants one is ARM7TDMI and the other is ARM7TDMI-S where
S stands for Synthesizable, non-S cores are not physical chips made by ARM. The Atmel
AT91SAM7 series is an example of a hard ARM7TDMI macrocell with customer IP added.
Whereas in S series it can be added peripheral and then go to a Fab to manufacture custom
microcontroller.

ARM7TDMI Core
The ARM7TDMI core is the industrys most widely used 32-bit embedded RISC
microprocessor. Optimized for cost and power sensitive applications, the ARM7TDMI
solution provides the low power consumption, small size and high performance needed in
portable, embedded applications. Key features are:
Hard macrocell
Portable down to 0.13m
Performance up to 120 MIPS (Dhrystone 2.1)
Thumb and ARM instruction sets
Three-stage pipeline
Unified bus architecture
Low power, fully static design
Small die size
Coprocessor interface
EmbeddedICE-RT debug logic
Embedded Trace Macrocell (ETM) interface

Fig: ARM7TDMI Processor Block

ARM7TDMI-S core
ARM7TDMI-S core is the synthesizable version of the ARM7TDMI core with identical
performance levels and feature set. Optimized for flexibility, the ARM7TDMI-S core cuts
time-to-market by reducing development time while allowing for increased design flexibility.

Fig: ARM7TDMI-S Processor Core