IC Manufacturing SMT Process Flow

Semiconductor
Manufacturing Technology
Michael Quirk & Julian Serda
October 2001 by Prentice Hall
Chapter 9
IC Fabrication Process
Overview
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
1/41
Objectives
After studying the material in this chapter, you will be able to:
1. Draw a diagram showing how a typical wafer flows in a
sub-micron CMOS IC fab.
2. Give an overview of the six major process areas and the
sort/test area in the wafer fab.
3. For each of the 14 CMOS manufacturing steps, describe its
primary purpose.
4. Discuss the key process and equipment used in each CMOS
manufacturing step.

2/41
Major Fabrication Steps in MOS Process Flow

UV light
Mask
oxygen
exposed
photoresist
photoresist
Silicon dioxide
oxide
Silicon substrate
Exposed
Photoresist
Mask-Wafer
Photoresist
Coating
Alignment and Exposure
rr
wwee
PPoo
RRFF
r
we
Po
RF
r
we
Po
RF
Ionized CF4 gas

photoresist
oxide
Dopant gas
Ionized oxygen gas

oxide
oxygen
gate oxide
Oxide
Etch
Photoresist
Develop
Photoresist
Strip
Oxidation
(Gate oxide)
Ionized CCl4 gas
Silane gas
polysilicon
Polysilicon
Deposition
po
ly
ga
te
Oxidation
(Field oxide)
oxide
Polysilicon
Mask and Etch
Scanning
ion beam
re
sis
t
silicon nitride
G
ox
S
Ion
Implantation
Contact
holes
top nitride
S
Active
Regions
G D
Nitride
Deposition
S G D
Contact
Etch
Used with permission from Advanced Micro Devices

Figure 9.1
Metal
contacts
G D
drain
S
Metal
Deposition and
Etch
3/41
CMOS Process Flow

Overview of Areas in a Wafer Fab
Diffusion
Photolithography
Etch
Ion Implant
Thin Films
Polish
CMOS Manufacturing Steps

Parametric Testing
6~8 weeks involve 350-step

4/41
Model of Typical Wafer Flow

in a Sub-Micron CMOS IC Fab
Wafer Fabrication (front-end)
Wafer Start
Unpatterned
Wafer
Completed Wafer
Diffusion
Test/Sort
Thin Films
Polish
Photo
Etch
Implant
6 major production areas

Figure 9.2
5/41
Diffusion: Simplified Schematic of HighTemperature Furnace

Thermocouple
measurements
Temperature
controller
Gas flow
controller
Process gas
Quartz tube
Heater 1
Temperaturesetting voltages
Heater 2
Three-zone
Heating
Elements
Heater 3
Pressure
controller
Exhaust
Can do : oxidation, diffusion, deposition, anneals, and alloy

Figure 9.3
6/41
Photolithography Bay in a Sub-micron

Wafer Fab
Yellow fluorescent: do not affect photoresist

Photo 9.1
7/41
Simplified Schematic of a
Photolithography Processing Module
Load Station
Wafer
Cassettes
Vapor
Prime
Resist
Coat
Develop- Edge-Bead
Rinse
Removal Transfer Station
Wafer Stepper
(Alignment/Exposure System)
Wafer Transfer System
Soft
Bake
Cool
Plate
Cool
Plate
Hard
Bake
Note: wafers flow from photolithography into only two other areas: etch and ion implant

Figure 9.4
8/41
Simplified Schematic of Dry Plasma Etcher

Etchant gas entering
gas inlet
Gas distribution baffle
High-frequency energy
Anode electrode
RF coax cable
Photon
Electromagnetic field
e-
e-
Free electron
Glow discharge
(plasma)
Vacuum gauge
e-
Ion sheath
Wafer
Cathode electrode
+
Chamber wall
Positive ion
Radical
chemical
Vacuum line

Figure 9.5
Flow of byproducts and

process gases
Exhaust to
vacuum pump
9/41
Simplified Schematic of Ion Implanter

Gas cabinet
Ion source
Filament
Mass resolving slit
Plasma
Extraction assembly
Analyzing magnet
Acceleration column
Beamline tube
Ion beam
Lighter ions
Process chamber
Heavy
ions
Graphite

Figure 9.6
Scanning
disk
10/41
Thin Film Metallization Bay
Photo courtesy of Advanced Micro Devices

Photo 9.2
11/41
Simplified Schematics of CVD Processing System

Gas inlet
Capacitivecoupled RF input
Process chamber
Chemical vapor deposition
Wafer
Susceptor
Exhaust
Heat lamps
CVD cluster tool
Figure 9.7
12/41
Polish Bay in a Sub-micron Wafer Fab

Photo 9.3
13/41
CMOS Manufacturing Steps

1. Twin-well Implants
14
Passivation layer
2. Shallow Trench Isolation
Bonding pad metal
ILD-6
3. Gate Structure
4.
ILD-5
Lightly Doped Drain Implants
M-4
13
5. Sidewall Spacer
ILD-4
M-3
6. Source/Drain Implants
ILD-3
12
7. Contact Formation
M-2
11
8. Local Interconnect
M-1
9. Interlayer Dielectric to Via-1
Via
10. First Metal Layer

11. Second ILD to Via-2
12. Second Metal Layer to Via-3
13. Metal-3 to Pad Etch
14. Parametric Testing
ILD-2
ILD-1
9
Poly gate
LI metal
n+
2
7
10
3
p+
LI oxide
p+
STI
4
n-well
n+
n+
p+
6
p-well
1
p-
Epitaxial layer
p+ Silicon substrate
14/41
n-well Formation
Epitaxial layer : improved quality and fewer defect
In step 2, initial oxide: (1) protects epi layer from
contamination, (2) prevents excessive damage to
ion/implantation, (3) control the depth of the dopant during
implantation
In step 5, anneal: (1) drive-in, (2) repair damage, (3)
activation
Phosphorus implant
Thin
Films
2
1
Diffusion
5
Polish
Photoresist
Photo
Etch
Oxide
n-well
~5 um
1
Implant
p- Epitaxial layer

Figure 9.8
(Dia = 200 mm, ~2 mm thick)
15/41
p-well Formation
Boron implant
Thin
Films
Polish
Photoresist
Diffusion
3
Photo
Etch
Oxide
n-well
p-well
p- Epitaxial layer
Implant

Figure 9.9
16/41
STI Trench Etch

STI: shallow trench isolation
1.
2.
3.
4.
Barrier oxide: a new oxide

Nitride: (1) protect active region, (2) stop layer during CMP
3rd mask
STI etching
Selective etching opens isolation regions in the epi layer.

+Ions
Thin
Films
1
Diffusion
Photo
Polish
4
Etch
Photoresist
Nitride
Oxide
n-well
p-well
STI trench
p- Epitaxial layer
Implant

Figure 9.10
17/41
STI Oxide Fill

1.
2.
Liner oxide to improve the interface between the silicon and trench CVD oxide
CVD oxide deposition
Trench fill by chemical vapor deposition

Oxide
Thin
Films
Polish
Trench CVD oxide

Nitride
Diffusion
Photo
Etch
p-well
n-well
Liner oxide
p- Epitaxial layer
Implant

Figure 9.11
18/41
STI Formation
1.
2.
Trench oxide polish (CMP): nitride as the CMP stop layer since nitride is harder than oxide
Nitride strip: hot phosphoric acid
Planarization by chemical-mechanical polishing

1
1
Thin
Films
Polish
Photo
Etch
STI oxide after polish

2
Nitride strip
Diffusion
p-well
n-well
Liner oxide
p- Epitaxial layer
Implant

Figure 9.12
19/41
Poly Gate Structure Process

1.
2.
3.
4.
Oxide thickness 1.5 ~ 5.0 nm is thermal grown

Poly-Si ~ 300 nm is doped and deposited in LPCVD using SiH4
Need Antireflective coating (ARC), very critical
The most critical etching step in dry etching
Thin
Films
1
Diffusion
Photo
Polish
4
Polysilicon
deposition
1
Photoresist
ARC
Poly gate etch
Gate oxide
Etch
p-well
n-well
p- Epitaxial layer
Implant

Figure 9.13
20/41
n LDD Implant
1.
2.
3.
LDD: lightly doped drain to reduce S/D leakage

Large mass implant (BF2, instead of B, As instead of P) and amorphous
surface helps maintain a shallow junction
5th mask
Thin
Films
Polish
Photo
Etch
Arsenic n- LDD implant
Photoresist mask
Diffusion
n-
n-well
n-
p-well
n-
p- Epitaxial layer
Implant

Figure 9.14
21/41
p LDD Implant
1.
2.
6th mask
In modern device, high doped drain is used to reduce series
resistance. It called S/D extension
Thin
Films
Polish
Photo
Etch
BF2 p- LDD implant
Photoresist Mask
mask
1Photoresist
Diffusion
n-
p-
p-
n-well
n-
n-
p-well
p-
p- Epitaxial layer
Implant

Figure 9.15
22/41
Side Wall Spacer Formation

Spacer is used to prevent higher S/D implant from penetrating too close to the channel
Thin
Films
Spacer etchback by anisotropic plasma etcher
Polish
1
+Ions
Spacer oxide
Side wall spacer
Diffusion
Photo
Etch
n-
p-
p-
n-well
n-
n-
p-well
p-
p- Epitaxial layer
Implant

Figure 9.16
23/41
n+ Source/Drain Implant
1.
2.
Energy is high than LDD I/I, the junction is deep

7th mask
Thin
Films
Polish
Photo
Etch
Arsenic n+ S/D implant
Photoresist mask
Diffusion
n+
n-well
n+
p-well
n+
p- Epitaxial layer
Implant

Figure 9.17
24/41
p+ Source/Drain Implant
1.
2.
8th mask
Using rapid thermal anneal (RTA) to prevent dopant
spreading and to control diffusion of dopant
Thin
Films
Polish
Photo
Etch
Boron p+ S/D implant
Photoresist Mask
mask
1Photoresist
Diffusion
3
n+
p+ n-well
p+
n+ p-well
n+
p+
p- Epitaxial layer
Implant

Figure 9.18
25/41
Contact Formation
1.
Titanium (Ti) is a good choice for metal contact due to low

resistivity and good adhesion
No mask needed, called self-align
Using Ar to sputtering metal
Anneal to form TiSi2, tisilicide
Chemical etching to remove unreact Ti, leaving TiSi2, called
selective etching
2.
3.
4.
5.
Thin
Films
Polish
Titanium depostion
2
Titanium etch
Tisilicide contact formation (anneal)
Diffusion
Photo
Etch
n+
p+ n-well
p+
n+
p-well
n+
p+
p- Epitaxial layer
Implant

Figure 9.19
26/41
LI Oxide as a Dielectric for Inlaid LI Metal

(Damascene)
Damascene: a name doped of year ago from a practice that began thousands ago by artist in Damascus, Syria
LI metal
LI oxide
LI: local interconnection

Figure 9.20
27/41
LI Oxide Dielectric Formation

1.
2.
3.
4.
Nitride: protect active region

Doped oxide
Oxide polish
9th mask
2 Doped oxide CVD
3
2
1
Thin
Films
1 Nitride CVD
3 Oxide polish
4 LI oxide etch
Polish
LI oxide
4
Diffusion
Photo
Etch
p-well
p-well
p- Epitaxial layer
Implant

Figure 9.21
28/41
LI Metal Formation
Ti/TiN is used: Ti for adhesion and TiN for diffusion barrier
Tungsten (W) is preferred over Aluminum (Al) for LI metal
due to its ability to fill holes without leaving voids
Diffusion
Thin
Films
Polish
Photo
Etch
Ti/TiN
2 deposition
3 Tungsten
deposition
4 LI tungsten polish
LI oxide
1
Ti deposition
p-well
n-well
p- Epitaxial layer
Implant

Figure 9.22
29/41
Via-1 Formation
1.
2.
3.
Interlayer dielectric (ILD): insulator between metal

Via: electrical pathway from one metal layer to adjacent metal layer
10 th mask
1 ILD-1 oxide
deposition
2 Oxide polish
2
1
Thin
Films
ILD-1 oxide etch

3 (Via-1 formation)
ILD-1
Polish
LI oxide
3
Diffusion
Photo
Etch
p-well
n-well
p- Epitaxial layer
Implant

Figure 9.23
30/41
Plug-1 Formation
1.
2.
3.
4.
Ti layer as a glue layer to hold W

TiN layer as the diffusion barrier
Tungsten (W) as the via
CMP W-polish
Ti/TiN
2 deposition
1
Diffusion
Thin
Films
Polish
Photo
Etch
3 Tungsten
deposition
1
Ti dep.
4 Tungsten polish (Plug-1)
ILD-1
LI oxide
p-well
n-well
p- Epitaxial layer
Implant

Figure 9.24
31/41
SEM Micrographs of Polysilicon,

Tungsten LI and Tungsten Plugs
Tungsten LI
Polysilicon
Tungsten
plug
Mag. 17,000 X
Micrograph courtesy of Integrated Circuit Engineering
Photo 9.4
32/41
Metal-1 Interconnect Formation

1. Metal stack: Ti/Al (or Cu)/TiN is used
2. Al(99%) + Cu (1%) is used to improve reliability
3. 11th mask
Ti Deposition
1
1
TiN
3 deposition
Al + Cu (1%)
2 deposition
4 Metal-1 etch
ILD-1
Thin
Films
Polish
LI oxide
4
Diffusion
Photo
Etch
p-well
n-well
p- Epitaxial layer
Implant

Figure 9.25
33/41
SEM Micrographs of First Metal Layer

over First Set of Tungsten Vias
TiN metal cap
Metal 1, Al
Tungsten
plug
Mag. 17,000 X

Photo 9.5
34/41
Via-2 Formation
1.
2.
3.
4.
Gap fill: fill the gap between metal

Oxide deposition
Oxide polish
12 th mask
ILD-2 oxide
deposition
ILD-2 oxide etch

4 (Via-2 formation)
3 Oxide polish
1 ILD-2 gap fill
1 2
Thin
Films
ILD-1
Polish
LI oxide
4
Diffusion
Photo
Etch
p-well
n-well
p- Epitaxial layer
Implant

Figure 9.26
35/41
Plug-2 Formation
1.
2.
Ti/TiN/W
CMP W polish
Ti/TiN
2 deposition
1 Ti deposition
Diffusion
Thin
Films
Polish
Photo
Etch
Tungsten
deposition 3
(Plug-2)
Tungsten
4 polish
ILD-2
ILD-1
LI oxide
p-well
n-well
p- Epitaxial layer
Implant

Figure 9.27
36/41
Metal-2 Interconnect Formation

1.
2.
3.
4.
5.
Metal 2: Ti/Al/TiN
ILD-3 gap filling
ILD-3
ILD-polish
Via-3 etch and via deposition, Ti/TiN/W
ILD-3 oxide
3 polish
Metal-2 deposition
1 to etch
2 Gap fill
4 Via-3/Plug-3 formation
ILD-3
ILD-2
ILD-1
LI oxide
p-well
n-well
p- Epitaxial layer

Figure 9.28
37/41
Full 0.18 m CMOS Cross Section

Passivation layer
Bonding pad metal
ILD-6
ILD-5
1.
2.
Passivation layer of
nitride is used to
protect from moisture,
scratched, and
contamination
ILD-6 : oxide
M-4
ILD-4
M-3
ILD-3
M-2
ILD-2
M-1
Via
ILD-1
Poly gate
LI oxide
LI metal
n+
p+
p+
STI
n-well
n+
n+
p+
p-well
p- Epitaxial layer

Figure 9.29
38/41
SEM Micrograph of Cross-section of AMD

Microprocessor
Mag. 18,250 X
Photo 9.6
39/41
Wafer Electrical Test using a Micromanipulator Prober

(Parametric Testing)
1.
2.
3.
After metal-1 etch,

wafer is tested, and
after passivation test
again
Automatically test on
wafer, sort good die (XY position, previous
marked with an red
ink)
Before package, wafer
is backgrind to a
thinner thickness for
easier slice and heat
dissipation

Photo 9.7
40/41
Chapter 9 Review
Summary
Key Terms
Review Questions
SMT Web Site
References

222
223
223
224
41/41

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Semiconductor

Semiconductor Manufacturing Technology

Major Fabrication Steps in MOS Process Flow

Ionized CF4 gas

Ionized oxygen gas

Ionized CCl4 gas

Used with permission from Advanced Micro Devices

Semiconductor Manufacturing Technology

CMOS Process Flow

CMOS Manufacturing Steps

Semiconductor Manufacturing Technology

Model of Typical Wafer Flow

6 major production areas

Semiconductor Manufacturing Technology

Diffusion: Simplified Schematic of HighTemperature Furnace

Can do : oxidation, diffusion, deposition, anneals, and alloy

Photolithography Bay in a Sub-micron

Yellow fluorescent: do not affect photoresist

Wafer Transfer System

Semiconductor Manufacturing Technology

Simplified Schematic of Dry Plasma Etcher

Gas distribution baffle

Semiconductor Manufacturing Technology

Flow of byproducts and

Simplified Schematic of Ion Implanter

Mass resolving slit

Semiconductor Manufacturing Technology

Thin Film Metallization Bay

Photo courtesy of Advanced Micro Devices

Simplified Schematics of CVD Processing System

Chemical vapor deposition

Polish Bay in a Sub-micron Wafer Fab

Photo courtesy of Advanced Micro Devices

CMOS Manufacturing Steps

2. Shallow Trench Isolation

Bonding pad metal

Lightly Doped Drain Implants

9. Interlayer Dielectric to Via-1

10. First Metal Layer

Semiconductor Manufacturing Technology

(Dia = 200 mm, ~2 mm thick)

Semiconductor Manufacturing Technology

STI Trench Etch

Barrier oxide: a new oxide

Selective etching opens isolation regions in the epi layer.

Semiconductor Manufacturing Technology

STI Oxide Fill

Trench fill by chemical vapor deposition

Trench CVD oxide

Semiconductor Manufacturing Technology

Planarization by chemical-mechanical polishing

STI oxide after polish

Semiconductor Manufacturing Technology

Poly Gate Structure Process

Oxide thickness 1.5 ~ 5.0 nm is thermal grown

Poly gate etch

Semiconductor Manufacturing Technology

LDD: lightly doped drain to reduce S/D leakage

Arsenic n- LDD implant

Semiconductor Manufacturing Technology

BF2 p- LDD implant

Semiconductor Manufacturing Technology

Side Wall Spacer Formation