Ies Digital Electronics Notes

Digital Electronics,
Basics & Combinational

Class Room
Practice Questions
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INDEX
Topics
---
1. Basics
--2. Combinational logic
---
Page No.
-----
1 to 20
21 to 47
From:
Institute of Engineering Studies (IES,Bangalore),

Leading Institute in Bangalore for GATE/IES/PSU operating from
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Branch :--EC/EE/IN/CS/IT
Subject:Digital Electronics
Topic:Basics
Total Questions :151
CLASS ROOM PRACTICE QUESTIONS
Common Data for Q1 and Q2 is given below
The function f(A, B, C, D) =

1)The number of prime implicants and essential prime implicants are
[A] 6, 1
[C]7, 1
. [QDigA047] .. (
. [QDigA048] .. (
[B] 6, 2
[D]7, 2
2)Prime implicant set is

[B]
[D]
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[A]
[C]
3)How many memory Ics of 4k x 2 capacity are required to construct a memory of 22k x 8 capacity ?
[A] 22
[C]24
. [QDigA054] .. (
[B] 20
[D]20
4)Pick up correct statement from the following

P. Any three variable Boolean equation can be implemented with 4 1 mux without using any additional
gates
Q. Floating inputs can be taken by the circuit as logic 1 in the case of TTL family circuits.
R. In an n-variable k-map combining 16 adjacent cells containing 1s as a single group will result a term of
(n-4) literals
[A] P, Q, R
[C]R, S, T
S,
B
S. The Boolean function f(w, x, y, z) =

is independent of only one variable
.
T. Binary weighted resistor type of DAC is advantages over R-2R ladder type of DAC because of good
linearity
5)How many Boolean equations of the form f(x, y, z) =
IE
[A] 256
[C]8
are possible with three variable x, y and z ?

. [QDigA067] .. (
. [QDigA068] .. (
. [QDigA079] .. (
[B] 64
[D]4
6) The Boolean function f(w, x, y, z) =

[A] w
[C]y
. [QDigA064] .. (
[B] Q, R, S
[D]P, R, T
is independent of variables
[B] x
[D]z and x
7)What is the minimized logic expression corresponding to the given k-map ?
[A]
[C]
[B]
[D]
Page.No.1
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
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8)The Karnaugh map of 4 variable Boolean functions A, B C, D is shown in figure X indicates dont care
combinations. The minimal SOP expression for the function is
[A]
[C]
. [QDigA088] .. (
. [QDigA099] .. GATE-ECE/TCE-2001(
[B]
[D]
9)The 2s complement representation of 17 is

[B] 101111
[D]110001
10)The logical expression

[A] Y = AB
[C]
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[A] 101110
[C]111110
is equivalent to
[B]
[D]Y = A + B
11)The minimized form of the logical expression

[A]
[C]
[B]
[D]
12)4- bit 2s complement representation of a decimal number is 1000. the number is

[A] +8
[C]-7
[B] 0
[D]-8
[A] 16
[C]1024
S,
B
13)The number of distinct Boolean expressions of 4 variables is
[B] 256
[D]65536
14)Two 2s complement numbers having sign bits x and y are added and the sign bit of the result is z.
Which Boolean function indicates the occurrence of the overflow?
IE
[A] xyz
[C]
. [QDigA481] .. IES-ECE/TCE-2008(
[B]
[D]xy+yz+zx
15)Statement (I) : Tristate logic is used for bus oriented systems .

Statement (II) : The tristate logic has three output states : 0 , 1 and indeterminant
[A] Both Statement (I) and statement (II) are
individually true and statement (II) is the correct
explanation of statement (I)
[C]Statement (I) is true but statement (II) is false
. [QDigA487] .. IES-EEE-2012(
[B] Both Statement (I) and statement (II) are

individually true but statement (II) is not the
correct explanation of statement (I)
[D]statement (I) is false but statement (II) is true
16)If the functions W, X, Y and Z are as follows

[A]
[C]
[B]
[D]
17)The range of signed decimal numbers that can be represented by 6-bite 1s complement number is
[A] 31 to + 31
[C] 64 to + 63
[B] 63 to + 63
[D] 32 to + 31
Page.No.2
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18)A digital system is required to amplify a binary-encoded audio signal. The user should be able to control
the gain of the amplifier from a minimum to a maximum in 100 increments. The minimum number of bits
required to encode, in straight binary, is
[A] 8
[C]5
[B] 6
[D]7
19)The minimum decimal equivalent of the number 11C.0 is

[A] 183
[C]268
[B] 194
[D]269
20)(FE35)16 XOR (CB 15)16 is equal to

[B] (FF35)16
[A] (3320)16
[C](FF50)16
[D](3520)16
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21)Kannaugh map is used to

[A] minimize the number of flip-flops in a digital
circuit
[B] minimize the number of gates only in a digital

circuit
[C]minimize the number of gates and fan in of a

digital circuit
[D]design gates
22)Fs complement of (2BFD)hexis

[A] E304
[C]D 402
23)The Boolean expression
is equivalent to
[B]
[D]
S,
B
[A]
[C]
[B] D 403
[D]C 403
24)11001, 1001 and 111001 correspond to the 2s complement representation of which one of the following
sets of number?
[A] 25, 9 and 57 respectively
[C]-7, -7 and -7 respectively
[B] -6, - 6 and 6 respectively

[D]-25, -9 and 57 respectively
IE
25)A Boolean function f of two variables x and y is defined as follows:

f(0, 0) = f(0, 1) = f (1, 1) = 1; f(1, 0) = 0
Assuming complements of x and y are not available, a minimum cost solution for realizing f using only 2input NOR gates and 2-input OR gates (each having unit cost) would have a total cost of
[A] 1 Unit
[C]3 Unit
[B] 4 Unit
[D]2 Unit
26)Decimal 43 in Hexadecimal and BCD number system is respectively

[A] B2, 0100 0011
[C]2B, 0011 0100
[B] 2B, 0100 00 11

[D]B2, 0100 0100
Page.No.3
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27)The Boolean expression for the truth table shown is
[A]
[C]
[B]
[D]
IE
S,
B
28)The number of product terms in the minimized sum of product expression obtained through the following
K-map is (where, d denotes dont care states)
[A] 2
[C]4
[B] 3
[D]5
29)A new Binary coded Pentary (BCP) number system is proposed in which every digit of a base- 5 number is
represented by its corresponding 3-bit binary code. For example, the base- 5 number 24 will be
represented by its BCP code 010100. In this numbering system, the BCP code 100010011001
corresponds to the following number in base-5 system
[A] 423
[C]2201
[B] 1324
[D]4231
30)X = 01110 and Y = 11001 are two 5-bit binary numbers represented in twos complement format. The sum
of X and Y represented in twos complement format using 6 bits is
[A] 100111
[C]000111
[B] 001000
[D]101001
Page.No.4

31)The Boolean function Y = AB + CD is to be realized using only 2-input NAND gates. The minimum number
of gates required is
[A] 2
[C]4
[B] 3
[D]5
Can be minimized to
[A]
[C]
[B]
[D]
33)The two numbers represented in signed 2s complement form are P = 11101101 and Q = 11100110. If Q is
subtracted from P, the value obtained in signed 2s complement form is
[A] 100000111
[C]11111001
[A] Y=Z
[C]Z=1
[D]111111001
, then
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34)If X = 1 in the logic equation
[B] 00000111
[B]
[D]Z=0
35)The Boolean theorem
corresponds to
[B]
[D]
[A]
[C]
36)Y= f(A,b) = M (0,1,2,3) represents (M is Maxterm)
[B] NAND gate
[A] NOR gate

[C]OR gate
[D]a situation where output is independent of input
[A] 8
[C]10
S,
B
37)The number of digital 1 present in the binary representation of 3 x 512 + 7 x 64 + 5 x 8 + 3 is

[B] 9
[D]12
38)If the output of a logic gate is 1 when all its inputs are at logic 0 the gate is either
IE
[A] NAND or NOR

[C]an OR or a NAND
[B] and AND or an EX-NOR

[D]an EX-OR-or an EX-NOR
39)For the Karnaugh map shown in the given figure, the minimum Boolean function is
[A] xy + z + yz
[C]xy + z + yz
[B] xz + z +zy
[D]xz + z + yz
40)Which one of the following is equivalent to the Boolean expression

[A]
[C]
[B]
[D]
Page.No.5
41)Given Boolean Theorem

Which one of the following identities is true?
[A]
[C]
[B]
[D]
42)In signed magnitude representation, the binary equivalent of 22.5625 is (the bit before comma represents
the sign)
[A] 0, 10110. 1011
[B] 0, 10110. 1001
[C]1, 10101.1001
[D]1, 10110.1001
43)Which of the following represents E316
[C](2BC)16 (1DE)16
[B] (1BC)16 (DE)16
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[A] (ICE)16 + (A2)16
[D](200)16 (11D)16
44)With 4 Boolean variables how many Boolean expressions can be formed?

[A] 16
[C]1024 (1K)
[B] 256
[D]64 (64 x 1024)
45)How is inversion achieved using EX-OR gate?
[A] Giving input signal to the two input lines of the

gate tied together.
[C]Giving input to one input line and logic one to the
other line
[B] Giving input to one input line and logic zero to the
other line
[D]inversion cannot be achieved using EX-OR gate.
IE
S,
B
46)The minimized expression for the given K map (x: dont care) is
[A]
[C]C+AB
[B] B+AC
[D]ABC
47)Consider the Boolean expression

The simplified form of X is
[A]
[C]CD
[B] BC
[D]BC
48)Which of the following is a self complementing code?

Page.No.6
[A] 8421 code

[C]Pure binary code
[B] Excess 3 code

[D]Gray code
49)A number is expressed in binary twos complement as 10011. Its decimal equivalent value is
[A] 19
[C]-19
[B] 13
[D]-13
50)The output of a logic gate is 1 when all its input 0 then the gate is either
[A] A NAND or an EX-OR gate
[B] A NOR or an EX-NOR gate
[C]An OR or an EX-NOR gate
[D]An AND or an EX-OR gate
51)Match List-I with List-II and select the correct answer using the codes given below the lists:
List-I List-II
1.
B.
2. A = B
C.
3. A =1 or B = 1
D.
4. A = 1 or B = 0
[A] A-3 B-2 C-1 D-4

[C]A- 3 B -2 C -4 D -1

[A]
[C]
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A.
[B] A-2 B-3 C-4 D-1

[D]A-2 B-3 C-1 D-4
Simplifies to
[B]
[D]
[A] zero
[C]4
S,
B
53)The minimum number of NAND gates required to implement the Boolean function
to
is equal
[B] 1
[D]7
IE
54)Match the logic gates in column A with their equivalent s in column B
[A] P-2, Q-4, R-1, S-3

[C]P-2, Q-4, R-3, S-1
[B] P-4, Q-2, R-1, S-3

[D]P-4, Q-2, R-3, S-1
55)How many 1s are present in the binary representation of (4 x 4096) + (9 x 256)+ (7 x16) + 5?
[A] 8
[C]10
[B] 9
[D]11
Page.No.7

56)Assume that only x and y logic inputs are available and the complements
is the minimum number of 2-input NAND gates required to implement
and are not available. What

?
[A] 2
[C]4
[B] 3
[D]5
57)A, B and C are three Boolean variables which one of the following Boolean expressions cannot be
minimized any further?
[A]
[C]
[B]
[D]
58)What is the minimum number of NAND gates required to implement
?
[A] 0
[C]4
[B] 1
[D]7
59)The output of a two level AND-OR gate network is F. what is the output when all the gates are replaced by
NOR gates?
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[A] F
[C]
[B]
[D]
60)If (2,3)base 4 + (1.2)base 4 = (y)base 4 What is the value of y?
[A] 10.1
[C]10.2
[B] 10.01
[D]1.02
61)The number of 1 in 8-bits representation of -127 in 2s complement from is m and that in 1s complement
form is n. what is the value of m:n?
[A] 2: 1
[C]3 : 1
. [QDigA318] .. GATE-EEE-2003(
[B] 1 : 2
[D]1 : 3
[A] 5
[C]12
S,
B
62)Given
(135)base x+ (144)base x = (323)base x
What is the value of base x?
IE
[A]
[C]
[B] 3
[D]6
can be simplified to
[B]
[D]
64)The simplified form of the Boolean expression

[A]
[C]
can be written as
. [QDigA333] .. IES-EEE-2001(
[B]
[D]
65)The Octal equivalent of the HEX number AB. CD is

[A] 253.314
[C]526.314
[B] 253.632
[D]526.632
66)In Boolean Algebra ,

If
, then
[A]
[C]
[B]
[D]
67)The decimal equivalent of hexadecimal number of 2A0F is
Page.No.8
[A] 17670
[C]17067
. [QDigA342] .. IES-EEE-2002(
. [QDigA343] .. IES-EEE-2002(
. [QDigA345] .. IES-EEE-2002(
. [QDigA346] .. IES-EEE-2003(
[B] 17607
[D]10767
68)The binary equivalent of hexadecimal number 4F2D is

[A] 0101 1111 0010 1100
[C]0100 1110 0010 1101
[B] 0100 1111 0010 1100

[D]0100 1111 0010 1101
69)Which logical operation is performed by ALU of 8085 to complement a number ?

[A] AND
[C]OR
[B] NOT
[D]EXCLUSIVE OR
70)The simplified form of a logic function

is
[A] A + B
[C]
[B] AB
[D]
is
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71)The reduced form of the Boolean expression

[A]
[C]AB
. [QDigA347] .. IES-EEE-2003(
. [QDigA356] .. IES-EEE-2003(
[B]
[D]
72)The binary representation 100110 is numerically equivalent to the

1. Decimal representation 46
2. Octal representation 46
3. Hexadecimal representation 26
4. Excess-3 representation 13
Select the correct answer using the codes given below :
[A] 1 and 2
[C]1 and 3
[B] 2 and 3
[D]2 and 4
S,
B
73)Match List-I (Circuit symbols) with List-II (Nomenclature) and select the correct answer using the codes
given below :
List-I List-II
B.
C.
1. NAND
IE
A.
D.
2. NOR
3. Buffer
4. Schmitt trigger
. [QDigA359] .. IES-EEE-2004(
[A] A-4, B-3, C-1, D-2

[C]A-4, B-3, C-2, D-1
74)If x and y are Boolean variables, which one of the following is the equivalent of
?
. [QDigA360] .. IES-EEE-2004(
[A]
[C]0
75)What are the values respectively, of
[B] A-3, B-4, C-2, D-1

[D]A-3, B-4, C-1, D-2
)
[B] x + y
[D]1
in the expression
Page.No.9
. [QDigA363] .. IES-EEE-2004(
[A] 8, 16
[C]6, 16
[B] 16, 8
[D]12, 8
76)Which one of the following statements is correct?

For a 4-input NOR gate, when only two inputs are to be used, the best option for the unused inputs is to
. [QDigA366] .. IES-EEE-2004(
[B] connect them to

[D]connect them to the used inputs
[A] connect them to the ground

[C]keep them open
77)Consider the following multiplication :

Which one of the following gives appropriate values of w, y and z ?
. [QDigA369] .. IES-EEE-2004(
[A] w = 0 , y = 0 , z = 1
[C]w = 1 , y = 1 , z = 1
[B] w = 0 , y = 1 , z = 1
[D]w = 1 , y = 1 , z = 0
[A] 1, 2 and 4
[C]2, 3 and 4
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78)Which of the following notations have two representations of zero?

1. 1s complement with radix of number being 2
Select the correct answer using the codes given below
. [QDigA370] .. IES-EEE-2005(
. [QDigA371] .. IES-EEE-2005(
. [QDigA372] .. IES-EEE-2005(
. [QDigA377] .. IES-EEE-2007(
[B] 1 and 3
[D]1, 2 and 3
79)Which of the following statements is not correct ?
[B]
[D]
[A]
[C]

[A]
[C]Y Z + X Z + X Y
[B]
[D]
S,
B
81)The function
is logically equivalent to
; can be reduced to which one of the following ?
[A] F = A
[C]F = ABC
[B] F = AB
[D]F = B
IE
82)If the input to the digital circuit of the below figure consisting of a cascade of 20 XOR gates is X , then
what is the output Y ?
. [QDigA380] .. IES-EEE-2007(
[A] 0
[C]X'
[B] 1
[D]X
Page.No.10
83)What is the minimized logic expression corresponding to the given Karnaugh Map?
[A] xz
[C]
[B]
[D]
84)The Boolean function
is equal to which one of the following expressions?

[A] (x+y)(y+z)
[C]
[B]
[D]
[A]
[C]
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85)
Which one of the following is the dual form of the Boolean identity given above?
. [QDigA407] .. IES-EEE-2008(
[B]
[D]
86)A Gray code is a/an:
[A] Binary weight code

[C]Code which exhibits a single bit change between
those successive codes
[B] Arithmetic code
[D]Alphanumeric code
[A]
[C]XY
S,
B
87)What is the simplified form of the Boolean expression

?
[B]
[D]
88)What is the Gray code wordfor the binary 101011?
[B] 110101
[D]111110
IE
[A] 101011
[C]011111
89)Which of the following subtraction operations results in F16

1. (BA)16 (AB)16
2. (BC)16 (CB)16
3. (CB)16 (BC)16
Select the correct answer using the code given below
[A] Only 1 and 2
[C] Only 2 and 3
[B] Only 1 and 3

[D]1, 2 and 3
90)The Boolean expression Y (A, B, C) = A + BC is to be realized using 2-input gates of only one type. What
is the minimum number of gates required for the realization?
[A] 1
[C]3
[B] 2
[D]4 or more
Page.No.11
91)Match List-I (Expression-I ) with List-II (Expression-II) and select the correct answer using the code given
below the lists :
List-I List-II
A.
1.
B.
2. A(B + C)
C.
3.
D.
4. AB + BC + AC
. [QDigA412] .. IES-EEE-2008(
[A] A-2, B-1, C-4, D-3

[C]A-2, B-3, C-4, D-1
[B] A-4, B-3, C-2, D-1

[D]A-4, B-1, C-2, D-3
92)The AND function can be realized by using only n number of NOR gates . What is n equal to ?
. [QDigA413] .. IES-EEE-2008(
[A] 2
[C]4
[B] 3
[D]5
an
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is logically equivalent to which of the following ?
1.
2.
3.
4.
Select the correct answer using the code given below :
. [QDigA415] .. IES-EEE-2008(
[A] 1 and 2
[C]1 and 3
[B] 2 and 3
[D]None of these
94)The Boolean expression X(P,Q,R) = (0,5) is to be realized using only two 2-input gates. Which are these
gates?
[A] AND and OR
[C]AND and XOR
[B] NAND and OR

[D]OR and XOR
IE
S,
B
95)What is the Boolean expression for the truth table shown below?
[A]
[C]
[B]
[D]
96)What does the Boolean Expression?
On minimization result into?

[A] A+D
[C]AD
[B] AD+A
[D]
97)If A and B are Boolean variables then what is (A+B). (A+
) equal to?
Page.No.12
[A] B
[C]A+B
[B] A
[D]AB
98)What is the Boolean expression
equivalent to ?
[A]
[C]B
[B]
[D]
99)Assume that only x and y logic inputs are available and the complements and are not available. What
is the minimum number of 2-input NAND gates required to implement
?
[A] 2
[C]4
[B] 3
[D]5
100)Which one of the following is the correct sequence of the numbers represented in the series given below?
(2)3, (10)4, (11)5, (14)6, (22)7 .........
[B] 2,4,6,8,10,......
[D]2,4,6,10, 16.....
an
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[A] 2,3,4,5,6.......
[C]2,4,6,10,12.....
101)What is the addition of (-64)10 and (80)16 ?

[A] (-16)10
[C](1100000)2
[B] (16)16
[D](01000000)2
102)When the Boolean function

F(x1x2x3) = (0, 1, 2, 3) + (4, 5, 6, 7)
is minimized, what does one get?
[A] 1
[C]x1
[B] 0
[D]x3
103)By inspecting the Karnaugh map plot of the switching function F(x1x2 x3) = (1, 3, 6, 7) one can say that
the redundant prime implicant is
S,
B
[A]
[C]x1x2
[B] x2x3
[D]x3
IE
104)For a function F , the Karnaugh map is shown in the figure below . Then minimal representation of F is
. [QDigA444] .. IES-EEE-2010(
[A]
[C]A + B + C
[B]
[D]
105)Match list-I (Boolean logic Function) with List-II (Inverse of Function) and select the correct answer using
the code given below the lists:
List-I List-II
A. ab+bc+ca+abc 1.
B.
2.
C. a + bc 3.
D. .
4.
[A] A-3 B- 2 C- 1 D- 4
[C]A- 3 B- 2 C- 4 D- 1
[B] A- 2 B- 3 C- 1 D- 4
[D]A- 2 B- 3 C- 4 D- 1
Page.No.13

106)Match List-I with List-II and select the correct answer using the codes given below the lists :
List-I List-II
A.
1. AB
B.
2.
C.
3. A + B
4.
an
ga
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re
D.
. [QDigA449] .. IES-EEE-2010(
[A] A-3, B-1, C-4, D-2

[C]A-3, B-4, C-1, D-3
[B] A-2, B-1, C-4, D-3

[D]A-3, B-4, C-1, D-2
107)Consider the following statements:

1. Minimization using Karnaugh map may not provide unique solution.
2. Re undant grouping in Karnaugh map may result in non-minimized solution
3. Dont care states if used in karnaugh map for minimization, the minimal solution is not obtained.
Which of the statements given above are correct?
[A] 1, 2 and 3
[C]1 and 3 only
. [QDigA457] .. IES-EEE-2011(
[B] 2 and 3 only

[D]1 and 2 only
[A]
[C]
S,
B
108)The Boolean expression for the shaded area in the Venn diagram shown is
[B]
[D]
IE
109)The Boolean functions can be expressed in canonical SOP (sum of products) and POS (product of sums)
form. For the functions.
which are such two forms
[A] Y= (1, 2, 6, 7) and Y = (0, 2, 4)

[C]Y= (1, 2, 5, 6, 7) and Y = (0, 1, 3)
[B] Y= (1, 4,5, 6, 7) and Y = (0, 2, 3)

[D]Y= (1, 2, 4,5,6, 7) and Y = (0, 2, 3,4)
110)The Boolean function A+BC is a reduced form of which one of the following
[A] AB+BC
[C](A+B) (A+C)
[B]
[D]None of the above
111)Which one of the following statements is not correct?

[A]
[C]
[B]
[D]
112)(24)8 is expressed in Cray code as which one of the following?

Page.No.14
[A] 11000
[C]11110
113)AND operation of
. [QDigA480] .. IES-EEE-2011(
[B] 10100
[D]11111
and
results in
[A] 50 H
[C]42 H
[B] 48 H
[D]08 H
114)Statement (I) : XOR gate is not a universal gate

Statement (II) : It is not possible to realize any Boolean function using XOR gates only
. [QDigA488] .. IES-EEE-2012(
[A] Both Statement (I) and statement (II) are

individually true and statement (II) is the correct
explanation of statement (I)
[C]Statement (I) is true but statement (II) is false
115)If
[B] Both Statement (I) and statement (II) are

individually true but statement (II) is not the
correct explanation of statement (I)
[D]statement (I) is false but statement (II) is true
, then the value of base x is :

. [QISRA066] .. ISRO-ECE/TCE-2012(
[B] 6
[D]9
an
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[A] 5
[C]7
116)In VHDL all the statements written inside a process statement are .......
[A] Concurrent
[C]Both of the above
[B] Sequential
117)Which of the following operator cannot be synthesized by VHDL synthesis tools

[A] +
[C]*
[B] [D]&
S,
B
118)The following code will implement a ..................

process (clk , d) begin
if (clk = '1' ) then
q <= d ;
end if ;
end process
[A] Positive edge triggered D- flip-flop
[C]A latch
[B] Negative edge triggered D-flip flop

119)The greatest negative number which can be stored in a 8-bit register using 2's complement arithmetic is
IE
[A] - 256
[C]- 127
[B] - 255
[D]- 128
120)Which statement is true regarding a behavior modeling in VHDL

[A] There can be more than one process statement
in an architecture which will interact concurrently
[C]process is not a single concurrent system
[B] Behavioral style of architecture can have only

concurrent assignment statements
[D]A process need not have sensitivity list for proper
implementation
121)When using a sequential code to design a combinational logic in VHDL , if complete truth table is not
defined , the synthesis tool will implement a ................ which is not required
[A] Clock buffer
[C]Flip flop
[B] Buffer
[D]Latch
122)The purpose of Design For Test (DFT) process in ASIC design flow is
[A] To capture functional errors
[C]To capture timing violations
[B] To capture manufacturing defects

[D]For radiation mitigation
Page.No.15

123)Which one of the following is the lowest level of abstraction for representation of a digital system ?
[A] VHDL / Verilog
[C]Gate level netlist
[B] GDS-II
[D]System C
124)How many adders are required to realize a 256 point radix-2 FET using
[A] 256
[C]4096
[B] 1024
[D]2048
125)Which of the following types of devices is not field programmable ?

[A] FPGA
[C]CPLD
[B] ASIC
[D]PLD
126)Which is the correct order of different process steps for a typical FPGA design ?
[B] Functional simulation , Timing Verification ,
Synthesis , Place &Route
[D]Synthesis , Functional simulation , Timing
Verification , Place &Route
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[A] Functional simulation , Synthesis , Place &Route ,

Timing Verification
[C]Timing Verification , Synthesis , Functional
simulation , Place &Route
127)The greatest negative number which can be stored in a computer that has 8-bit word length and uses 2's
complement arithmetic is
[A] - 256
[C]- 128
[B] - 255
[D]- 127
128)Which of the following relation is valid ?

Where MTBF = Mean Time Between Failures
MTTF = Mean Time To Failures
MTTR = Mean Time To Repair
[A] MTBF = MTTF + MTTR
[C]
S,
B
storage element is
129)
[A] Cross-coupled latch

[C]Capacitor
[B] MTTR + MTTF + MTBF = 1

[D]MTBF . MTTF . MTTR = 1
[B] Isolated gate transistor

[D]Flip flop
130)Odd parity generator uses .................... logic
IE
[A] XNOR
[C]Sequential
[B] XOR
[D]OR
131)Which type of memory has fast erase and write times

[A] EPROM
[C]Flash memory
[B] EEPROM
[D]None of these
132)Which of the following binary number is equal to octal number 66.3

[A] 101101.100
[C]111111.1111
[B] 1101111.111
[D]110110.011
133)Assuming that only the X and Y logic inputs are available and their complements
available , what is the minimum number of two-input NAND gates requires to implement
are not
?
[A] 2
[C]4
[B] 3
[D]5
Page.No.16
134)In the given network of AND and OR gates f can be written as :
[A]
[B]
[D]
[C]
135)How many 1 ' s are present in the binary representation of 3 x 512 + 7 x 64 + 5 x 8 + 3 ?

[A] 8
[C]10
[B] 9
[D]11
[A] 1100
[C]0110
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136)Gray code for number 7 is

[B] 1001
[D]0100
137)For the switch circuit , taking open as 0 and closed as 1 , the expression for the circuit is Y .
[A] A + (B + C)D
[C]A (BC + D)
[B] A + BC + D
[D]None of these
IE
S,
B
138)The Boolean expression for the shaded area in the Venn diagram is
[A]
[C]X + Y + Z
[B]
[D]
139)Given the decimal number - 19 , an eight bit two's complement representation is given by
[A] 11101110
[C]11101100
[B] 11101101
[D]None of these
140)The function shown in the figure when simplified will yield a result with
Page.No.17
[A] 2 terms
[C]7 terms
[B] 4 terms
[D]16 terms
141)BCH code belongs to

[A] Block Codes
[C]Turbo Codes
[B] Convolution Codes

142)The number of product terms in the minimized sum-of-product expression obtained through the following
k-map is (where " d " denotes don't care states )
. [QDigA002] .. (
. [QDigA009] .. (
[B] 3
[D]5
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[A] 2
[C]4
143)Minterm (sum of products ) expression for a Boolean function is given as follows.

Where A is MSB and C is the LSB . The minimized expression for the function is
[A]
[C]
[B]
[D]
144)In a given switching function the number of variables are 4 , the number of prime implications are 'm' and
the number of essential prime implicants are (m-1) then the number of minimal expressions are
[A] 4
[C]1
. [QDigA021] .. (
[B] 2
[D]The data in the problem is not enough to decide
[A] 23
[C]31
[A]
[C]
. [QDigA022] .. (
. [QDigA023] .. (
. [QDigA025] .. (
[B] 32
[D]13
, then which one of the following is true ?
IE
146)If
S,
B
145)In the following series the same integer is expressed in different number system 10000, 121, 100 , ? , 24 ,
22, 20 ,....... The missing member of the series is
[B]
[D]
147)In a cyclic prime - implicant K-map

[A] Number of prime- implicants are equal to the
number of variables
[C]Number of prime implicants are double the
number of variables
148)If
[A]
[C]
149)Let
[A]
[C]xy + z
[B] Number of prime implicants are half of the

number of variables
[D]Number of prime implicants number way related
to the number of variables
and
then
is
. [QDigA031] .. (
. [QDigA032] .. (
[B]
[D]
, simplified expression for function f(f(x + y, y) , z) is

[B] xyz
[D]1
Page.No.18

150)A digital circuit is monitoring three pumps whenever majority pumps fails the circuit panel LED must glow ,
otherwise LED must OFF . The digital circuit output must be zero whenever the majority of the pumps fails
. The possible minimal SOP expression of the circuit is [ Consider the Boolean variables assigned to
pumps are x , y, z ]
. [QDigA035] .. (
. [QDigA036] .. (
[B]
[D]
[A]
[C]xy + yz + zx
151)Which one of the following statement is true

[A] Excess-3 code is self complementary code
because of 2's complement of excess-3 code is
9's complement of given BCD number
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[C]Excess-3 code is self complementary code

9's complement of given BCD number is 2's
complement
[B] Excess-3 code is self complementary code

9's complement of given BCD number is 1's
complement form
[D]Excess-3 code is self complementary code
because of 1's complement of given BCD number
Excess-3 code is 9's complement of given BCD
number in Excess-3 form
IE
S,
B
Page.No.19
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S,
B
ng
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1.
To know how to use our portal for

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Page.No.20
Institute of Engineering Studies (IES,Bangalore)

Leading Institute for GATE/IES/JTO/PSUs in (Branches @ Jayanagar &Malleshwaram) Bangalore.

Contact: (+91) 99003 99699 E-Mail: onlineies.com@gmail.com Site: www.onlineies.com
Branch :--EC/EE/IN/CS/IT
Subject: Digital Electronics
Topic: Combinational Logic
Total Questions :119
CLASS ROOM PRACTICE PROBLEMS
1)The point Z in the following figure is stuck at -1 . The output f will be ..........
. [QDigA003] .. (
. [QDigA008] .. (
[B]
[D]A
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[A]
[C]
2)Match the following

List-I
List-II
P. Full adder
1. Sequential digital circuit
Q. Multiplexer
2. One bit adder
R. Read/Write Memory
3. Two bit adder
S. ROM
4. Universal gate
5. Universal element
6. Combination of decoder &demux
7. Combination of decoder &encoder
[A] P-3, Q-5, R-1, S-7
[C]P-4, Q-1, R-7, S-2
[B] P-2, Q-5, R-1, S-7

[D]P-4, Q-3, R-5, S-7
IE
S,
B
3)A combinational circuit using a 8-to-1 mux is shown in the following figure . The minimized expression for
the output (Z) is
. [QDigA010] .. (
[A]
[C]
4)A digital circuit which compares two numbers

Choose one pair of correct input numbers
[B] C (A + B)
[D]
is shown in figure to get output Y = 0 .
Page.No.21
[A] 1010 , 1010

[C]0010, 0010
. [QDigA013] .. (
. [QDigA015] .. (
. [QDigA016] .. (
[B] 0101, 0101

[D]0010, 1011
5)Identify the code converter shown below
[A] Excess-3 to BCD code converter

[C]BCD to gray code converter
[B] BCD to Excess -3 code converter

[D]Gray to BCD code converter
6)Without any additional circuitry an 8 : 1 MUX can be used to obtain

[B] All functions of 3 variables but none of 4 variables
[D]All functions of 4 variables
an
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[A] Some but not all Boolean functions of 3 variables

[C]All functions of 3 variables and some but not all of
4 variables
7)Identify the fastest adder circuit from the following

[A] Ripple carry adder
[C]Carry look-ahead adder
. [QDigA019] .. (
[B] Serial adder

[D]none of these
8)The minimum number of 2 input NAND gates required to implement the following Boolean function
[A] 3
[C]5
. [QDigA026] .. (
. [QDigA027] .. (
. [QDigA029] .. (
[B] 4
[D]6
IE
[A]
[C]
S,
B
9)The output 'f' of the 4 to 1 MUX shown in figure is
[B] x + y
[D]xy + x
10)Match List-I with List-II and select the correct answer by using the code given below the lists :
List-I List-II
P. Multiplexer 1. Sequential memory
Q.De-Multiplexer 2. Converts decimal number to binary
R. Shift-Register 3. Data selector
S. Encoder 4. Routes out many data output with single input
[A] P-3, Q-4, R-1, S-2
[C]P-4, Q-3, R-1, S-2
[B] P-3, Q-4, R-2, S-1

[D]P-1, Q-2, R-3, S-4
Page.No.22
11)Consider the circuit shown in figure . The output of 2 : 1 MUX is given by the function ac + bc . Which of
the following is true ?
[A]
[C]
. [QDigA030] .. (
. [QDigA034] .. (
. [QDigA039] .. (
[B]
[D]
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12)The output function 'f' of the given logic circuit is
[A]
[C]
[B]
[D]
13)The logic circuit shown in the given figure can be minimized to
[B]
[C]
S,
B
[A]
[D]
IE
14)It is possible to realize 32 x 1 MUX by using (Consider A, B, C, D and E are select variables of 32 x 1 MUX
and A is MSB variable and 'E' is LSB variable
[A] 4 x 1 MUX 11 number while connecting A and B
variable at level-1 MUX and C and D at level-2
and E at level-3
[C]4 x 1 MUX 11 number while connecting D and E
variables at level-1 and B and C at level-2 and A
at level-3
. [QDigA042] .. (
[B] 4 x 1 MUX 11 number while connecting C and D

variable at level-1 and A and E at level-2 and B at
level-3
[D]4 x 1 MUX 11 number while connecting any
variable at any level
15)A 4-bit binary adder is adding two BCD numbers . The output from the adder is with variables DCBA (D is
MSB) and carry . If it is required to develop a checking circuit its output must be zero , when the binary
adder result is valid BCD otherwise output is 1 . The possible Boolean expression f of the checking circuit
is
. [QDigA043] .. (
[A]
[C]f = DC + DB
[B]
[D]
Page.No.23
16)Consider the logic circuit shown below has four bit binary number
as output the circuit implements
as input and five bit number
. [QDigA044] .. (
[A] Binary to Hex conversion

[C]Binary to Gray code conversion
[B] Binary to BCD conversion

[D]Binary to radix-12 conversion
an
ga
lo
re
17)The block box in the following figure consists of a minimum complexity circuit that uses only AND , OR and
NOT gates
The function f(x, y, z) = 1 whenever x, y are different and '0' otherwise in addition the 3 inputs x, y and z
are never all the same value . Which of the following equation lead to the correct design for the minimum
complexity circuit ?
[A]
[C]
. [QDigA045] .. (
. [QDigA046] .. (
[B]
[D]
IE
S,
B
18)In figure the LED
[A] Emits light when both

[C]Emits light when
and
is open
are closed
are open
[B] Emits light when both and are open

[D]Does not emit light , irrespective of the switch
positions
19)Which of the following circuits represents AND-OR-INVERT function ?

. [QDigA053] .. (
Page.No.24
[A]
[B]
[C]
[D]
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20)The output equation of the following digital circuit is
[A]
[C]
. [QDigA056] .. (
[B]
[D]
[A] 1, 2, 3
[C]3, 4 &5
S,
B
21)Pick up the correct statements from the following

1. Any given three variable Boolean equation can be implemented using 4 x 1 multiplexer without using
any additional gates
2. One-cold code can be generated with active low output type of decoder
3. Read only memory is not a sequential digital circuit
4. Asynchronous counters are slow when compared to synchronous counters
5. Full adder is an example for 3-bit adder
. [QDigA057] .. (
. [QDigA058] .. (
[B] 2, 3 &4
[D]1,3 &5
IE
22)Find the input conditions needed to produce X = 1 in the logic shown below
[A] 111
[C]011
[B] 101
[D]101
Page.No.25
23)A 3-line to 3-line decoder , with active low outputs is used to implement a 3-variable Boolean function as
shown in the figure
The simplified form of Boolean function f(x, y, z) implemented in sum of products form is
[A] xy + yz + zx
[C]
. [QDigA059] .. (
. [QDigA062] .. (
[B]
[D]
an
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24)What is the code converter shown in the figure
[A] 3-bit Binary to gray code converter

[C]3-bit Binary to gray/ gray to binary code converter
[B] 3-bit gray to binary code converter

[D]4-bit binary to octal code converter
[A]
[C]
IE
S,
B
25)The Boolean equation F(x, y, z) = (0, 2, 4, 7) is to be implemented using 4 1 multiplexer shown in

figure. Which one of the following choices of inputs to multiplexer will realize the Boolean function ?
. [QDigA072] .. (
[B]
[D]
26)What is the Code Converter shown below ?
Page.No.26
. [QDigA074] .. (
[A] Binary to gray

[C]Binary to 1's complement
[B] Gray to Binary

[D]3-bit binary to 2's complement of input
Statement for Linked answer Q27 and Q28 is given below
What is the circuit shown above

[A] Full adder
[C]Half adder
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27)Consider the combinational circuit shown below
. [QDigA082] .. (
. [QDigA083] .. (
. [QDigA086] .. (
[B] Full subtractor

[D]Quarter adder
[A] 8
[C]10
S,
B
28)Minimum number of two input NAND gates required to implement above circuit
[B] 9
[D]11
IE
29)The logic realized by the circuit shown in figure is
[A]
[C]
[B]
[D]
30)For a binary half-subtractor having two inputs A and B, the correct set of logical expressions for the
outputs D (= A minus B) and X (= borrow) are
[A]
[C]
[B]
[D]
Page.No.27
31)For the logic circuit shown in the figure, the required input condition (A, B, C) to make the output (X) = 1 is
[A] 1, 0, 1
[B] 0, 0, 1
[C]1, 1, 1
[D]0, 1, 1
[A] A+B+C
[C]B
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32)For the logic circuit shown in the figure, the simplified Boolean expression for the output y is
[B] A
[D]C
S,
B
33)In the figure, the LED
[A] emits light when both S1 and S2 are closed.

[C]emits light when only of S1 and S2 are closed.
[B] emits light when both S1 and S2 are open.

[D]does not emit light, irrespective of the switch
positions.
IE
34)If the input to the digital circuit (in the figure) consisting of a cascade of 20 XOR- gates is X, then the
output Y is equal to
[A] 0
[C]
[B] 1
[D]X
35)The gates G1and G2 in the figure have propagation delays of 10nsec and 20 nsec respectively. If the input
Vi makes an abrupt change from logic 0 to 1 at time t = t0, then the output waveform V0 is
Page.No.28
[A]
[B]
[C]
[D]
36)without any additional circuitry an 8:1MUX can be used to obtain

[A] some but not all Boolean functions of 3 variables
[C]all functions of 3 variables and some but not all of
4 variables
[B] all functions of 3 variables but none of 4 variables

[D]all functions of 4 variables
The circuit acts as a
an
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37)The circuit shown in the figure has 4 boxes each described by inputs P, Q, R and outputs Y, Z with
[A] 4 bit adder giving P+Q

[C]4 bit subtractor giving Q-P
[B] 4 bit subtractor giving P-Q

[D]4 bit adder giving P+Q+R
IE
S,
B
38)The circuit shown in the figure converts
[A] BCD to binary code

[C]Excess- 3 to Gray code
[B] Binary to excess- 3 code

[D]Gray to Binary code
39)The minimum number of 2-t0-1 multiplexers required to realize a 4-to-1 multiplexer is

[A] 1
[C]3
[B] 2
[D]4
Page.No.29
40)The Boolean function f implemented in the figure using two input multiplexers is
[A]
[C]
[B]
[D]
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41)The point P in the following figure is stuck-at-1. the output f will be
[B]
[D]A
[A]
[C]
42)In the following circuit, X is given by
[B]
[D]
S,
B
[A]
[C]
IE
43)Which of the following Boolean Expressions correctly represents the relation between P, Q, R and M1 ?
[B] M1 = (P AND Q) XOR R
[A] M1 = (P OR Q) XOR R
[C]M1 = (P NOR Q) XOR R
[D]M1 = (P XOR Q) XOR R
Page.No.30
44)For the circuit shown in the following figure I0- I3 are input to the 4:1 multiplexer. R (MSB) and S are
control bits.
The output Z can be represented by

[B]
[D]
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[A]
[C]
45)What are the minimum number of 2-to-1 multiplexers required to generate a 2-input AND gate and a 2input Ex-OR gate?
[A] 1 and 2
[C]1 and 1
[B] 1 and 3
[D]2 and 2
S,
B
46)Two products are sold from a vending machine, which has two push buttons P1 and P2. When a button is
pressed, the price of the corresponding product is displayed in a 7-segment display. If no buttons are
pressed 0 is displayed, signifying Rs. 0. If only P1 is pressed 2 is displayed signifying Rs.2
If only P2is pressed 5 is displayed signifying Rs. 5. If both P1 and P2are pressed E is
displayed.Signifying Error the names of the segments in the 7-segment display, and the glow of the
display for 0, 2 5 and E are shown below:
[A]
[C]
IE
Consider
(i) push button pressed/not pressed in equivalent to logic 1/0 respectively.
(ii) a segment glowing/not glowing in the display is equivalent to logic 1/0 respectively.
If segments a to g are considered as functions of P1 and P2, then which of the following is correct?
[B]
[D]
47)What are the minimum numbers of NOT gates and 2-input OR gates required to design the logic of the
driver for this 7-segment display?
[A] 3 NOT and 4 OR
[C]1 NOT and 3 OR
[B] 2 NOT and 4 OR

[D]2 NOT and 3 OR
48)Assertion (A): A demultiplexer can be used as a decoder.

Reason (R): A demultiplexer is built by using AND gates only.
Page.No.31
[B] Both A and R are true but R is not the correct
[A] Both A and R are true and R is the correct
explanation of A
explanation of A
[C]A is true but R is false
[D]A is false but R is true
49)The given figure shows a NAND gate with input waveforms A and B
The correct output waveform X of the gate is

[B]
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[A]
[D]
[C]
50)The output Y of the given circuit is
[B] zero
[D]
IE
S,
B
[A] 1
[C]X
Page.No.32
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51)The input waveform Vi and the output waveform V0 of a Schmitt NAND are shown in the given figures.
The duty cycle of the output waveform will be
[A] 100%
[C]72.2%
[B] 85.5%
[D]25%
[C]
IE
[A]
S,
B
52)The logic circuit realized by the circuit shown in the given figure will be
[B]
[D]
53)Which one of the following figures represents the coincidence logic?

[A]
[C]
[B]
[D]
Page.No.33
54)Which one of the following circuits is the minimized logic circuit for the circuit shown in figures I?
[A]
[B]
[C]
[D]
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55)The circuit shown in the given figure realizes the function
[A]
[C]
[B]
[D]
56)The logic operations of two combinational circuits given in Figure-I and Figure-II are
Figure-I
S,
B
Figure-II
[A] entirely different

[C]complementary
[B] identical
[D]dual
IE
57)Which one of the following statements correctly defines the full-adder?

An adder circuit
[A] having two inputs used to add two binary digits. It
produces their sum and carry as input
[C]used in the least significant position when adding

two binary digits with no carry-in to consider. It
produces their sum and carry as outputs.
[B] having three inputs used to add two binary digits

plus a carry. It produces their sum and carry as
outputs.
[D]having two inputs and two outputs.
Page.No.34
58)The half-adder circuit in the given figure has inputs AB=11
The logic level of P and Q outputs will be

[B] P = 0 and Q=1
[A] P = 0 and Q = 0
[C]P =1 and Q = 0
[D]P = 1 and Q = 1
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A multiplexer
1. Selects one of the several inputs and transmits it to a single output
2. routes the data from a single input to one of many output
3. converts parallel data into serial data
4. is a combinational circuit
Which of these statements are correct?
[A] 1, 2 and 4
[C]1, 3 and 4
[B] 2,3 and 4
[D]1, 2 and 3
60)Assertion (A): A look-ahead carry adder is a fast adder.

Reason (R) : A parallel carry adder generates sum digits directly from the input digits
S,
B
[A] Both A and R are true and R is the correct

explanation of A
[C]A is true but R is false
[B] Both A and R are true but R is not the correct

explanation of A
[D]A is false but R is true
IE
61)The circuit shown in the given figure is
[A] an adder circuit

[C]a comparator circuit
[B] a substractor circuit

[D]a parity generator circuit
62)The number of 4-line to-16 line decoders required to make an 8-line to 256 line decoder is
Page.No.35
[A] 16
[C]32
[B] 17
[D]64
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63)Consider the following circuits (Assume all gates to have a finite propagation delay)
Which of these circuits generate a periodic square wave output?
[A] 1 and 2
[C]2, 3 and 4
[B] 3 and 4
[D]1, 2, 3 and 4
S,
B
64)The addition of two binary variables A and B results into a SUM and a CARRY output . Consider the
following expressions for the SUM and CARRY outputs.
Which of these expressions are correct?
IE
[A] 1 and 3
[C]2 and 4
[B] 2 and 3
[D]1 and 4
65)for a binary half- subtractor having two inputs A and B, the correct sets of logical expression for the output
D (= A minus B) and X (= borrow) are
[A]
[C]
[B]
[D]
66)The circuit shown below is functionally equivalent to
Page.No.36
[A] NOR gate

[C]EX-OR gate
[B] OR gate
[D]NAND gate
67)For the output F to be 1 in the logic circuit shown , the input combination should be
[A] A = 1 , B = 1 , C = 0
[C]A = 0 , B = 1 , C = 0
[B] A = 1 , B = 0 , C = 0
[D]A = 0 , B = 0 , C = 1
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68)The output Y in the circuit below is always " 1 " when
[A] two or more of the inputs P, Q, R are " 0 "

[C]any odd number of the inputs P, Q, R is " 0 "
[B] two or more of the inputs P, Q, R are " 1 "

[D]any odd number of the inputs P, Q, R is " 1 "
IE
S,
B
69)The logic function implemented by the circuit below is (ground implies a logic " 0 " )
[A] F = AND (P, Q)

[C]F = XNOR (P, Q)
[B] F = OR (P, Q)
[D]F = XOR (P, Q)
70)Consider the following logic circuit:

What is the required input condition (A,B, C) to make the output X =1, for the above logic circuit?
[A] (1,0,1)
[C](1,1,1)
[B] (0,0,1)
[D](0,1,1)
71)The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input
B . The number of combinations for which the output is logic 1 , is
Page.No.37
. [QDigA288] .. GATE-ECE/TCE-2012,GATE-EEE-2012(
[A] 4
[C]8
[B] 6
[D]10
72)Which one of the following statements describes the operation of a multiplexer?

[A] A logic circuit used to generate coded output

[C]A logic circuit that accepts two or more inputs and
allows one of them at a time to get through the
output
[B] A logic circuit used to generate Fs complement

[D]A logic circuit that transmits one input to several
output lines

[A] An 8 input MUX can be used to implement any 4

variable functions
[C]A 64 input MUX can be built using nine 8 input
MUXs
[B] A 3 line to 8 line DEMUX can be used to

implement any 4 variable function
[D]A 6 line to 64 line DEMUX can be built using nine
3 line to 8 line DEMUX
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74)The Boolean function realized by the logic circuit shown is
[B]
[A]
[C]
[D]
75)A 1-bit full adder takes 20 ns to generate carry-out bit and 40 ns for the sum bit. What is the maximum rate
of addition per second when four 1-bit full adders are cascade?
S,
B
[A] 107
[C]6.25 x 106
[B] 1.25 x 107

[D]105
IE
76)Consider the followingstatements

A 4: 16 decoder can beconstructed (with enable input) by
1. using four2:4 decoders(each with an enable input) only.
2,. Using five 2:4 decoders(each with an enable input) only
3. using two 3:8 decoders(each with an enable input) only
4. using two 3:8 decoders(each with an enable input) and inverter
Which of the statements givenabove is/are correct
[A] 2 and 3
[C]2 and 4
[B] 1 only
77)What is the output f (x,y) of the multiplexer resulting from the input logical values?
Page.No.38
[A] An EXOR gate

[C]An AND gate
[B] A NOR gate

[D]A NAND gate
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78)Figure shows a 4 to 1 MUX to be used to implement the sum S of a 1-bit full adder with input bits P and Q
and the carry input
. Which of the following combinations of inputs to
of the MUX will
realize the sum S ?
[A]
[C]
[B]
[D]
S,
B
79)A digital circuit which compares two numbers

choose one pair of correct input numbers
IE
[A] 1010, 1010

[C]0010 , 0010
is shown in figure. To get output Y = 0,
[B] 0101 , 0101

[D]1010 , 1011
80)A 4 x 1 MUX is used to implement a 3-input Boolean function as shown in figure. The Boolean function
F(A, B, C) implemented is
[A]
[C]
[B]
[D]
Page.No.39

81)A, B, C, and D are input, and Y is the output bit in the XOR gate circuit of the figure below. Which of the
following statements about the sum S of A, B, C, D and Y is correct ?
[A] S is always with zero or odd

[C]S = 1 only if the sum of A, B, C and D is even
[B] S is always either zero or even

[D]S = 1 only if the sum of A, B, C and D is odd
82)For the circuit shown in the below figure, the output F will be
. [QDigA334] .. IES-EEE-2001(
[B] zero
[D]
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[A] 1
[C]X
83)The Boolean expression for the output Y in the logic circuit is
[A]
[C]
. [QDigA339] .. IES-EEE-2002(
. [QDigA340] .. IES-EEE-2002(
. [QDigA341] .. IES-EEE-2002(
. [QDigA344] .. IES-EEE-2002(
[B] ABC
[D]
84)To add two m-bit numbers , the required number of half adders is
[A] 2 m - 1
[C]2 m + 1
[B]
[D]2 m
IE
[A] 1 , 2 and 3
[C]2, 3 and 4
S,
B
85)Consider the following :

Any combinational circuit can be built using
1. NAND gates
2. NOR gates
3. EX-OR gates
4. Multiplexers
Which of these are correct ?
[B] 1, 3 and 4
[D]1, 2 and 4
86)A 3-to-8 decoder is shown below :
All the output lines of the chip will be high, when all the inputs 1, 2 and 3
[A] are high ; and

[C]are high ; and
,
,
are low
are high
[B] are high ; and

[D]are high ; and
is low , is high
is high , is low
Page.No.40

87)Which one of the following statements is not correct ? Conversion of EXCESS-3 code to BCD can be
achieved by using
. [QDigA353] .. IES-EEE-2003(
[A] Discrete gates

[C]A 4-bit full adder
[B] 4 : 16 de-multiplexer
[D]A 4-bit half adder
88)Match List-I (operation) with List-II (Associated Device) and select the correct answer using the codes
given below :
List-I List-II
A. Counting 1. ROM
B. Decoding 2. Multiplexer
C. Data selection 3. Demultiplexer
D. Code conversion 4. Register
. [QDigA362] .. IES-EEE-2004(
[A] A-3, B-4, C-2, D-1

[C]A-4, B-3, C-1, D-2
[B] A-3, B-4, C-1, D-2

[D]A-4, B-3, C-2, D-1
89)It is required to construct a to 1 multiplexer by using 2 to 1 multiplexers only. How many of 2 to 1

multiplexers are needed?
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. [QDigA364] .. IES-EEE-2004(
[A] n
[C]
[B]
[D]
90)Consider the following circuit :
Which one of the following gives the function implemented by the MUX based digital circuit ?
S,
B
. [QDigA365] .. IES-EEE-2004(
[A]
[C]
[B]
[D]
[A]
[C]
IE
91)A range decode is a digital circuit which outputs as 1 whenever an m-bit number X falls within the range
X , 0 P, q m 1.
Which one of the following functions describes the range decoder?
. [QDigA367] .. IES-EEE-2004(
[B]
[D]
92)What are the output bits S (sum) and C (Carry) of a Half adder having inputs A = 1 and B = 1 ?
[A] S = 1, C=1
[C]S = 0 , C = 1
. [QDigA381] .. IES-EEE-2007(
[B] S = 1, C= 0
[D]S = 0 , C = 0
93)Which one of the following functions realized by the circuit shown below?
[A]
[C]AB+C+DE
[B] (A+B) C+D+E

[D]AB +C(D+E)

Page.No.41
[A] A full adder can be constructed using two half

adders and an OR gate
[C]Ripple carry adder has addition time independent
of the number of bits.
[B] Two four bit parallel adders can be cascaded to

constructed 8-bit parallel adder.
[D]carry look ahead is used to speed up the parallel
addition.

A half- adde
1. is a half-subtractor also.
2. has two outputs
for two inputs x and y.
3. has two outputs

or two inputs x and y.
4. is a combinational circuit.
Which of the statements given above is/are correct?
[A] 1,3 and 4

[C]4 only
[B] 1,2 and 4

[D]2 and 3
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96)What is the number of selector lines required in a single input n-output demultiplexer?
[A] 2
[C]2n
. [QDigA419] .. IES-EEE-2009(
[B] n
[D]log2n
97)I =1, J = B
The circuit shown above is to be used to implement the function
[A] I=1 J=B

[C]I=B, J=1
S,
B
What values are to be selected for I and J?
[B] I=A , J=B

[D]
IE
98)Which one of the following is the correct output ( f ) of the below circuit ?
[A]
[C]
[B]
[D]
99)Which one of the following logical operations is performed by the digital circuit shown below?
[A] NOR
[B] NAND
Page.No.42

[D]OR
[C]EX-OR
100)When two 16-input multiplexers drive a 2-input MUX, what is the result?
[A] 2-input MUX
[C]16-input MUX
[B] 4-input MUX

[D]32-input MUX
101)For the logic circuit given above, what is the simplified Boolean function?
[A] X=AB+C
[C]X=AB+AC
[B] X=BC+A
[D]X=AC+B
[A] 1 and 4 only

[C]1 and 3 only
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102)consider the following statements:

For 3 input variables a, b, c; a Boolean function y = ab+bc+ca represents
1. a 3-input majority gate
2. a 3-input minority gate
3. carry output of a full adder
4. product circuit for a, b and c
Which of the above statements are correct?
. [QDigA447] .. IES-EEE-2010(
[B] 2 and 3 only

[D]3 and 4 only
IE
[A]
[C]
S,
B
103)The circuit shown in the figure below generates the function of
[B] 0
[D]
104)For logic circuit shown , the required inputs A, B and C to make the output X = 1 are respectively
. [QDigA456] .. IES-EEE-2011(
[A] 1, 0 and 1
[C]1 , 1 and 1
[B] 0, 0 and 1
[D]0 , 1 and 1
Page.No.43
105)The black box in the above figure consists of a minimum complexity circuit that uses only AND OR and
NOT gates.
The function f (x,y,z) = 1 whenever x,y are different and 0 otherwise. In addition the 3 inputs x,yz are never
all the same value which one of the following equations leads to the correct design for the minimum
complexity circuit?
[A]
[C]
[B]
[D]
The circuit shown below

of the following?
[A] NOR gate

[C]EX-OR gate
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106)
is functionally equivalent to which one
[B] OR gate
[D]NAND gate
107)Which one of the following statements is correct?
[A] Static 1 hazard may occur in a 2-level AND-OR

gate network
[C]Dynamic hazard may occur in a 2 level OR-AND
gate network
[B] Static 0 hazard may occur in a 2 level AND-OR

gate network
[D]Essential hazards may occur in a combinational
logic circuit
S,
B
108)A digital multiplexer can be used for which of the following?

1. Parallel to serial conversion
2. Many-to-one switch
3. To generate memory chip select
4. For code conversion
Select the correct answer using the code given below:
[B] 2, 3 and 4
[D]2 and 3 only
IE
[A] 1, 3 and 4
[C]1 and 2 only
109)For the logic circuit shown in the below figure. What is the required input condition (A.B,C) to make output
X = 1?
[A] 1, 0, 1
[C]1, 1, 1
[B] 0, 0, 1
[D]0, 1, 1
Page.No.44
110)The output of the circuit shown in the figure is equal to
[A] 0
[C]
[B] 1
[D]
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111)The truth table for implementing a boolean variable F is given by
Which d represents don't care states . The minimized expression for F is
[A]
[C]
[B]
[D]None of above
112)Minimum number of 2-input NAND gates that will be required to implement the function :
Y = AB + CD + EF is
[B] 5
[D]7
S,
B
[A] 4
[C]6
113)A programmable device (PROM) is
[A] programmable OR and fixed AND array

[C]programmable AND and programmable OR array
[B] programmable AND and fixed OR array

[D]None
114)A half-adder can be constructed using two 2-input logic gates . One of them is an AND-gate , the other is
IE
[A] OR
[C]NOR
. [QISRA424] .. ISRO-ECE/TCE-2007,ISRO-ECE/TCE-2007(
[B] NAND
[D]EX-OR
115)The Boolean expression for the output of the logic circuit shown in the figure is
[A]
[C]
116)For the identity
[B]
[D]
, the dual form is

[A]
[C]
[B]
[D]
Page.No.45

117)The combinational logic circuit shown in the given figure has an output Q which is
[A] ABC
[C]
[B] A + B + C
[D]A.B + C
118)The sum S of A and B in a half Adder can be implemented by using K NAND gates . The value of K is
[A] 3
[C]5
[B] 4
[D]None of these
into
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119)The logic circuit given below converts a binary code
[A] Excess-3 code

[C]BCD code
IE
S,
B
[B] Gray code

[D]Hamming code
Page.No.46
Key Paper
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S,
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Digital Electronics,

Basics & Combinational

(Useful For EC/EE/IN/CS/IT)

Institute of Engineering Studies

Digital Electronics Class room Practice Questions ONLY for

Institute of Engineering Studies (IES,Bangalore),

Institute of Engineering Studies (IES,Bangalore)

Leading Institute for GATE/IES/JTO/PSUs in (Branches @ Jayanagar &Malleshwaram) Bangalore.

Total Questions :151

CLASS ROOM PRACTICE QUESTIONS

Common Data for Q1 and Q2 is given below

The function f(A, B, C, D) =

2)Prime implicant set is

4)Pick up correct statement from the following

S. The Boolean function f(w, x, y, z) =

5)How many Boolean equations of the form f(x, y, z) =

are possible with three variable x, y and z ?

6) The Boolean function f(w, x, y, z) =

7)What is the minimized logic expression corresponding to the given k-map ?

9)The 2s complement representation of 17 is

10)The logical expression

11)The minimized form of the logical expression

12)4- bit 2s complement representation of a decimal number is 1000. the number is

13)The number of distinct Boolean expressions of 4 variables is

15)Statement (I) : Tristate logic is used for bus oriented systems .

[B] Both Statement (I) and statement (II) are

16)If the functions W, X, Y and Z are as follows

For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com

19)The minimum decimal equivalent of the number 11C.0 is

20)(FE35)16 XOR (CB 15)16 is equal to

21)Kannaugh map is used to

[B] minimize the number of gates only in a digital

[C]minimize the number of gates and fan in of a

22)Fs complement of (2BFD)hexis

23)The Boolean expression

[B] -6, - 6 and 6 respectively

25)A Boolean function f of two variables x and y is defined as follows:

26)Decimal 43 in Hexadecimal and BCD number system is respectively

[B] 2B, 0100 00 11

27)The Boolean expression for the truth table shown is

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32)The Boolean expression

34)If X = 1 in the logic equation

35)The Boolean theorem

36)Y= f(A,b) = M (0,1,2,3) represents (M is Maxterm)

[B] NAND gate

[A] NOR gate

[D]a situation where output is independent of input

37)The number of digital 1 present in the binary representation of 3 x 512 + 7 x 64 + 5 x 8 + 3 is

[A] NAND or NOR

[B] and AND or an EX-NOR

40)Which one of the following is equivalent to the Boolean expression

41)Given Boolean Theorem

[B] 0, 10110. 1001

43)Which of the following represents E316

[B] (1BC)16 (DE)16

[A] (ICE)16 + (A2)16

44)With 4 Boolean variables how many Boolean expressions can be formed?

[D]64 (64 x 1024)

45)How is inversion achieved using EX-OR gate?

[A] Giving input signal to the two input lines of the

47)Consider the Boolean expression

48)Which of the following is a self complementing code?