7, JULY 2014
2371
I. I NTRODUCTION
Manuscript received July 2, 2013; revised February 25, 2014, April 1, 2014,
and May 5, 2014; accepted May 8, 2014. Date of publication May 29, 2014;
date of current version June 17, 2014. This work was supported in part
by the National Science Council of Taiwan the Ministry of Science and
Technology of Taiwan and in part by the University of California IMPACT+
Research Program. The review of this paper was arranged by Editor
Y.-H. Shih.
Y.-B. Liao and W.-C. Hsu are with the Department of Electrical Engineering,
Institute of Microelectronics, National Cheng Kung University, Tainan 701,
Taiwan.
M.-H. Chiang is with the MS Degree Program on Nano-Integrated-Circuit
Engineering, Department of Electrical Engineering, National Cheng Kung
University, Tainan 701, Taiwan (e-mail: mhchiang@mail.ncku.edu.tw).
N. Damrongplasit and T.-J. K. Liu are with the Department of Electrical Engineering and Computer Sciences, University of California at
Berkeley, Berkeley, CA 94720 USA (e-mail: nattapol@eecs.berkeley.edu;
tking@eecs.berkeley.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2014.2323059
0018-9383 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
2372
Fig. 3.
Fig. 2. (a) 3-D view and channel region cross section of the GAA MOSFET
(not to scale). (b) Simulated IDS VGS characteristics for various designs with
the same scale length, GAA (3.3 nm).
2373
TABLE I
C OMPARISON OF GAA MOSFET P ERFORMANCE PARAMETERS FOR
C ELL O PERATING V OLTAGE VDD = 0.68 V. C URRENT VALUES A RE
N ORMALIZED TO E FFECTIVE C HANNEL W IDTH ( HSi + WSi ) 2
Fig. 4. Impact of random variations on ION versus IOFF for GAA MOSFETs
of various designs of the same scale length, GAA (3.3 nm).
2374
Fig. 7.
Fig. 10. Impact of cell operating voltage VDD on SNM and IW for various
GAA 6-T SRAM designs. For each curve, VDD ranges from 0.35 to 0.8 V in
50-mV steps.
Fig. 8. Butterfly plots for 6-T SRAM cells implemented with single-NW
GAA MOSFETs. Good agreement in SNM between TCAD (mixed-mode)
simulations and the macromodel is seen.
Fig. 9. Write N-curves for 6-T SRAM cells implemented with single-NW
GAA MOSFETs. Good agreement in IW values between TCAD (mixedmode) simulations and the macromodel is seen.
2375
TABLE II
L AYOUT D IMENSIONS FOR 11.9- NM N ODE 6-T SRAM C ELL . T HE
H ALF -C ELL L AYOUT I S S HOWN ON THE R IGHT FOR R EFERENCE
Fig. 12. GAA 6-T SRAM cell read (SNM) yield and write (Iw ) yield as a
function of cell operating voltage.
Fig. 11. 6-T SRAM half-cell layouts (not to scale). (a) Square (HSi = 10 nm)
double-NW PD and (b) rectangular (HSi = 7.5 nm) GAA SRAM cell designs.
Fig. 13. Adjustment of the tradeoff between write (IW ) yield and read
(SNM) yield through PG transistor sizing, for a 6-T SRAM cell implemented
with single-NW GAA MOSFETs with HSi = 7.5 nm.
TABLE III
S UMMARY C OMPARISON OF GAA 6-T SRAM C ELL D ESIGNS
2376
2377
Meng-Hsueh
Chiang
(S97M01SM07)
received the B.S. degree in electrical engineering
from National Cheng Kung University, Tainan,
Taiwan, in 1992, and the M.S. and Ph.D. degrees
in electrical and computer engineering from the
University of Florida, Gainesville, FL, USA, in
1995 and 2001, respectively.
He is a Faculty Member of the Department of
Electrical Engineering at National Cheng Kung
University.