CAREER OBJECTIVE

Seeking a Challenging career as custom Layout Engineer.

TECHNICAL SUMMARY
An Electrical and Electronics engineer having around 9+ years of design experience in
Library development and Analog Layout with strong understanding of CMOS design
concepts and commitment to the work would really contribute to the success in the field of
VLSI design.
Area Of interest
Custom LAYOUT (STD Cell, Memory Cells , Analog, IO )
WORK EXPERINCE

Having 3 years of experience in Standard cell Library Development and 6 years

Analog Layout.
Currently working as Senior Design Engg at Sankalp Semiconductor pvt ltd.
Worked as Senior Layout Design Engg at Infotech Enter Preises Ltd.
Worked as Layout design engineer in Microchip Design India pvt ltd.
Worked as Design Engineer at INSILICA Semiconductor India pvt ltd.
Worked as Design engineer at TATA Elxsi Ltd.

SKILL SET
CAD tools

Cadence,Tanner Tool.

Schematic

S-EDIT

Circuit simulator

T-Spice

Layout

L-Edit, VLE, VXL.

Verification

Assura,Calibre,Hercules.

PROJETS AND EXPERIENCE:

1) Layout design of Frequency Divider block :
Tool

: Cadence VLE & VXL .

Verification : Calibre.
Technology : 28nm.
Project Description :
Worked on Floorplan, Placement and routing with all the constraints
taken care and verification like DRC & LVS and EM are taken care.

2) Layout design of 8GHZ SERDES :

Tool
: VLE, VXL.
Verification : PVS tool.
Technology : 16nm FINFET Process.
Project Description :
Worked on Sub Blocks of SERDES. Floorplan,Placement and Routing.
Performing checks -LVS,DRC,EM&IR drop. Shielding of critical nets.
3) Layout design of Reference top level and Reference buffer Modules :
Tool
: Cadence VLE & VXL .
Verification : Calibre.
Technology :180nm.
Project Description :
Complete lay out design of these modules from scratch includes floorplan and
verification like LVS and DRC taken care.
Worked on toplevel integration of these blocks .
4) Layout design of PAD RING :
Tool
: Cadence VLE & VXL .
Verification : Calibre.
Technology :180nm.
Project Description :
Complete layout design pad ring for 4kv ESD.Which will consist four different
blocks and Integration,Verification. Layout design of all the blocks and integration,
verification of all the blocks DRC and LVS and ESD DRC also done.

5) Layout design of 12bit saradc :

Tool
: VLE, VXL.
Verification : PVS tool.
Technology : 65nm
Project Description:

This module consists of Reference Buffer blocks and switches.Reference blocks

include adc12c_ref1buf and adc12c_ref2buf, adc12c_refout blocks. In these blocks
worked on floor plan and verification of all the blocks, DRC and LVS , EM checks
taken care.
6)

Layout design of Mod Oscilator:

Tool
:VLE, VXL.
Verification : PVS tool.
Technology : 65nm.
Project Description:
This module consists of Bias generator, Comparator and Level shifter blocks. In
these blocks worked on Floor plan and Verification includes DRC & LVS and EM
checks are taken care and worked on a top level integration of all the blocks.

7) Layout design of DCO Module:

Tool
: VLE, VXL.
Verification : PVS tool.
Technology : 65nm.
Project Description:
Which consists of LDO block, gmcell and PTAT gen block, fault logic cell,
Ring oscillators, current mirrors and Level shifters, digital loop, Encoder blocks.
Worked on most of the blocks, includes floor plan and verification like DRC and LVS
are taken care, worked on top level integration and verification.
8) Layout design of Transmiter and Reciever Blocks :
Tool
: Virtuso Layout Editor XL
Verification : Calibre,Hercules,Quartz.
Technology : 32Nm
Project description:
Layout design of some of the blocks in transmiter and reciever, which includes Floorplan

and Verification of all the Blocks, DRC, LVS and EM, Yield Checks were taken care.

9) Layout design of Temperature Voltage Sensor ( TV Sensor) :

Tool
: Virtuso Layout Editor XL
Verification : Calibre, Hercules, Quartz.
Technology : 32Nm
Project description:

TV sensor consists of Comparator, Bias Generator, Integrator, Opamp , Bandgap

Diodes blocks . Design of all the blocks which includes Floorplan and Verification of
all the Blocks , DRC,LVS and EM, Yield Checks were taken care.
Integrating of all the blocks in top level and verification has been taken care.

10) Layout design of LCD_MUX :

Tool
: Virtuso layout Editor,
Verification : Calibre,Hercules.
Technology : 200k, TSMC0.18nm and TSMC0.25nm

Project description:
Consists of Phase Mux and Segment Mux and Comm Mux block. Design of all the
three blocks with DRC, LVS, ANTENNA and EM checks were taken care.
While 200k technology is microchip own technology. lcd_mux contains 48 segment
block and 4 comm block.
In TSMC0.18nm consists 64 segment block and 8 comm block with different current
densities in phase mux.
In TSMC0.25nm lcd_mux is design for deep sleep mode, which is differ from above
two, consists of 25 segment block and 8 comm block and current densities in phase
mux.

11) Layout design of filt_edge_low_pulse rejection :

Tool
: VLE.
Verification : Hercules.
Technology : 200k (microchip own technology)
Project description:
Consists of schmit trigger and pulse one shot ckt. Floor planned and
design the layout and verified Anttena,DRC , LVS by using Hercules tool.

12)

Layout design of Programmable_LVD Module :

Tool
:
Verification :
Technology :

VLE.
Hercules,Calibre.
TSMC 0.18nm

Project description:

Programmable lvd block consists of Decoder and comparator analog switch,resistor

ladder,lvd comparator Floor plan Layout design and verified DRC,LVS by both
Hercules and Calibre tool .
13) Lay Out Design of USB 2.0 ( Reciever Block ) :
Tool
: Virtuso layout Editor .
Verification : Calibre.
Technology : 65nm.
Project description:
Reciever Block consists of Four blocks, like High Speed Data Receiver, Squelch
Ckt, Disconnect Ckt, Single Ended Data Receiver Layout design of all the four
blocks with DRC,LVS ,DFM checks are done by for both twin well and triple
well process using Calibre tool and EM checks are done by tool provided by client.
14) TSMC 12 track HS Standard cell Library Architecture.
Tool
: Cadence. VLE.
DRC
: Assura.
Technology : 65nm, 90nm, 130nm,180nm.
Project description:
Design and development of library architecture for given net list and schematic. Cells
designing verified for DRC and Electric Rules, DFM according to the specification
by Assura DRC tool and Quality analysis also taken care along with designing.
15) TSMC 180nm Metal Programmable Library Architecture:
Tool: Virtuso layout Editor.
DRC: Assura.
Team size: 5
Project description:
The project required completely optimizing and modifying a standard cell library of
about 1000 cells. The cells were of the Metal Programmable cell library architecture
on a TSMC 0.18u process. Tanner L-edit was used to hand craft the cells and improve
design yield and manufacturability. Design goals were achieved within the specified
time frame and cells were sent for post layout simulation.

QUALIFICATION

B.E in Electrical and Electronics.

Advanced training programming in VLSI design.