Semiconductor Devices
Module 3
Page 1
Module 3
In pnp BJT, two p regions are separated by a n region. The structure and symbol of pnp
BJT is shown below:
The emitter region is typically medium in area and heavily doped, base region is small in
area and lightly doped and collector region is large in area and moderately doped.
BJT has two junctions named emitter-base junction and
Question:
collector-base junction. So the device is called bipolar
Part A
junction transistor.
What are the different modes of
Modes of operation:
operation of BJT?
BJT can operate in different modes according to the biasing
of two junctions. They are:
Biasing
Modes of
Emitter-Base Collector-Base Applications
operation
junction
junction
Forward active
Forward bias
Reverse bias
Amplifier
Inverse active
Reverse bias
Forward bias
Attenuator
Forward
Forward bias
Forward bias
Switch
saturation
(VEB > VCB)
Inverse
Forward bias
Forward bias
Switch
saturation
(VEB < VCB)
Cut-off
Reverse bias
Reverse bias
Switch
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Page 2
Module 3
Question:
Part B
Draw the current components in
BJT.
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Module 3
Question:
Part A
Define injection efficiency and
transport factor of a BJT.
=
+
should be minimum.
This can be achieved by keeping the emitter doping concentration maximum with
respect to base doping concentration.
Base transport factor
It defines that how many carriers are transporting from emitter to collector through base. For
pnp, it is the ratio of collector current due to hole to the emitter current due to hole.
It can be expressed as
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Module 3
can be achieved by reducing doping concentration in base and reducing width of base.
Common-base current gain
This is defined as ratio of collector current and emitter
Question:
current, when base is common for other two terminals.
Part A
This current gain may be ac or dc and can be expressed
Define and of a BJT.
as,
dc current gain
We can express
= +
=
Then
---(1)
( )
=
( )
And
---(2)
This shows that for a good transistor, common-base current gain must be close to
unity.
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Module 3
Relationship between common-base current gain, injection efficiency and transport factor
Let M is the multiplication factor in collector-base
Question:
junction during the Avalanche breakdown of reverse
Part B
biasing. Then M is given by
Give the relationship between
basic performance parameters
=
of BJT.
We have
---(3)
---(4)
=
=
---(5)
Using (5)
= ---(6)
This shows that current gain can be improved by increasing injection factor and
transport factor.
Common-emitter current gain
It is defined as the ratio between collector current and base current when emitter is
common for other two terminals. This also has ac and dc current gain.
It can be expressed by
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Page 6
Module 3
---(7)
We have =
Then
= ---(8)
=
Substituting to (9)
= +
= + ( + )
= ---(10)
(Since = + and = + )
Using =
=
=
=
= ---(11)
This shows that, for a good BJT is infinity. In practical it is very high.
and of a BJT can be improved by increasing the emitter injection efficiency and
base transport factor.
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Module 3
Problem:
The following parameters are given for an npn transistor. InE = -5mA, IpE = -0.01mA,
InC = -4.99mA, IpC = -0.001mA. Determine T, , , , IB, IC and IE.
Solution:
For pnp transistor,
=
= .
.
+
+
= + . = .
=
=
=
= .
.
+
.
We have
=
Assume M = 1,
= . . = .
We have
.
=
=
.
For pnp transistor, IE = IpE + InE
Then for npn, IE = InE + IpE = -5 0.01 = -5.01mA
For pnp transistor IC = IpC + ICBO
Then for npn, IC = -(InC + ICBO)
ICBO is given as IpC = -0.001mA
Then IC = ( 4.99 0.001) = +4.991mA
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Module 3
Page 9
Module 3
Question:
Part B
Energy band diagram of BJT
The energy band diagram of pnp BJT
under isolation, equilibrium, forward active
and saturation region are shown below:
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Module 3
Potential distribution in pnp BJT under equilibrium and forward active modes:
Equlibrium
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Module 3
Question:
Part A
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Module 3
= (
Using this,
=
=
=
=
---(1)
---(2)
---(3)
---(4)
The minority carrier distribution in base region is almost linear, because the current flow in
base region during saturation mode is only due to diffusion of carriers, not recombination.
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Module 3
Question:
Part B
Derive expressions for IC, IE
and IB of an pnp BJT
---(2)
=
= , =
Then (2) becomes,
= +
= + ---(3)
And
---(4)
---(6)
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Module 3
= +
=
=
()
(( )
---(7)
(( )
() ) + (
() )
(
+
+ ( ) ()
+
=
)
)
---(8)
=
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---(9)
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Module 3
---(10)
At x = 0,
=
=
---(11)
+
=
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Module 3
---(12)
At x = WB
=
Using (10)
+
=
+
=
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Module 3
---(13)
Similarly
---(14)
---(15)
= +
Using (12) and (14)
---(16)
In general
=
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---(17)
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Module 3
Where
---(18)
---(19)
= +
Using (13) and (15)
()
= ---(21)
Where is forward current gain when emitter-base junction is forward biased and
collector-base junction is reverse biased.
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Module 3
=
DC parameters in terms of physical dimensions:
Consider pnp BJT in forward active mode. Emitter injection efficiency
Then
If WB << Lp,
If WE << LnE,
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Then
And
()
=
Then
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If WB << Lp,
Since
1
1 + 2
2
Then
()
Let M = 1,
=
Using (22) and (23)
+
+
()
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Module 3
And
=
Using (24)
When
and
()
Problem:
1. A Si npn BJT has pB = 1s and pB = 440 cm2/V-s. Determine WB so that the transport
factor is 0.995 at T = 300K. Assume WB << Lp.
Solution:
If WB << Lp base transport factor
We have
=
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= . = . /
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Module 3
. = .
Then
. =
+
.
+
=
.
.
= .
.
= .
.
= . . = .
= .
Collector
1015cm-3
5m
1s
p = 450 cm2/V-s
=
+
=
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= . = . /
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Module 3
=
= . = . /
=
=
= =
= =
.
+
= .
For npn
= . . = .
=
= .
Assume M = 1
= = . . = .
=
.
=
=
.
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Module 3
Question:
Part B
Draw Ebers-Moll model of pnp
BJT and write the Ebers-Moll
equations. Explain the term
involved.
()
()
In general
()
()
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Module 3
= =
Question:
Part B
Derive relationship between ICS
and ICBO
()
Take
()
+ =
= +
()
When IE = 0
=
=
()
Where
=
()
Similarly
()
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Module 3
Problem:
Prove the relations
a) = +
b) = + ( + )
Solution
a) For pnp BJT, we know that = + ()
When
= , =
Then = ()
By definition
i.e
()
From (1), =
Then (3) becomes
= +
Hence proved.
b) We have = + ()
Take = + ()
Substitute (1) to (2)
= + +
= +
= +
=
+
()
We know
= + = +
= + +
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Module 3
Question:
Part B
Plot the minority carrier distribution in pnp BJT in
a) forward active mode b) saturation mode c) cutoff mode e) inverse active mode
Minority carrier distribution of pnp BJT in different operating modes:
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Module 3
Real BJT:
Consider the following non-idealities for a practical BJT:
1. Carrier recombination in emitter-base junction.
2. Drift in base region.
3. Effects of variation of VCB on terminal currents.
4. Avalanche multiplication in collector-base junction.
5. Resistance of the base region.
6. Non-ideal structure.
7. Kirk effect.
Effect due to recombination in emitter-base junction
Considering the recombination in emitter-base junction, the emitter current consists that
component also and is given by
()
Where
+ +
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=
=
=
Module 3
()
()
()
This shows that the built-in electric field is positive directed from emitter to collector.
This electric field helps transport of holes across the base region from emitter to collector
and transit time is reduced.
The reduction in transit time of electron (in npn) or hole (in pnp) is useful for BJT in high
frequency applications.
Effect of bias to collector-base junction (Early effect or base width modulation)
The effective width (WB) of base region is the difference between the total base width
(WB0) and the depletion layer width of collector-base junction into the base region. This
is as shown below:
Then
()
We know that
Substituting to (1)
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Module 3
()
+
Question:
This shows that the effective width of base region decreases
Part A
with increase in reverse-bias on the collector-base junction. What is base width
This effect is called base width modulation or Early effect.
modulation? (April
Due to Early effect, reverse bias of collector-base junction
2014)
increases IC and IE increases.
Increase in VCB, decreases WB and which increase the slope of minority carrier
distribution in base region. Increase in slope results increase in IpE and IpC.
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Module 3
+
+
+ =
, then
Typically
+
=
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Module 3
=
()
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Module 3
Problem:
Question:
Part B
+
+
+ =
= .
= .
+
=
.
. .
= . . = .
Resistance of base region and emitter crowding
In real structure of BJT base region has large in area comparing to emitter and the
resistance of base is distributed over this region. This is shown below:
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Module 3
Here the input current is IE (+ve), input voltage is VEB (+ve), output current is IC (-ve) and
output voltage is VCB (-ve).
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Module 3
Question:
Part B
Plot the input and output
characteristics of a pnp
transistor in common-base
configuration and explain?
Marks different operating
regions.
Question:
Part A
The shape of this characteristic is similar to pn junction diode, but increasing reverse bias
VCB shifts the characteristics to left side.
When VCB increases, reduce base width cause an increase in IE. i.e is the reason for shift
of the curve to left.
This shift is also the consequence of Early effect.
Output characteristics of CB configuration
It is the plot of output current IC as a function of output voltage VCB with input current IE
held constant.
Consider the equation
= +
= +
()
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Module 3
= ()
IC is constant.
When IE > 0, and VCB 0,
= ()
= +
=
=
=
()
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Module 3
Question:
Part A
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Module 3
CE configuration:
The circuit arrangement of pnp BJT in
configuration is shown below:
CE
Question:
Part B
Explain the
characteristics of
transistor in CE
configuration. (April
2014)
Here the input current IB (-ve), input voltage VBE (-ve), output current IC (-ve) and output
voltage VCE (-ve).
Input characteristics of CE configuration
It is the plot of input current IB as a function of input voltage VBE with output voltage VCE
held constant.
Consider Ebers-Moll equations,
=
=
= +
()
+ +
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Module 3
The shape of the characteristics is similar to pn junction diode, but if VCE increases
reverse bias, the curve shift to right side.
When VCE increases vely, VCB also increases vely and collector-base junction becomes
more reverse biased. This results base width modulation and causes increase in T, then
base current IB decreases for a given VBE.
Due to this the curve shifts right side when VCE increases vely.
Output characteristics of CE configuration
It is the plot of output current IC as a function of output voltage VCE with input current IB
held constant.
We have VCE = VCB + VBE,
VBE = VCE VCB
When VCE = 0, VCB = VBE = VEB
i.e collector-base and emitter-base junctions are equally biased. Under this condition, the
injection of carrier from both junctions are equal and there is no current flow in collector
and IC = 0.
When VCE increases vely, VCB also increase vely cause an increase in collector current
IC. Further increase in VCE cause Early effect results an increase in IC for a given IB. Here
IC is not constant like CB due to the Early effect.
IB can be increased by increasing VBE. Increasing IB reduce the resistance between
collector and emitter cause more injection of carrier into base. This results an increase in
IC.
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Page 41
Module 3
= + +
When IB = 0, i.e.
= +
For IB = 0, VBE 0, therefore VEB 0 (emitter-base junction reverse biased) and VCE 0,
VCB = VCE - VBE
VCB = VCE + VEB 0 (collector-base junction reverse biased).
This region is labeled as cutoff region. Here |IC| = ICEO.
For IB < 0, VBE < 0, therefore VEB > 0 (emitter-base junction forward biased) and if VCE
varies from 0 to -VBE, VCB will be VBE to 0 (collector-base junction forward biased). This
region is labeled as saturation region. Here IC increases linearly with increase in VCE.
For IB < 0, VBE < 0, therefore VEB > 0 (emitter-base junction forward biased) and if VCE <
-VBE, VCB < 0 (collector-base junction reverse biased). This region is labeled as active
region. Here |IC| IB.
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Module 3
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Module 3
Question:
Part A
Explain the fabrication of JFET.
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Module 3
It consists of a lightly doped n-region sandwiched between two p+ regions. The middle n
region is called channel of the JFET and the p+ regions form gate. (In case of p-channel
JFET, p-channel and n+ gates are there.)
One end of the channel is designated as source (S) and other end as drain (D). These are
interchangeable terminals. For n-channel JFET, terminal to which higher potential is
applied acts as drain.
The drain collects the charge carriers emitted from the source through the channel.
The gate (G) terminal controls the flow of current through the channel.
The symbol of FET is:
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Module 3
Question:
Part B
Explain the working of
an n-channel JFET.
(October 2014)
Let the channel thickness is 2a, channel width Z, channel length L, W0 depletion layer
width of gate to channel junction on both side under thermal equilibrium and Nd doping
concentration of channel.
The resistance of the channel with no bias (VGS = 0,
Question:
VDS = 0) or under equilibrium is given by
Part B
Derive
expression
for
=
=
()
= ()
Area of cross section of the channel
= ()
Substituting (3) and (2) into (1)
=
()
=
()
()
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Module 3
When reverse bias on the gate increase, depletion layer extends more into the channel.
Then effective channel thickness and channel cross section area reduces, cause decrease
in channel conductance.
Changing conductance of channel by gate voltage is called conductance modulation.
When a drain to source voltage VDS is applied, the drift current through the channel ID
and is governed by Ohms law. i.e =
The channel resistance R can be controlled by gate voltage VGS. It also changes according
to VDS.
Drain characteristics of JFET:
It is the plot of drain current ID as a function of drain to
Question:
source voltage VDS keeping gate to source voltage VGS
constant.
Part B
Case 1: If VGS = 0, VDS = 0, R = R0 and ID = 0
Draw and explain the
drain characteristics of
an n-channel JFET.
(April 2014)
Hint: Answer each case and
draw drain characteristics.
Dont answer pinch-off voltage
derivation.
Case 2: If VGS = 0, 0 < VDS < V0, for small VDS change in R is negligible, so it is almost
close to R0. Then ID increase linearly with increase in VDS. This portion of drain
characteristics is called linear region or ohmic region. This is shown below:
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Module 3
Case 3: If VGS = 0, V0 < VDS < VD(sat), as VDS increases voltage drop in the channel
gradually increase from source to drain. Also the reverse bias between gate and channel
gradually increases from source end to drain end. Then the depletion layer width also
gradually increases from source end to drain end. This increase R of the channel. When
channel resistance increase with VDS, the slope of the characteristics decreases and the
situation is shown below:
Then = +
At pinch-off, VDS = VD(sat) + V0, VDG = Vp, then
() + = +
= () + ()
But Vp is independent of VDS or VGS.
At pinch-off the depletion width equals half width of
channel. i.e. W = a. Then
Question:
Part A
Define a) pinch-off voltage b)
saturation voltage of JFET.
Question:
Part A
Write the expression for pinchoff voltage interms of a) doping
concentration and channel
thickness b) saturation voltage
and gate to source voltage
Since Vp >> Vo
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Page 48
Module 3
=
()
This shows that the pinch-off voltage is unique for a given JFET and is depends on the
channel doping and channel width. If doping concentration or channel width increases
pinch-off voltage increases.
At pinch-off, ID becomes constant and is denoted as ID(sat) as shown below:
Case 5: If VGS = 0, VDS > VD(sat) , more portion of channel width becomes pinch-off and
current flow in longitudinal direction and remain constant. This is shown below:
Case 6: If VGS = 0, VDS is higher value, the reverse biased gate channel junction
breakdown due to Avalanche multiplication. Then ID increases uncontrollable.
The drain characteristics for VGS = 0 is shown below:
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Module 3
Case 7: If VGS < 0 (increases reverse bias), increase depletion width and channel
resistance. This reduces the slope of the characteristics in ohmic region. This also reduces
VD(sat) and ID(sat). With increase in VDS and VGS (reverse bias), Avalanche breakdown
occurs also decrease. Then the complete drain characteristics of JFET is shown below:
From this characteristics, an important parameter for JFET is dynamic drain resistance rD
and is given by
()
The value of VGS at which channel gets completely depleted is called cut-off voltage or
threshold voltage Vth of JFET.
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Module 3
The drain current is maximum when VGS = 0 due to minimum channel resistance and
it reduces to zero when VGS = VGS(cut-off), where VGS(cut-off) is given by
() =
()
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Module 3
Consider the cross sectional view of JFET with direction current and variation of
depletion layer along the channel.
= ()
Where A(x) is area of cross section of the channel at distance x, is the channel
= ()
Depletion width in the channel along x-axis,
+ + ()
+ ()
=
Then
+ ()
()
= ()
Electric field
()
()
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Module 3
()
+ ()
()
+ ()
= =
+ ()
()
+ ()
()
+ ()
+ ()
()
()
+ ()
()
+ ()
()
+ ()
()
+ ()
()
(Neglecting W0 in G0)
Page 53
+ ()
()
+ ()
()
=
=
Module 3
()
= ()
Drain current at saturation, ID(sat):
It is the drain current at VDS = VD(sat), and is given by
() = +
Question:
Part A
Express the equation for a) Vth )
b) ID(sat) c) Channel conductance
d) Transconductance.
()
Where
= () +
Channel conductance, gD:
It can define as
()
It is given by
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Module 3
()
()
Transconductance, gm:
It can define as
()
=
=
+ ()
+ +
()
It is given as
()
(4) and (6) are identical, i.e. gD = gm or gD in linear region is same as gm in saturation
region (below pinch-off region).
() =
Where IDSS is short-circuit drain saturation current, i.e. saturation current with VGS = 0
Page 55
Module 3
Problem:
An n-channel Si JFET at 300K has width Z = 1mm, channel thickness on one side a = 1m,
channel length L = 25m, channel doping Nd = 1016 cm-3 and the gate doping is 1019cm-3.
Determine: a) contact potential b) pinch-off voltage c) current at VGS = - 2 V, VDS = 3V and
d) saturation current at VGS = -2V using theoretical and approximate expressions. Take n =
1100cm2/V-s.
Solution:
a)
b)
= .
.
..
= .
= .
.
=
=
= .
= . .
.
.
. ()
= .
d) () = + +
= . . . . + .
.+
.
= .
Approximate value
() =
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Module 3
.
= . . . . + .
.
= .
() = .
+
= .
.
Real JFET:
The characteristics of real JFET are:
1. Channel length modulation: Ideally drain current is
Question:
constant after pinch-off, but really it increases slightly
Part A
with VDS after pinch-off.
What is meant by channel
The effective length of channel decreases after pinch- length modulation in JFET?
off, then the channel conductance G0 increases. This
shows that conductance of channel is modulated by the variation in effective length
by VDS. This is called channel length modulation. Due to this ID increases with
increase in VDS after pinch-off.
2. High field effects: The electric field along the channel is very high, if the channel is
short. The velocity of electron at high electric field has saturation, then mobility of
electron decreases with increase in electric field. Then there is a reduction in
conductance of the channel and ID for a given VDS.
3. Breakdown: In JFET, gate channel junction is always reverse biased. Then for large
values of VDS may cause Avalanche breakdown of the junction. For more ve values
of VGS, the breakdown occurs at the smaller values of VDS.
4. Temperature effects: With increase in temperature the
Question:
mobility of carriers decreases due to increase in
Part A
scattering by lattice vibration. This leads to reduction in
What is the effect of increase in
ID with rise in temperature.
temperature on JFET drain
current?
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Module 3
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The change in carrier concentration near the interface causes a bending of energy band at
the interface. Then the energy band diagram of MOS capacitor under VG < 0 (called
accumulation) is as shown below:
The semiconductor outside the accumulation region remains neutral. When VG increases
vely, the Fermi-level on the semiconductor side shifts downward by qVG.
Under this condition, the effective capacitance of MOS capacitor is the series
combination of oxide capacitance and capacitance of accumulation layer.
The accumulation layer is very thin, so its capacitance is very high, then the effective
capacitance is same as Cox.
Case 2 (VG > 0, or depletion):
When a small +ve voltage is applied to the metal with respect to semiconductor (V G > 0),
-ve charges are introduced in p-type semiconductor,
The ve charges moves towards metal-semiconductor interface and they recombine with
holes. Then depletion layer formed near the interface.
The energy band diagram for this bias voltage is shown below:
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Module 3
Where Eib is intrinsic level in the bulk semiconductor and Eis is intrinsic level at the
surface of interface.
Case 3 (VG >> 0 or inversion) :
When VG is increased to high value, Fermi-level on the semiconductor move upside and
band bends downside. Then the Fermi-level at the interface lies above the intrinsic level.
This result inversion of interface surface and is called inversion.
The inversion of surface is due to the attraction of electrons towards the surface, and the
concentration of electrons near the interface becomes more than hole.
Then the thin region in which electron concentration exceeds hole concentration is called
inversion layer. This is shown below:
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Once inversion occurs, further increase in VG cause only increase in inversion layer
charge.
The thickness of inversion layer is very small compared to W.
The total charge in the semiconductor under this condition is given by
= +
=
Where is charge per unit area of electrons in the inversion layer, Wm maximum
width of depletion layer and QDm is maximum value of the charge per unit area of
depletion layer.
Further increase in VG cause the intrinsic level at the interface surface goes below the
Fermi-level by an amount equal to or above of the Fermi-level at the bulk semiconductor.
Then electron concentration at the interface surface become equal to hole concentration
in the bulk. This is called strong inversion. This is shown below:
Fermi-potential is defined by
= ()
=
or
= ()
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Page 62
Module 3
From (2), =
Substituting into (3)
= + ()
From (1), =
Then (4) becomes
= +
= +
=
= ()
This shows that under strong inversion, surface potential is twice of Fermi potential. And
highly concentration of electrons is present in the surface.
Relation of charge densities:
We have carrier concentration under equilibrium,
=
=
Here hole concentration
=
= ()
Where Fermi potential
()
=
()
= ( )( )
= ( )+( )
Then
= +
=
= ()
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Page 63
Module 3
and increase in
electron concentration. When = , = . At
this point inversion starts and when > , electron
Increasing VG causes increase in
At strong inversion
= ,
=
Question:
Part A
What is the value of surface
potential of a MOS capacitor
under a) at the inversion b)
strong inversion?
i.e minority carrier concentration at the interface is same as majority carrier concentration
in the bulk semiconductor.
After strong inversion, a small increase in VG causes only a large increase in nS only, not
in W.
= + ()
()
We have =
Then (1) becomes
+ ()
+
=
+
()
=
=
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( )
=
()
Page 64
Module 3
()
=
+
=
+
=
()
+
This shows that oxide capacitance and semiconductor capacitance are in series. C ox is
always constant and Cs is dependent on bias.
At accumulation (VG < 0), C = CG and at depletion (0 < VG
Question:
< Vth), CS = CD. CD decreases with increase in VG due to
Part B
increase in depletion width.
At strong inversion, depletion width remains constant and Draw and explain the
C-V characteristics of
CS will constant.
The equivalent capacitance of MOS devices is shown an ideal MOS
below:
capacitor. (October
2014)
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Module 3
If capacitance is measured at high frequency signal, the inversion layer didnt respond
with the gate voltage. The Cs effect is negligible and CD is effective. When VG < 0
(accumulation), C = Cox and is constant. When VG > 0 (depletion), CD decreases and
C CD and varies with VG. When VG >> 0 (inversion and strong inversion), CD goes to
minimum and constant, since depletion width is also constant. Then C = Cmin.
At low frequency, depletion layer width is almost constant and CD is negligible. The net
capacitance is decided by inversion layer capacitance CS and Cox. When VG < 0
(accumulation), C = Cox and is constant. When VG > 0 (depletion), Cs decreases and
C CS and varies with VG. When VG >> 0 (inversion and strong inversion), CS goes to
high and is more than Cox, then C = Cox.
Question:
Part B
Define threshold voltage of
ideal MOS capacitor.
= +
=
+
At inversion,
= =
=
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Module 3
=
Then
= ()
Substituting (2) to (1)
+ ()
This shows that threshold voltage of MOS devices is inversely proportional to oxide
capacitance.
Problems:
1. For a MOS capacitor formed on p-type Si substrate doped with Na = 5x1016cm-3,
determine the surface potential required to make the surface: a) intrinsic b) at strong
inversion.
Solution:
a) At inversion (intrinsic), =
= .
= .
b) At strong inversion =
= . = .
= .
= .
.
Department of ECE, VKCET
Page 67
Module 3
. .
=
=
=
= . /
. . . .
.
+ .
= .
a) Given VG > Vth, then strong inversion occurs.
b) At strong inversion = = . = .
= +
= = . = .
Real MOS systems:
Real MOS devices have:
1. Work function difference of metal and semiconductor
2. Oxide and interface charges
3. Change in Vth due to the different work functions.
Question:
Part B
What are the non-idealities in a
real MOS capacitor? How do
they change flat band voltage
and threshold voltage?
Question:
that of semiconductor. Therefore at equilibrium, there is a
Part A
bend in conduction bands of interface at equilibrium. So to What is meant by flat band
obtain flat band a negative voltage must be applied at VG voltage?
and is referred as flat band voltage VFB.
There will be lot of charges in oxide layer and will affect oxide-semiconductor interface.
Different charges are:
1. Ionic charges Presence of Alkali ions like Na+ shifts
Question:
the threshold voltage.
Part A
2. Fixed oxide charges These charges located in oxide
What are the different charges
as a sheet of +ve charge near Si-SiO2 interface.
present in the oxide? How do
3. Interface charges These charges present in Si-SiO2 they affect the threshold of
interface due to the sudden termination of MOS system?
semiconductor at the interface.
4. Trapped charges Oxide may contain trapped charges within the defects present in
the oxide.
Due to the flat band voltage, the modified threshold voltage is given by
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