Leakage
Drain floating
Drain connected to
source
Leakage
current
Pass 0
Pass 1
For the pMOS device, the 1 on the gate should leave the drain floating. In that situation again, a nArange current called leakage current may flow between source and drai.
Page 1/13
Leakage
Leakage current
Figure 3: The low leakage MOS symbol (left) and the high speed MOS symbol (right)
Page 2/13
Leakage
Ion=550A
Ion=800A
Fig. 4: The low leakage MOS offers a low Ioff current (1nA) but a reduced Ion current (550A)
as compared to the high speed MOS, in 0.12m technology [Sicard2005a]
In figure 4, the low leakage MOS device (left side) has an Ioff current reduced nearly by a factor 100,
thanks to a higher threshold voltage (0.4V rather than 0.3V) and larger effective channel length
(120nm) compared to the high speed MOS (100nm, see figure 5). By default, the MOS device is in
low leakage option, to encourage low power design. The Ion difference is around 30%. This means
that an high speed MOS device is 30% faster than the low leakage MOS. Its use is justified in circuits
where speed is critical.
20
gate
oxide
N+
diffusion
High substrate
doping
Effective channel
0.10m
20
gate
oxide
N+
diffusion
Low substrate
doping
Effective channel
0.12m
Low leakage MOS
Fig. 5: Process section of the high speed (left) and low leakage (right) MOS devices
High speed MOS devices may be found in clock trees, data bus interfaces, central processing units,
while low leakage MOS are used whenever possible, for all nodes where a maximum switching speed
is not mandatory.
Page 3/13
Leakage
Ids = 0
Ioff Modelling using LEVEL3
In sub-threshold mode (gate voltage less than the threshold voltage VTO), an exponential dependence
of the current with Vgs is introduced by using the equation 1. See [Weste] for a detailed analysis of
MOS LEVEL3. Notice the temperature effect introduced in the denominator nkT. Without any voltage
applied to the gate, the current is not equal to zero. The current of Ids for Vgs=0 is called the Ioff
current (Figure 6). Its value in 0.12m is around 10-10 A. In contrast, for Vgs=VDD, the maximum
current Ion is of the order of several mA (10-3 A).
Ids = Ids(Von,Vds)exp(
q(Vgs - Von)
)
nkT
(Equ. 1)
Ids (log)
10-3
-5
10
Subthreshold
(Vgs<VTO)
Von
model 3,
BSIM do this
Above threshold
(Vgs>VTO)
10-7
10-9
Ion
Vgs
Ioff
VTO
VDD
Figure 6: An exponential law is introduced to the MOS device model to account for the subthreshold behavior of the current
Page 4/13
Substhreshold factor
Leakage
(Vgs Vth)
)
n.vt
) (Equ. 2)
Vgst eff = max( VOFF,
(Vgs Vth)
1 + n.exp(
)
n.vt
n = 1 + NFACTOR
(Equ. 3)
n.vt.ln(1 + exp(
A specific parameter VOFF is introduced to account for a specific effect appearing in short-channel
device when Vgs is negative. Conventional models predict that the current decrease with an
exponential law down to zero with decreasing Vgs. For Vgs<0, Ids is supposed to be 0. In
Microwind31, both VOFF and NFACTOR are user-accessible.
Ids (Log)
Measurements
10-3
Ids below
VTO
10-6
With VOFF,
current keeps
above a limit
10-9
VOFF
VTO
Vgs
Figure 7: Illustration of the subthreshold current for Vgs below the threshold voltage VTO
In real-case measurements, Ids stops decreasing near zero Vgs, and then tends to increase with
negative Vgs (Figure 7). This effect is called gate-induced drain leakage (GIDL). Consequently, the
leakage current Ioff can be significant when Vgs is negative (Quite frequent in logic cells). The VOFF
parameter stops the Ids at a certain value, a simplified version of the BSIM4 modeling of the so-called
gate-induced leakage current (More info may be found in [Liu]).
Page 5/13
Leakage
NFACTOR acts on
the slope
VOFF
Description
Name in RUL
file
B4NFACTOR
B4VOFF
Page 6/13
Leakage
Traditionnal
process
10-3
10-4
10-5
Metal-gate
process
10-6
10-7
Ioff current
decrease
10-8
10-9
10-10
0.0
0.5
1.0
NMOS
Low leakage
40
35
0.20
0.9
7
NMOS
High speed
40
30
0.18
1.2
200
Table 2: nMOS parameters featured in the CMOS 45-nm technology provided in Microwind31
The device I/V characteristics of the low-leakage and high-speed MOS in 45-nm technology devices
are obtained using the MOS model BSIM4 (See [Sicard2005a] for more information about this
model). Concerning the low-leakage MOS, the I/V characteristics reported in Fig. 10 demonstrate a
drive current capability of around 0.9 mA/m for W=1.0m at a voltage supply of 1.0 V. For the high
Page 7/13
Leakage
speed MOS, the effective channel length is slightly reduced as well as the threshold voltage, to achieve
a drive current around 1.2 mA/m.
High-speed Ion
Imax=0.9 mA
Low-leakage Ion
Figure 10: Id/Vd characteristics of the low leakage and high speed nMOS devices
Id/Vg for Vb=0, Vds=1 V
Ioff=7 nA
Vt=0.2 V
Ioff=200 nA
Vt=0.2 V
Figure 11: Id/Vg characteristics (log scale) of the low leakage and high-speed nMOS devices
The drawback of the high-speed MOS current drive is the leakage current which rises from 7 nA/m
(low leakage) to 200 nA/m (high speed), as seen in the Id/Vg curve at the X axis location
corresponding to Vg= 0 V (Fig. 11-b).
Temperature effects
Note that in the sub-threshold region, the impact of temperature is extremely important, as
demonstrated in figure 12. At low temperature the current Ids decreased rapidly down to 10nA,
corresponding to a small off leakage current. In contrast, at high temperature, not only the threshold
voltage is reduced but the sub-threshold slope is flattened, which means an exponential increase of the
Ioff leakage current (figure 12).
Page 8/13
Leakage
100C
27C
-20C
Page 9/13
Leakage
Figure 13: The schematic diagram and layout of the ring oscillator used to compare the analog performances in
high speed and low leakage mode (INV5Enable.MSK)
Page 10/13
Leakage
Reduced
consumption
(100 A max)
Strong consumption
(170 A max)
Low standby
current
High standby
current
Fast oscillation
(37 GHz)
Slower
oscillation
(28 GHz)
Figure 14: Simulation of the ring oscillator in high speed mode (left) and low leakage mode (right). The
oscillating frequency is faster in the case of high-speed mode but the standby current is high (Inv5Enable.MSK)
The tick in front of "Scale I in log" must be asserted to display the current in logarithmic scale. The
option layer which surrounds all the oscillator devices is set to high speed mode first by a double click
inside that box, and by selecting high speed (Fig. 14). The analog performances of both options are
summarized in Fig. 14. In the high speed mode, the circuit works fast (37 GHz) but consumes a
significant standby current when off (around 200 nA).
(1) Double click in
the option box
Figure 15: Changing the MOS option into low leakage mode
Once the option layer is set to low leakage (Fig. 15), the simulation is performed again. The lowleakage mode features a little slower oscillation (29 GHz that is approximately a 30 % speed
reduction) and more than one decade less standby current when off (5 nA). In summary, low leakage
MOS devices should be used as default devices whenever possible. High speed MOS should be used
only when switching speed is critical.
Page 11/13
Leakage
Mos Level3
The parameter l3nss may be changed to modify the subthreshold slope and therefore the Ioff current.
PARAMETER
KEYWORD
DEFINITION
NSS
l3nss
Sub-threshold factor
In the RUL file, the parameters l3nss in the NMOS section and l3nss in the PMOS section may be
modified. The following NSS values are provided for CMOS 45-nm technology.
* Nmos Model 3 parameters
*
NMOS
l3vto = 0.34
l3nss = 0.045
*
* Pmos Model 3
*
PMOS
l3vto = -0.32
l3nss = 0.045
Mos BSMI4
The parameters Nfactor and Voff may be changed to modify the sub threshold slope and minimum
value, with direct impact on the Ioff current.
Parameter Keyword
Description
NFACTOR B4nf
VOFF
b4voff
NMOS
value in
0.12m
1
PMOS
value in
0.12m
1
-0.08V
-0.08V
In the RUL file, the parameters b4nfact and b4voff in the NMOS and PMOS sections may
be modified. The following b4nfact and b4voff values are provided for CMOS 45-nm
technology.
* BSIM4 parameters
*
NMOS
Page 12/13
Leakage
b4vtho = 0.35
b4nfact = 1.02
b4voff = 0.01
*
PMOS
b4vtho = 0.36
b4nfact = 1.05
b4voff = 0.01
7. Conclusions
This application note has detailed the leakage current effect and its modeling, with illustration of the
MOS options, the different available models in Microwind31 and one illustration in the case of a ring
oscillator.
References
[Bsim4] BSIM4 web site www-device.eecs.berkeley.edu
[Weste] N. Weste, K. Eshraghian "Principles of CMOS VLSI design", Addison Wesley, ISBN 0-20153376-6, 1993
[Liu] W. Liu "Mosfet Models for SPICE simulation including Bsim3v3 and BSIM4", Wiley & Sons,
2001, ISBN 0-471-39697-4
[Sicard2005a] E. Sicard, S. Ben Dhia Basic CMOS cell design, McGraw Hill India, 450 pages,
ISBN 0-07-0599335, June 2005, international edition 2007.
[Sicard2005b] E. Sicard Introducing 90-nm technology in Microwind3, application note, July 2005,
www.microwind.org
[Sicard2006a] E. Sicard Microwind Users Manual, lite version 3.1, www.microwind.org, INSA
editor, 2006
[Sicard2006b] E. Sicard Introducing 65-nm technology in Microwind3, application note, July 2006,
www.microwind.org
[Sicard2007] E. Sicard Introducing 45-nm technology in Microwind3, application note, July 2007,
www.microwind.org
Page 13/13