International Journal of Advanced Computing and Communication Systems (IJACCS)

vol.1 Issue.1 March 2014. ISSN: 2347 9299 / 2347 9280

Fault Classification in Analog Circuits Using Evolutionary Algorithms

V.Gomathy,
Research Scholar, EEE Dept,
PSG College of Technology,
Coimbatore, Tamilnadu, India.
gomathyvelmayil@gmail.com
ABSTRACT
Testing of analog electronic circuits for faults has
been challenging due to a myriad of problems such as
unpredictable variation in component tolerance, non-linearity
and lack of mathematical fault models. The fault testing
procedure can rather be performed using artificial intelligence
techniques though, for they are better than mathematical
models and automate the testing process altogether. The
project proposed seeks to automate fault testing procedure
using support vector machines (SVM) based classifier, a
widely successful AI model. Consequently, an SVM-based
classifier is built and trained for the circuit under test (CUT),
which can then on its own autonomy pronounce whether a
newly projected state of the circuit is faulty or not. Primarily,
the distinguishing features of the many faults that can arise in
the CUT are assessed. For these specific features, data
corresponding to the several faulty operational states are
extracted, here, in P-SPICE software suite using Monte-Carlo
technique. Later, three ensemble of SVMs, each of the
following strategies Directed-Acyclic-Graph, Voting and
Cascading are built and trained that can now accomplish the
classification. The performance of the classifiers thus created
is analyzed for two sample circuits, namely, Sallen-Key Band
Pass Filter and High Pass Filter and the results are
summarized.

Dr.S.Sumathi
Associate Professor, EEE Dept,
PSG College of Technology,
Coimbatore, India.
ssi@eee.psgtech.edu
The NN can learn the samples itself according to some
training rules and after a training stage it can predict a
sample which does not belong to the training samples. Up to
now, the back-propagation neural network (BPNN) was the
most popular classifier in the analog diagnosis domain, but it
faces some difficulties like easy entrapment into the local
minima during the training stage, long training time to
convergence and also ANN is sensitive to the data
dimension of the training samples. High-dimensional data
always results in a long training time, and sometimes,
failure to converge. Hence we go for support vector classifier,
which is characterized by fast convergence to the global
optimization, excellent generalization capability and immunity
to high-dimensional data.

LITERATURE SURVEY
Literature survey plays a key role in successful
implementation of the project. The papers that provided
better understanding of the problem and solutions and aided
comparison and analysis of results are briefed.
Significant research on analog fault diagnosis at the
system, board, and chip level begin in 1975 when Winston,
Hunt and Butchler modeled fault diagnosis as pattern
recognition problem [1]. A survey of the research conducted
in this area clearly indicates that analog fault diagnosis is
complicated due to the poor fault models, component
Keywords Support Vector Machine; Monte-Carlo Technique; tolerances, and non-linearity issues. These difficulties made
Directed-Acyclic-Graph Strategy; Voting Strategy; Cascading the application of neural networks to these problems very
Strategy.
appealing.
In the past several years, some researchers have
IINTRODUCTION
begun to use the SVC to perform the analog circuit
A fault in analog circuit is defined as any kind of diagnosis task. In 1998, Vapnik introduced support vector
malfunction in the system that leads to degradation in the machine for classification [2]. The frequently used SVC is
overall system performance. Fault analysis in analog based on the structure of so-called one-against-one or the
circuits includes three basic objectives: fault detection, fault one-against-rest that was introduced by him.
localization and fault classification. Fault detection determines In 2009, Grzechca, D., Rutkowski, J. employed a multi-class
whether given circuit is faulty or fault-free. Fault SVC which has a one-against-rest structure to perform fault
localization is aimed at identifying which component is faulty. classification task [7]. This was basic attempt to obtain
Fault classification determines what type of fault has occurred multiclass SVM from binary SVM. They used Gaussian kernel
in the circuit. The methods of fault analysis in analog circuits function. They provided better results compared to neural
are basically classified into two types which are mathematical network. The basic idea of designing multi-class SVC from
approach and artificial intelligence approach. Mathematical binary SVC is taken from this paper.
approaches are infeasible for large circuits and also difficult to
In 2011, Jiang Cui, Youren Wang proposed different
automate. Hence artificial intelligence approach is preferred architecture of SVC based on analysis of number of
generally. In the past decades, the Neural Networks (NNs) informative fault decision functions [6]. Their objective was to
based methods has been applauded by researchers in make it easy to classify repeatable faults. This improved
diagnosing analog linear circuits or even nonlinear circuits.
accuracy and reduced testing and training time. They
implemented this algorithm in linear and non linear circuits
and extended it to actual circuits. They used wavelet packet
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International Journal of Advanced Computing and Communication Systems (IJACCS)

vol.1 Issue.1 March 2014. ISSN: 2347 9299 / 2347 9280

decomposition for feature extraction. They used Haar

wavelet at level 5 decomposition. Kernel function used was
polynomial kernel function and radial basis function (RBF)
kernel function. The concept of effective classification of
faults that falls in unclassifiable region and rejected region is
taken from this paper.
OBJECTIVE OF THE PROJECT
The aim of the project is to develop a system that
diagnoses circuit faults that occur due to unforeseen
tolerance variation of the various components of the circuit.
The system relates the faulty state of the circuit to the
component that caused the fault and provides insight upon
that part of the circuit that needs repair. The project is
executed in two phases. The first phase is to simulate a
sample circuit and perform Monte Carlo analysis. Monte Carlo
analysis vows to represent the real world condition of
unforeseen variation in tolerance range specified for
individual components. The resulting output of the circuit for
such variations is distorted and incorrect. The second phase
takes up the recorded values of the circuit output, obtained
for tolerance violations, and this information is used to train
the Support Vector Classifier ensemble to identify faults. They
are each of Directed-Acyclic-Graph, Cascading, and Voting
architectures, each apt for different testing scenarios.
PROPOSED SYSTEM
The proposed technique of fault analysis shown
in Fig.1 includes two basic steps. First step is to simulate the
circuit and run monte-carlo simulation to generate fault
dictionary. Second step is support vector machine based
classification.

a)High-Pass Filter: It is considered for a central frequency

of 7.96 kHz. The implementation is shown in Fig. 2. It is made
up of four resistors, two capacitors, voltage source and an
op-amp. Two nodes 1 and 2 are of particular interest. At
these nodes, voltage and power dissipated are found out.

Fig.2 High-Pass filter schematic

There are eleven fault classes considered in total.
They are R1 High, R1 Low, R2 High, R2 Low, R3 High, R3 Low,
R4 High, R4 Low, C2 High, C2 Low, and Normal Circuit. The
high and low values mentioned state that the components
specified are 20% above or below their nominal values,
correspondingly. For each of these fault classes, voltage and
power values at nodes 1 and 2 are recorded. To arrive at
more than one sample for each fault class, Monte-Carlo
simulation is to be done.
b) Sallen-Key Band Pass Filter: It is considered for a central
frequency of 24.5 kHz.

Fig.3 Band-Pass filter schematic

Fig.1 Block diagram of the proposed system
A. INPUT CIRCUIT
The input circuits taken are standard Sallen-Key
Band Pass Filter and High Pass Filter. They both are linear
circuits that are generally used for fault analysis. The faults
considered are basically soft faults. The circuit designed is
simulated in PSPICE to check its correct functionality under
normal condition. Below are the parameters of the two
circuits, their schematic and other relevant information.

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Node Vout is of particular interest, voltage

dissipated is found out at this node is given in Fig. 3. There
are five fault classes considered in total. They are R3 High, R3
Low, C1 High, C1 Low, and Normal Circuit. The high and
low values mentioned state that the components specified are
20% above or below their nominal values, correspondingly.
For each of these fault classes, voltage and power values at
node Vout are recorded. To arrive at more than one sample
for each fault class, Monte-Carlo simulation is to be done.

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International Journal of Advanced Computing and Communication Systems (IJACCS)

vol.1 Issue.1 March 2014. ISSN: 2347 9299 / 2347 9280

B. MONTE-CARLO ANALYSIS
Monte Carlo Methods (or Monte Carlo experiments)
are a broad class of computational algorithms that rely on
repeated random sampling to obtain numerical results, that is,
by running simulations many times over in order to calculate
those same probabilities heuristically just like actually playing
and recording the results in a real casino situation, hence
the name. They are often used in physical and mathematical
problems and are most suited to be applied when it is
impossible to obtain a closed-form expression or infeasible to
apply a deterministic algorithm. Monte Carlo methods are
mainly used in three distinct problems:
optimization,
numerical integration and generation of samples from a
probability distribution.
Monte Carlo methods are especially useful for
simulating systems with many coupled degrees of freedom,
such as fluids, disordered materials, strongly coupled solids,
and cellular structures. They are used to model phenomena
with significant uncertainty in inputs, such as the
calculation of risk in business. They are widely used in
mathematics, for example to evaluate multi-dimensional
definite integrals with complicated boundary conditions.
When Monte Carlo simulations have been applied in space
exploration and oil exploration, their predictions of failures,
cost overruns and schedule overruns are routinely better than
human intuition or alternative "soft" methods.
Random adjustment of the parameters by a
computer simulation program within the worst case limits
produces a statistical result through Monte Carlo analysis. It
throws light on the probability of a circuit output
characteristic belonging to a given range and includes
determining the probability of a negative design margin.
Monte Carlo analysis results are commonly shown in the form
of a histogram. This can also be extracted to excel sheet or
notepad for further processing.
Monte Carlo methods vary, but tend to follow a
particular pattern:

Define a domain of possible inputs.

Generate inputs randomly from a probability

distribution over the domain.

Perform a deterministic computation on the inputs.

Aggregate the results.

Fig.4 DAG SVM schematic

As seen from the structure of the DAG classifier, it is
clear that the classifier at first discriminates between classes 1
and 2. It then branches off to the tree belonging to fault class
1 or fault classes 2 and proceeds in the same manner finally
culminating in one of the fault classes as 1 or 2 or 3 or 4.
The DAG SVM boasts of these attractive features:

No. of BSVCs that need to be trained for a fault

scenario of 'N' faults N * (N-1) / 2

No. of BSVCs that need to be tested for a fault

scenario of 'N' faults (N-1)
b) CASCADE SVM: For a four fault scenario, the classifier
structure is displayed in Fig.5. The cascade classifier at first
discriminates between classes 1 and 2, 3, 4 combined. It then
branches off to fault class 1 or fault classes 2, 3, 4 combined
and proceeds in the same manner finally culminating in one of
the fault classes as 1 or 2 or 3 or 4.

C. SUPPORT VECTOR MACHINE ENSEMBLE

The fault data is fed into the support vector based
classifier. Three different architecture of support vector
machine are designed, trained and tested, the details of which
are listed.
a) DAG SVM: The Directed-Acyclic-Graph SVM or simply DAG
SVM is one novel classifier that branches off the classification
task amongst the many faults in a tree-like fashion. For a four
fault scenario, the DAG structure is shown in Fig. 4.

Fig.5 CASCADE-SVM Schematic

The CASCADE SVM features are:

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International Journal of Advanced Computing and Communication Systems (IJACCS)

vol.1 Issue.1 March 2014. ISSN: 2347 9299 / 2347 9280

No. of BSVCs that need to be trained for a fault

scenario of 'N' faults - (N-1)
No. of BSVCs that need to be tested for a fault
scenario of 'N' faults - 1 up to (N-1)

c) ONE-VS-ONE (VOTING)SVM: For a four fault scenario, the

classifier considers each pair of the four faults, namely, (1,2),
(1,3), (1,4), (2,3), (2,4), (3,4) and decides upon the result of
each of these pairs. Then, the number of times each fault has
been declared is counted and the fault with the highest
occurrence (votes) is declared the fault to which the input
sample belongs.
The VOTING SVM has the following features:

No. of BSVCs that need to be trained for a fault

scenario of 'N' faults N * (N-1) / 2
No. of BSVCs that need to be tested for a fault
scenario of 'N' faults N * (N-1) / 2

RESULTS ANALYSIS
In this section experimental results on the fault
diagnosis problems carried out on Sallen Key Band Pass Filter
and High Pass Filter are presented. The most important
criterion for evaluating the performance of these methods is
their accuracy rate. However, it is unfair to use only one
parameter set and then compare these three classifiers solely
on their accuracy. Thus, another important parameter, the
time factor involved in training and testing are analyzed as
part of results. It is to be noted that while solving several
binary SVCs (for Voting, Cascaded and DAG architectures), it
is considered with a linear kernel without any modifications.
The computational experiments for this section were done on
a Pentium IV with 2 GB RAM using MATLAB.
TABLE III NUMBER OF BINARY UNITS EVALUATED
Circuit Under
Test
Sallen Key Band
Pass Filter

High Pass Filter

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Architecture

Number of
Binary Units
Evaluated

DAG SVC

Cascaded SVC
Voting SVC
DAG SVC

4
10
10

Cascaded SVC
Voting SVC

10
55

VALIDATION PARAMETERS
Various parameters that are used to validate the
results are shown in Table I. The SVC structure and the
component binary classifiers are first trained using the data of
the relevant classes. The accuracy percentage is then
evaluated by feeding in newer samples called the test samples
to the structure and evaluating the percentage of correct
classification at each node. The overall accuracy of
classification is the average of the classification accuracy of all
the binary classifier nodes involved.
Parameter

Meaning

Accuracy

TrT

Percentage of Correct Classification only for

Testing Samples
Percentage of Correct Classification only for
Training Samples
Training Time

TeT

Testing Time

Recall Rate

Table.I Parameters to validate the results of SVCs

The recall rate is obtained by feeding the same
samples that were used for training, during testing. The recall
rate is an estimate of how well the binary classifiers have
learnt or trained. The training and testing time indicate the
time spent between feeding the samples and obtaining the
results.
PROBLEM STATISTICS
The problem statistics are an illustration of the
dimension of fault dictionary, number of binary classifier
evaluations for each classification architecture. The
statistics are presented in Tables II and Table III.
Circuit Under Test
Sallen Key Band Pass Filter

Fault Dictionary
Dimension
150 x 1

High Pass Filter

330 x 4

Table.II Fault Dictionary Dimension

The Sallen Key filter diagnosis problem considers 30 samples
for each of the five fault classes considered thus the fault
dictionary has a length of 150 rows. The High Pass Filter
diagnosis problem relatively considers 30 samples for each of
the eleven fault classes considered and thus its length is
330 rows. Since the samples are obtained for voltage and
power values from two nodes, i.e., V1, V2, P1, P2, the span of
the fault dictionary is four columns.

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International Journal of Advanced Computing and Communication Systems (IJACCS)

vol.1 Issue.1 March 2014. ISSN: 2347 9299 / 2347 9280

training and testing but as observed, the Cascade Classifier

scores less on accuracy. This can be explained from the fact
that in cascade architecture, each binary evaluation happens
on a larger fault data and consequently, there are more
support vectors than in the other cases.
The results of classification for High Pass Filter are
shown in Table V. Here again the Voting Classifier gives top
performance but takes more time. Its accuracy is paralleled by
DAG classifier but the time factor of which is the least.
Recall Rate
(%)

Accuracy (%)

TrT
(s)

TeT
(s)

DAG SVC

93.5

92.3

0.08

0.09

Cascade
SVC

87.3

86.7

0.08

0.09

Voting SVC

97

96.2

0.16

0.15

Table.III classifier performance for high pass filter

Table III displayed that for the Sallen Key filter, there
exist five fault classes. As discussed in the Support Vector
Classifier section, the DAG and Cascade SVCs each evaluate
(N-1) binary classifier units for an N-fault scenario, on
their road to pronounce the actual fault class. Thus, here, they
evaluate a total of four binary units. On the other hand, the
High Pass Filter where eleven fault classes are present, the
two classifiers evaluate ten binary classifier units. On contrary,
the Voting Classifier evaluates every time, all possible
combinations of the fault classes. The number of possible
combinations for an N-fault scenario is given by N (N-1)/2 and
therefore for Sallen Key filters the number of evaluations
amount to 10 and for High Pass Filter, the number of
evaluations amount to 55.
PERFORMANCE OF CLASSIFIERS
The result of classification for the two CUTs through
the classifiers designed such as accuracy, recall rate, testing
time and training time are listed in Table IV and Table V. In
estimating the accuracy of the classifiers, the evaluation loop
is run ten times and the result is then averaged.
Recall
Rate (%)

Accuracy
(%)

TrT
(s)

be concluded to increase on increasing fault dictionary

dimension.
CONCLUSION
The results of the classifiers show that the
classification methodology adopted is apt for the analog
circuit fault diagnosis problem. The DAG classifier
achieves high performance rates in considerably low time. The
number of binary classifier units employed in this classifier is
only a fraction of the units employed for Voting Classifier.
Voting Classifier gives better performance at the cost of
increased throughput time. By and far, the Voting Classifier
uses maximum number of binary classifier units. Cascade
Classifier which is the easiest to construct is found to
deteriorate in performance when larger data set is
considered. Its performance in general is the lowest and takes
the highest time throughput. But it is to be noted that the
Cascade Classifier has very few binary classifier units in use.
Above all, the trainings of the Binary SVCs are
always successful and the training time needed for each
training set is also stable unlike for the neural network
methods which sometimes fail to converge and the
performance of which also varies depending on the training
stage.
It can be observed that the Voting Classifier takes up
more time for classification compared to its counterparts but
the accuracy of classification is also higher. This is because of
the fact that there are more binary evaluations and at each
evaluation only a fraction of the actual fault dictionary is fed
for classification. The number of support vectors is less and
the classification is superior. The DAG and Cascade Classifiers
share same amount of time for
FUTURE ENHANCEMENTS
The number of support vectors determines
computational complexity and memory requirement.
Optimisation of number of support vectors can lead to better
memory utilisation and faster analysis. Further, evolutionary
algorithms optimize the support vector classifier parameters
thus leading to superior results.

TeT (s)

DAG SVC 98.3

97.1

0.22

0.22

Cascade
SVC

94.3

93.6

1.63

1.62

Voting
SVC

98.3

96.8

1.17

1.18

Table.IV classifier performance for sallen key band

pass filter

The Cascade Classifier comes third in terms of accuracy and

quite surprisingly, on counts of time too. The time factor can
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vol.1 Issue.1 March 2014. ISSN: 2347 9299 / 2347 9280

REFERENCES
[1] E. Hunt, 1975, Artificial Intelligence, New York:
Acedemic.
[2] Vapnik, V.N., 1998, Statistical Learning Theory, Wiley,
New York.
[3] Wai-Kai Chen, 1986, Passive and Active Filters, John
Wiley and Sons, Singapore
[4] Paul Tobin, 2010, PSPICE for Filters and Transmission
Lines, Wiley Publications, New York.
[5] Shigeo Abe, 2005, Support Vector Machine for Pattern
Classification, Springer, New York.
[6] Jiang Cui, Youren Wang, 2010, A Novel Approach
of Analog Fault Classification using Support Vector Machines
Classifier, Metrology and Measurement Systems, ISSN 08608229
[7] Grzechca, D. and Rutkowski, J., 2009, Fault Diagnosis in
Analog Electronic Circuits The SVM Approach, Metrology
and Measurement Systems, Vol XVI, No. 4, pp-583-598
[8] Takahashi, F., Abe, S., 2002, Decision-Tree- Based
Multi-Class Support Vector Machines, ICONIP, Singapore, pp1418-1422.

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