ANNA UNIVERSITY PRACTICAL EXAMINATION APRIL/MAY 2012

Name of the college

College code
Subject code
Subject
Date

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:
:
:
:

A.R.ENGINEERING COLLEGE, VILLUPURAM-605 601.

433
EC2357
VLSI DESIGN LAB
24TH APRIL 2012.

List of question
1(a) Design and Write a VERILOG HDL code for a combinational circuit that has an n input lines and
2n output lines (n=3). Verify the logic design using Xilinx ISE 9.1i and XC3S250 FPGA trainer kit.
(b) Perform the functional verification of the CMOS Inverter through schematic entry.
2(a) Design and Write a VERILOG HDL code for a combinational circuit that has and 2n input lines and
n output lines (n=3).Verify the logic design using Xilinx ISE 9.1i and XC3S250 FPGA trainer kit.
(b) Perform the functional verification of the CMOS Inverter through schematic entry
3(a) Perform the functional verification of a differential amplifier through schematic entry.
(b) Design, synthesize, simulate, implement and program the 4 bit Multiplier using Xilinx ISE 9.1i
and XC3S250 FPGA trainer kit.
4(a) Perform the functional verification of a differential amplifier through schematic entry.
(b) Design, synthesize, simulate, implement and program the 8 bit Adder using Xilinx ISE 9.1i and
XC3S250 FPGA trainer kit.
5(a) Design and write a SPICE simulation of MOS Differential amplifiers and find the CMRR.
(b) Design, synthesize, simulate, implement and program the Multiplexer using Xilinx ISE 9.1i and
XC3S250 FPGA trainer kit.
6(a) Perform the functional verification of a differential amplifier through schematic entry.
(b) Design, synthesize, simulate, implement and program the DEMultiplexers using Xilinx ISE 9.1i
and XC3S250 FPGA trainer kit.
7(a) Perform the functional verification of a differential amplifier through schematic entry.
(b) Design, synthesize, simulate, implement and program the Divider using Xilinx ISE 9.1i and
XC3S250 FPGA trainer kit.
8(a) Design and Write a VHDL code for a combinational circuit that has an n input lines and 2n output
lines (n=3). Verify the logic design using Xilinx ISE 9.1i and XC3S250 FPGA trainer kit.
(b) Perform the functional verification of the CMOS Inverter through schematic entry.
9(a) Design and Write a VHDL code for a combinational circuit that has an 2n input lines and n output
lines (n=3). Verify the logic design using Xilinx ISE 9.1i and XC3S250 FPGA trainer kit.
(b) Perform the functional verification of the CMOS Inverter through schematic entry.

10(a) Design and Write a VHDL code for a combinational circuit that has an Add an 4- bit number.
Verify the logic design using Xilinx ISE 9.1i and XC3S250 FPGA trainer kit.
(b) Design and write a SPICE simulation of MOS Differential amplifiers and find the CMRR.
11(a) Design and Write a VHDL code for a combinational circuit that has Subtract a 4- bit number.
Verify the logic design using Xilinx ISE 9.1i and XC3S250 FPGA trainer kit.
(b) Perform the functional verification of the CMOS Inverter through schematic entry.
12(a) Design and Write a VHDL code for a combinational circuit that has multiply a 4- bit number.
Verify the logic design using Xilinx ISE 9.1i and XC3S250 FPGA trainer kit.
(b) Generate the layout of a CMOS inverter and simulate it.
13(a) Design and Write a VHDL code for a combinational circuit that has a Divide a 4- bit number.
Verify the logic design using Xilinx ISE 9.1i and XC3S250 FPGA trainer kit.
(b) Perform the functional verification of the CMOS differential amplifier through schematic entry.
14(a) Design, synthesize, simulate, implement and program 4 bit up counter using Xilinx ISE 9.1i and
XC3S250 FPGA trainer kit
(b) Generate the layout of a CMOS differential amplifier and simulate it.
15(a) Design, synthesize, simulate, implement and program 4 bit down counter using Xilinx ISE 9.1i and
XC3S250 FPGA trainer kit.
(b) Generate the layout of a CMOS inverter and simulate it.
16(a) Design and Write a VERILOG HDL code for a accumulator, verify the logic design using
Xilinx ISE 9.1i
(b) Generate the layout of a CMOS inverter and simulate it.
17(a) Perform the functional verification of the 10 bit Number Controlled Oscillator through schematic
Entry.
(b) Design, synthesize, simulate, implement and program the full Adder using Xilinx ISE 9.1i
and XC3S250 FPGA trainer kit.
18(a) Design and Write a VERILOG HDL code for a PRBS Generator, verify the logic design using
Xilinx ISE 9.1i.
(b) Perform the functional verification of the 10 bit Number Controlled Oscillator through schematic
Entry.
19(a) Design and Write a VERILOG HDL codes for 4:1 multiplexer using assign, if, and Case
Statement, verify the logic design using Xilinx ISE 9.1i and XC3S250 FPGA trainer kit.
(b) Perform the functional verification of the CMOS Inverter through schematic entry.
20 (a) Design and Write a VERILOG HDL codes for a counter and implement in FPGA and view its
Output using CRO.
(b) Generate the layout of a CMOS inverter and simulate it.

21(a) Synthesis and P&R and post P&R simulation and concepts of floor plan of accumulators.
(b) Perform the functional verification of a differential amplifier through schematic entry.
22 (a) Synthesis and P&R and post P&R simulation and concepts of floor plan of 8-bit adder.
(b) Perform the functional verification of the CMOS Inverter through schematic entry.
23 (a) Synthesis and P&R and post P&R simulation and concepts of floor plan of Decoder.
(b) Generate the layout of the CMOS Inverter through schematic entry.
24 (a) Synthesis and P&R and post P&R simulation and concepts of floor plan of DEMultiplexers.
(b) Generate the layout of the CMOS differential amplifier through schematic entry.
25 (a) Design and Write a VERILOG HDL codes for a counter and implement in FPGA and view its
Output using CRO.
(b) Design and write a SPICE simulation of MOS Differential amplifiers and find the CMRR.

INTERNAL EXAMINAR

EXTERNAL EXAMINAR

G.SATHISHKUMAR (ID 5248)

V.ANANDKUMAR (ID: 1268)

AP/ECE
433 AREC
VILLUPURAM

AP/ECE
440 - SCET
VILLUPURAM

ANNA UNIVERSITY PRACTICAL EXAMINATION APRIL -2012

Name of the college
College code
Subject code
Subject
Date

:
:
:
:
:

A.R.ENGINEERING COLLEGE, VILLUPURAM-605 601.

433
EC2357
VLSI DESIGN LAB
24TH APRIL 2012

MARK ALLOCATION:
AIM/PROCEDURE

PROGRAM

10 Marks
-

20 Marks

LOGICAL DIAGRAM/TABULATION -

25 Marks

EXECUTION
OUTPUT/RESULT
VIVA
TOTAL

INTERNAL EXAMINER

25 Marks
10 Marks
-

10 Marks
100 MARKS

EXTERNAL EXAMINER

G.SATHISHKUMAR (ID 5248)

V.ANANDKUMAR (ID: 1268)

AP/ECE
433 AREC
VILLUPURAM

AP/ECE
440 - SCET
VILLUPURAM