6.

012 - Microelectronic Devices and Circuits - Fall 2005

Lecture 12-1

Lecture 12 - Digital Circuits (I)

The inverter
October 20, 2005

Contents:
1. Introduction to digital electronics: the inverter

2. NMOS inverter with resistor pull up

Reading assignment:
Howe and Sodini, Ch. 5, 5.1-5.3.2

6.012 - Microelectronic Devices and Circuits - Fall 2005

Lecture 12-2

Key questions

What are the key gures of merit of logic circuits?

How can one make a simple inverter using a single

MOSFET?

6.012 - Microelectronic Devices and Circuits - Fall 2005

Lecture 12-3

1. Introduction to digital electronics: the inverter

In digital electronics, digitally-encoded information is represented by means of two distinct voltage ranges:
V
VMAX
logic 1
VOH
VOL

undefined
region
logic 0

VMIN

logic 0: VM IN V VOL
logic 1: VOH V VM AX
undened logic value: VOL V VOH .
Logic operations are performed using logic gates.

Simplest logic operation of all: inversion in

verter
inverter

Lecture 12-4

6.012 - Microelectronic Devices and Circuits - Fall 2005

2 Ideal inverter:

OUT=IN

IN

IN

OUT

Circuit representation and ideal transfer function:

VOUT

v+

V+

+
VIN
-

VOUT=VIN

V+
+

VOUT

0
0

VM= V

V+ VIN

Dene switching point or logic threshold:

threshold:
VM input voltage for which VOU T = VIN
-for 0 VIN VM

VOU T = V +

-for VM VIN V + VOU T = 0

Lecture 12-5

6.012 - Microelectronic Devices and Circuits - Fall 2005

Key property of ideal inverter: signal re

regeneration
generation
VOUT

v+

V+

VOUT=VIN

V+

VIN

VOUT
-

0
0

VM = V

V+ VIN

Ideal inverter returns well dened logical outputs (0 or

V +) even in the presence of considerable noise in VIN
(from voltage spikes, crosstalk, etc.)

logic level
level restoration

noise suppression

pulse edge sharpening

VIN

VOUT

V+

V+

VM

VM

VIN

VOUT

V+

V+

VM

VM

VIN

VOUT

V+

V+

VM

VM

Lecture 12-6

6.012 - Microelectronic Devices and Circuits - Fall 2005

2 Real inverter:
VOUT
V+

logic 1

slope=-1

VMAX
VOH

v+

|Av|>1

undefined
region
logic 0

VOL
VMIN
0

VIN

VOUT

V+

VIN

In a real inverter, valid logic levels dened as follows:

logic 0:
VM IN output voltage when VIN = V +
VOL smallest output voltage where slope=-1
logic 1:
VOH largest output voltage where slope=-1
VM AX output voltage when VIN = 0

Lecture 12-7

6.012 - Microelectronic Devices and Circuits - Fall 2005

Two other important voltages:

|Av|<1
noise suppressed

VOUT

logic 1

VMAX
VOH

slope=-1
|Av|>1
edges sharpened

undefined
region
logic 0

VOL
VMIN
0

|Av|<1
noise suppressed

VIL

VIH

V+

VIN

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VIL smallest input voltage where slope=-1

VIH highest input voltage where slope=-1
To have signal regeneration:

range of input values that produce acceptable logic output

> range of valid logic values
Key to signal regeneration in inverter: high voltage gain

Lecture 12-8

6.012 - Microelectronic Devices and Circuits - Fall 2005

Quantify signal regeneration through noise mar

margins.
gins.
Consider chain of two inverters:
noise

N
VOUT

VIN

VMAX

VMAX

VOH

VOL

NMH

NML

VMIN

inverter M
output

VIH
VIL
VMIN

inverter N
input

Dene noise margins:

N MH = VOH VIH
N ML = VIL VOL

noise margin high

noise margin low

When signal is within noise margins:

logic 1 output from rst inverter interpreted as logic

1 input by second inverter
logic 0 output from rst inverter interpreted as logic
0 input by second inverter

Lecture 12-9

6.012 - Microelectronic Devices and Circuits - Fall 2005

Simplications for hand calculations

Hard to compute Av = 1 points in transfer function.
Approximate calculation:
VOUT
VOH=VMAX
slope= Av(VM)
VOUT=VIN
VM

VOL=VMIN
0

VIL VM VIH

V+

VIN

Assume VOL  VM IN and VOH  VM AX

Trace tangent of transfer function at VM

(slope=small signal voltage gain at VM )

VIL  intersection of tangent with VOU T = VM AX

VIH  intersection of tangent with VOU T = VM IN
to enhance noise margin: |Av (VM )|

Lecture 12-10

6.012 - Microelectronic Devices and Circuits - Fall 2005

VOUT
VOH=VMAX
slope= Av(VM)
VOUT=VIN
VM

VOL=VMIN
0

|Av (VM )| 
|Av (VM )| 

VIL VM VIH

V+

VIN

VMAX VM
VMAX VM
VIL  VM
VM VIL
|Av (VM )|

VM VMIN
1
VMIN
VIH  VM (1 +
)
VIH VM
|Av (VM )|
|Av (VM )|

Then:
NML = VIL VOL  (VMAX VMIN )(VMAX VM )(1+

1
)
|Av (VM )|

NMH = VOH VIH  (VMAX VMIN )(VM VMIN )(1+

1
)
|Av (VM )|

If |Av (VM )| :

N ML VM VM IN

N MH VM AX VM

Lecture 12-11

6.012 - Microelectronic Devices and Circuits - Fall 2005

2 Transient characteristics
Look at inverter switching in the time domain:

VIN

VOH

90%
50%
10%
0

IN

VOL
t

tF

tR

OUT
tPHL

VOUT

tPLH
VOH

90%
50%
10%
0

tF

VOL
tR

tCYCLE

tR rise time between 10% and 90% of total swing

tF fall time between 90% and 10% of total swing
tP HL propagation delay from high-to-low between
50% points
tP LH propagation delay from low-to-high between
50% points
Propagation delay:

tP = 12 (tP HL + tP LH )

Lecture 12-12

6.012 - Microelectronic Devices and Circuits - Fall 2005

Propagation delay: simplication for hand calculations

Input wavefunction = ideal square wave

Propagation delay times = delay times to 50% point

VIN

VOH

tCYCLE

VOL
t
VOUT

tPHL

tPLH

VOH

VOH
50%

tCYCLE

VOL
t

Hand calculations only approximate

SPICE essential for accurate delay analysis

Lecture 12-13

6.012 - Microelectronic Devices and Circuits - Fall 2005

2. NMOS inverter with resistor pull up

V+=VDD

IR
VOUT
ID

VIN

CL
load capacitance
(from following
stages)

Features:
VBS = 0 (typically not shown)
CL summarizes capacitive loading of following stages
(other logic gates, interconnect lines)
Basic operation:
if VIN < VT , MOSFET OFF VOU T = VDD
if VIN > VT , MOSFET ON VOU T small (value set
by resistor/nMOS divider)

Lecture 12-14

6.012 - Microelectronic Devices and Circuits - Fall 2005

VDD

+
R

IR VR
-

VOUT

ID
VIN

Transfer function obtained by solving:

IR = ID
Can solve graphically: I-V characteristics of pull-up resistor on ID vs. VOU T transistor characteristics:
IR=ID

1/R

IR=ID

IR=ID

VDD

VDD

1/R

1/R

0
VR=VDD-VOUT

-VDD

VR-VDD=-VOUT

VDD

VOUT

Lecture 12-15

6.012 - Microelectronic Devices and Circuits - Fall 2005

Overlap I-V characteristics of resistor pull-up on I-V characteristics of transistor:

load line

IR=ID

VGS=VDD

VDD
R

VGS=VIN

VGS=VT
0
0

VDD

VDS=VOUT

Transfer function:

VOUT=VDS
VDD

VT

VDD

VIN=VGS

Lecture 12-16

6.012 - Microelectronic Devices and Circuits - Fall 2005

Logic levels:
VOUT=VDS
VMAX=VDD

VOUT=VIN
VM

VMIN

VT

VM

VDD

VIN=VGS

For VM AX , transistor is cut-o, ID = 0:

VM AX = VDD
For VM IN , transistor is in linear regime; solve:
VM IN
VDD VM IN
W
VT )VM IN = IR =
ID = nCox (VDD
L
2
R
For VM , transistor is in saturation; solve:
ID =

VDD VM
W
nCox (VM VT )2 = IR =
2L
R

Will continue next lecture with analysis of noise margin

and dynamics...

6.012 - Microelectronic Devices and Circuits - Fall 2005

Lecture 12-17

Key conclusions

Logic circuits must exhibit noise margins in which

they are inmune to noise in input signal.
Logic circuits must be regenerative: able to restore
clean logic values even if input is noisy.
Propagation delay: time for logic gate to perform its
function.
Concept of load line: graphical technique to visualize
transfer characteristics of inverter.
First-order solution (by hand) of inverter gures of
merit easy if regimes of operation of transistor are
correctly identied.
For more accurate solutions, use SPICE (or other circuit CAD tool).