WHAT IS DECODER AND ITS TYPES

Labels: DECODER Posted by Abhishek Gupta

DEFINITION OF DECODER:
Decoder is a combinational circuit that converts binary information from n coded inputs to a
maximum of 2n unique outputs. If n-bit coded information has unused combinations, it may
have
less
than
2n outputs.
The
Decoders
are
called
n-to-m
line
n
Decoders, where m2 . In the logic diagram of a 2-to-4 line Decoder, the two data inputs A and
B are decoded into four outputs, each output representing one of the combinations Of the
binary input variables .The inverts provide the compliment of the inputs, and each of the four
AND Gates generates one of the binary combinations. It has one enable input represented by
EN. The decoder is enabled when EN is equal to 1 and disabled when EN is equal to 0 and this
condition of enable input is called Active high enable input. In Active low enable input
condition, it is enabled when EN is equal to 0 and disabled when EN is equal to 1. The
operation of the Decoder can be clarified using the truth table or function table. When the
enable input is equal to 0, all the outputs are equal to 0 regardless of the values of the other
three data inputs. The three crosses in the table designate do not care condition. When the
enable input is equal to 1, it operates in a normal function. For each possible input
combination, there are seven outputs that are equal to 0 and only one that is equal to 1, the
output which is equal to 1 becomes active of its respective input. The truth of the above
decoder is shown below.

EN
1
1
1
1
0

INPUT
A
0
0
1
1
X

OUTPUT
B
0
1
0
1
X

Y0
1
0
0
0
0

Y1
0
1
0
0
0

Y2
0
0
1
0
0

Y3
0
0
0
1
0

USE OF DECODERS:
There is a definite signal or combination of signals at the decoder outputs to correspond to
any signal or combination of signals at the inputs. This correspondence is determined by the
structure assigned during designing of the Decoder. Decoders are used in various data
processing and transmitting devices: in remote control, in computer technology, in radio
engineering and measurement techniques and in telephone and telegraph communications
systems. The purpose determines the structure and the number of inputs and outputs of the
decoder and the form and sequence of the input and output signals. In computer technology
Decoders are used for converting a code or codes into equivalent continuous quantities (for
example, electrical current, voltage, angle of rotation). In radio engineering, Decoders
reconstruct the message transmitted from a radio signal whose parameters (amplitude,
frequency, and phase) change according to the message being transmitted and also does the
reverse operation of an encoder.

TYPES OF DECODERS:
There are different types of Decoder available in the market e.g. 2-to-4 line decoder, 3-to-8 line
decoder or 4-to-16 line decoder, where 2, 3, and 4 are the numbers of inputs to the decoders
and 4, 8, and 16 are the number of output assigned to them. We can form a 3-to-8 line decoder
by using two 2-to-4 line Decoders with enable inputs. Similarly, we can also form a 4-to-16 line
Decoder by cascading two 3-to-8 line Decoders or four 2-to-4 line Decoders.

DECODER CASCADING:

By combining two or more Decoders and getting the logic circuit of another Decoder is
known as Decoder cascading. When we take two decoders and combine them into one
decoder this process is called cascading, now when we want to create a new decoder by the
means of cascading we have to take an extra input that joins the two enable inputs of each
decoders and having an invert gate between them so that only one decoder is active at a time.
When we want to combine four decoders in order to get a single decoder, we have to use a 2to-4 line decoder to select a particular decoder one at a time and only that decoder generates
output and remaining decoders gives 0 as output whatever are the combination of their
inputs.

2-TO-4 LINE DECODER:

In a 2-to-4 line Decoder, there are two input lines and four output line, there is another input
which is called enable input that enables and disable the Decoder. In the picture given below
A and B are two inputs of the Decoder and EN is the enable input. The outputs of the Decoder
are as y0, y1, y2, and y3, only one output is active at a time as the input is given to it. As for
example if input is 00 then y0 is active, if input is given 01 to the decoder the output y1 is
active, similarly for inputs 10 y2 is active and y3 will be active if inputs are 11. On the basis of
the conditions of enable input and the output of a Decoder a 2-to-4 line Decoder can be of the
following types:

1.
2.
3.
4.

When enable input is active high and output is also active high
When enable input is active high and output is active low
When enable input is active low and output is active high
When enable input is active low and output is also active low

BLOCK DIAGRAM

Here, it is the logic diagram of a 2-to-4 line Decoder with active low
enable input and active high enable output. In this logic diagram enable input is preceded by a
circle that represent an invert gate, a low enable input is represented by EN having a bar over
it. A and B are the two inputs and y0, y1, y2 and y4 are the four outputs for four combinations of
inputs A and B.

TRUTH TABLE AND CIRCUIT DIAGRAM

The operation of the Decoder can be illustrated by means of truth table. Since the enable
inputs is following active low logic therefore when enable input is 1 the output of the Decoder
is 0 that means the Decoder does not respond to any combinations of inputs. The two Xs
represent dont-care condition it means the input of Decoder may have any combination.
When the enable input is 0 the Decoder responds to their specific combinations of inputs. For
two inputs the Decoder has four outputs and that are equal to 0 except one. That particular
variable which is equal to 1 is the output of the Decoder for that particular combination of
inputs.
The circuit diagram of the Decoder is shown below to implement this circuit we need four AND
Gates and each AND Gate has different outputs for two inputs A and B. each AND Gate has
three data inputs. Two inputs are the normal inputs of Decoder and one input is enable input.
The enable input enables each AND Gate when it is 0 and disables them when it is 1. The two
inputs have two lines one line generates normal value and one line produces complement of
that particular input. Only one AND Gate gets active at a time for its inputs.

EN
1
1
1
1
0

INPUT
A
0
0
1
1
X

OUTPUT
B
0
1
0
1
X

Y0
0
1
1
1
1

Y1
1
0
1
1
1

Y2
1
1
0
1
1

Y3
1
1
1
0
1

2-TO-4 LINE DECODER CASCADING

The first thing we want to know is what is cascading, the cascading is a process of combining
more Decoders to get a single Decoder. 2-to-4 line Decoder can be combined in such a way
that they can generate 3-to-8 line Decoder, 4-to-16 line decoder or 5-to-32 line Decoder etc.

IMPLEMENTATION OF 3-TO-8 LINE DECODER USING TWO 2-TO-4 LINE DECODER

A 3-to-8 line Decoder can be implemented by cascading two 2-to-4 line Decoders. To see how
it is implemented click on the link given below.
Implementation of 3-to-8 line Decoder using two 2-to-4 line Decoders
IMPLEMENTATION OF 4-TO-16 LINE DECODER USING 2-TO-4 LINE DECODERS

As we have seen that a 3-to-8 line Decoder can be implemented by the uses of 2-to-4 line Decoders in the
same manner we can design a 4-to-16 line Decoder with help of 2-to-4 line Decoders. From the logic
diagram of 4-to-16 line Decoder shown below we see that there are five 2-to-4 line Decoders which combine
in such a way that they generate the output of a 4-to-16 line Decoder. The first Decoder (says) D1 acts as
enabler and that enables only one Decoder at a time. A and B are the two inputs for D1 and they have four
combinations 00, 01, 10 and 11. There are four more Decoders say D2, D3, D4 and D5 respectively. When the
inputs A = 0 and B = 0 Decoder D2 gets active and rest of the Decoders gets inactive. Similarly when A = 0
and B = 1, A = 1 and B = 0, and A = 1 and B = 1 Decoders D3, D4 and D5 gets active respectively. C and D are
the two more inputs which are connected to each Decoders except Decoder D1. As we can see inputs C
and D are connected to each Decoder, they can have four possible combinations for their
each particular combination a particular output gets active. This output belongs to one of the
Decoder which is made active by the inputs A and B. From X1 to X3 they are the output of D2, form X4
to X7 they are the output of D3, from X8 to X11 they are the output of D4 and from X12 to X15 they are the
output of D5. The outputs from X1 to X15 represent the sixteen different outputs of 4-to-16 line Decoder.

IMPLEMENTATION OF 5-TO-32 LINE DECODER USING 2-TO-4

LINE DECODER

A 5-to-32 line decoder has been implemented here using 10 2-to-4 line decoders. A 5-to-32 line
decoder has five inputs and 32 outputs. The block diagram shown here has 10 decoders
namely D1, D2, to D10. A, B, C, D and E are the five inputs of this decoder. Here decoders D1
and D2 are used as a switch which enables the rest of the 8 decoder one at a time. From
decoder D3 to D10 these 8 decoders give the output of a 5-to32 line decoder. Now input A is
used to active either of the decoders D1 and D2 one at a time. When input A is 1 the D1 is
active and D2 is inactive but when A is 0 then D2 is active and D1 is inactive. When D1 is
active the output line X0, X1, X2 and X3 will active their corresponding decoders for the input
combinations of B and C as for example if B and C are both 0 then output line X0 is active and
other output lines of D1 are inactive. Since X0 output line is active so it actives the decoder D3.
Now the last two input lines D and E gives the final output for their respective values if D is 1
and E is 0 then the output line Y2 is active and it gives output 1 and rest of the outputs are 0. In
sort if A = 1, B = C = 0 and D = 1, E = 0 then Y2 = 1. The truth table of 5-to-32 line decoder is
shown below.
INPUTS

OUTPUTS

A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

B
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

E
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Y
Y0 = 1 AND REST ARE ZERO
Y1 = 1 AND REST ARE ZERO
Y2 = 1 AND REST ARE ZERO
Y3 = 1 AND REST ARE ZERO
Y4 = 1 AND REST ARE ZERO
Y5 = 1 AND REST ARE ZERO
Y6 = 1 AND REST ARE ZERO
Y7 = 1 AND REST ARE ZERO
Y8 = 1 AND REST ARE ZERO
Y9 = 1 AND REST ARE ZERO
Y10 = 1 AND REST ARE ZERO
Y11 = 1 AND REST ARE ZERO
Y12 = 1 AND REST ARE ZERO
Y13 = 1 AND REST ARE ZERO
Y14 = 1 AND REST ARE ZERO
Y15 = 1 AND REST ARE ZERO
Y16 = 1 AND REST ARE ZERO
Y17 = 1 AND REST ARE ZERO
Y18 = 1 AND REST ARE ZERO
Y19 = 1 AND REST ARE ZERO
Y20 = 1 AND REST ARE ZERO
Y21 = 1 AND REST ARE ZERO
Y22 = 1 AND REST ARE ZERO
Y23 = 1 AND REST ARE ZERO
Y24 = 1 AND REST ARE ZERO
Y25 = 1 AND REST ARE ZERO
Y26 = 1 AND REST ARE ZERO
Y27 = 1 AND REST ARE ZERO
Y28 = 1 AND REST ARE ZERO
Y29 = 1 AND REST ARE ZERO
Y30 = 1 AND REST ARE ZERO
Y31 = 1 AND REST ARE ZERO

3-TO-8 LINE DECODER

In a 3-TO-8 line Decoder, there are three inputs and eight outputs. And there is one more input
that is named as enable input that makes the decoder active and inactive. there are eight
possible combinations of three inputs and these are 000,001,010,011,100,101,110 and 111.The
output are written as Y0 ,Y1 ,Y2 ,Y 3 ,Y 4 ,Y5 ,Y6 ,Y7 Only one output gets active at a time for its
specific input. For 000 Y0 gets active, for 001 Y1 gets active, for 010 Y2 gets active, for
011 Y 3 gets active, for 100 Y 4 gets active, for 101 Y5 gets active, for 110 Y6 gets active, for
111 Y7 gets active.
As we have classified the 2-to-4 line Decoder on the basis of different conditions of enable
input and output, a 3-to-8 line can also be divided into four different categories.
1. Whenenable input is active high and output is also active high
2. Whenenable input is active high and output is active low
3. Whenenable input is active low and output is active high

4. When enable input is active low and output is also active low
BLOCK DIAGRAM

It is the block diagram of a 3-to-8 line Decoder which follows the active high logics of enable
input and output. A, B and C are three inputs to the Decoder EN is enable input and from y0 to
y7 these are different output for different combinations of inputs.
TRUTH TABLE AND CIRCUIT DIAGRAM

The operation of the 3-to-8 line decoder with active high enable input and active high output
can be clarified using the truth table shown below. When the enable input of the Decoder is 0,
all the outputs of the Decoder are equal to 0 regardless of the values of the other three data
inputs. The three Xs in the table shows dont-care conditions. When the enable input is equal
to 1, the Decoder operates in a normal way. For each possible combination of three inputs,
there are seven outputs that are equal to 0 and only one output is equal to 1. The output
variable whose value is equal to 1 represents the octal number equivalent of the binary
number that is available in the input data lines. The circuit diagram of a Decoder is given below and it
is constructed by using logic gates. AND gates and NOT gates are used to implement it. We use eight AND
gates to generate eight outputs of the Decoder. Each input A, B and C have two inputs lines one for the
normal value of inputs and one for the complement value. Each AND gate has four inputs which of them
three are the regular inputs and one is enable input. Enable input is the input that makes the Decoder
active. The four inputs for first AND gate are A = 0, B = 0, C = 0 and EN = 1 (we are taking EN = 1 because
active high logic of enable input is used here) and output for these inputs is 0. Similarly for other seven AND
gates, the inputs are as written 0011, 0101, 0111, 1001, 1010, 1101, 1111 the LSB (Least Significant Bit)

represent the value of EN and last three bits from left to right each bit represents the inputs A, B and C
respectively.

INPUT
EN
1
1
1
1
1
1
1
1
0

A
0
0
0
0
1
1
1
1
X

B
0
0
1
1
0
0
1
1
X

C
0
1
0
1
0
1
0
1
X

Y0
1
0
0
0
0
0
0
0
0

Y1
0
1
0
0
0
0
0
0
0

Y2
0
0
1
0
0
0
0
0
0

OUTPUT
Y3
Y4
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0

Y5
0
0
0
0
0
1
0
0
0

Y6
0
0
0
0
0
0
1
0
0

Y7
0
0
0
0
0
0
0
1
0

4-TO-16 LINE DECODER USING 3-TO-8 LINE DECODERS

A 4-to-16 line decoder can be implemented by cascading 3-to-8 line decoders with an active
high enable input. Since a 4-to-16 line decoder have four inputs and 16 outputs so we have to
use only two 3-to-8 decoder because each 3-to-8 line decoder have 8 outputs. Now from the
above diagram we can see that there are two 3-to-8 line decoders namely D1 and D2 and both
decoder have same input line A, B and C respectively and active enable input EN serves as
the first input for 4-to-16 line decoder. The decoder D1 gives the output from Y0 to Y7 and
decoder D2 gives output from Y8 to Y15. Now the operation is done as when the enable input is
1 the decoder D1 gets active (while D2 is inactive) and gives output from Y0 to Y7 for the

respective values of A, B and C and when it is 0 the decoder D2 gives output from
while decoder D1 is inactive. The truth table for this block diagram is shown below.
INPUT
OUTPUT
EN A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14
0 0 0 0 1 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0 0 0 1 0 1 0 0 0 0 0 0 0 0
0
0
0
0
0
0 0 1 0 0 0 1 0 0 0 0 0 0 0
0
0
0
0
0
0 0 1 1 0 0 0 1 0 0 0 0 0 0
0
0
0
0
0
0 1 0 0 0 0 0 0 1 0 0 0 0 0
0
0
0
0
0
0 1 0 1 0 0 0 0 0 1 0 0 0 0
0
0
0
0
0
0 1 1 0 0 0 0 0 0 0 1 0 0 0
0
0
0
0
0
0 1 1 1 0 0 0 0 0 0 0 1 0 0
0
0
0
0
0
1 0 0 0 0 0 0 0 0 0 0 0 1 0
0
0
0
0
0
1 0 0 1 0 0 0 0 0 0 0 0 0 1
0
0
0
0
0
1 0 1 0 0 0 0 0 0 0 0 0 0 0
1
0
0
0
0
1 0 1 1 0 0 0 0 0 0 0 0 0 0
0
1
0
0
0
1 1 0 0 0 0 0 0 0 0 0 0 0 0
0
0
1
0
0
1 1 0 1 0 0 0 0 0 0 0 0 0 0
0
0
0
1
0
1 1 1 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
1
1 1 1 1 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0

Y8 to Y15

Y15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1