Microprocessor and Interfaces

MicroprocessorandInterfaces
8085architecture

Pin and signal diagram

Pinandsignaldiagram

Address and data bus signals

Addressanddatabussignals
A15 A8 ((Output3State)
p
)
AddressBus.Mostsignificant8bitsofthememory
addressorthe8bitsoftheI/Oaddress
TristatedduringHoldandHaltmodes
Tri stated during Hold and Halt modes

AD7 AD0(Input/Output 3State)

MultiplexedAddress/DataBus.Lower8bitsofthe
p
/
memoryaddress(orI/0address)appearonthebus
duringthefirstclockcycleofamachinestate
Itthenbecomesthedatabusduringthesecondand
It then becomes the data bus during the second and
thirdclockcycles
TristatedduringHoldandHaltmodes

Control and status signals

Controlandstatussignals
ALE(Output)
AddressLatchEnable
Whenasserted,latcheslowerbyteofaddressonAD7 AD0
ALEisnevertri
ALE is never tristated
stated

RD(Output3state)
IndicatesthatselectedmemoryorI/Odeviceistoberead
anddatabusisavailableforthedatatransfer.
dd t b i
il bl f th d t t
f

WR(Output3state)
IndicatesthatdataontheDataBusistobewrittenintothe
selectedmemoryorI/Olocation
DataissetupatthetrailingedgeofWR
TristatedduringHoldandHaltmodes
g

Control and status signals

Controlandstatussignals
IO/M(Output)
IO/M (Output)
IO/MindicateswhethertheRead/Writeisto
memory or l/O
memoryorl/O
TristatedduringHoldandHaltmodes

SO,S1(Output)(statussignal)
SO S1 (Output) (status signal)
DataBusStatus.Encodedstatusofthebuscycle
S1

S0

HALT

WRITE

READ

FETCH

Externally initiated signals / Interrupts

Externallyinitiatedsignals/Interrupts
READY(Input)
READY (Input)
IfReadyishighduringareadorwritecycle,it
indicates that the memory or peripheral is ready
indicatesthatthememoryorperipheralisready
tosendorreceivedata
IfReadyislow,theCPUwillwaitforReadytogo
If Ready is low, the CPU will wait for Ready to go
highbeforecompletingthereadorwritecycle

Externally initiated signals / Interrupts

Externallyinitiatedsignals/Interrupts
HOLD(Input)
O ( put)
IndicatesthatanotherMasterisrequestingtheuseof
theAddressandDataBuses
TheCPU,uponreceivingtheHoldrequestwill
relinquishtheuseofbusesassoonasthecompletion
ofthecurrentmachinecycle.Internalprocessingcan
y
p
g
continue
TheprocessorcanregainthebusesonlyaftertheHold
i
isremoved
d
WhentheHoldisacknowledged,theAddress,Data,
RD,WR,andIO/Mlinesaretristated
,
,
/

Externally initiated signals / Interrupts

Externallyinitiatedsignals/Interrupts
HLDA(Output)
HLDA (Output)
HOLDACKNOWLEDGE
IndicatesthattheCPUhasreceivedtheHold
Indicates that the CPU has received the Hold
requestanditwillrelinquishthebusesinthenext
clock cycle
clockcycle
HLDAgoeslowaftertheHoldrequestisremoved
CPUtakesthebusesonehalfclockcycleafter
CPU takes the buses one half clock cycle after
HLDAgoeslow

Externally initiated signals / Interrupts

Externallyinitiatedsignals/Interrupts
INTR(Input)
( put)
INTERRUPTREQUEST
Usedasageneralpurposeinterrupt
Ifactive,theProgramCounter(PC)willbeinhibited
fromincrementingandanINTAwillbeissued
RESTARTorCALLinstructioncanbeinsertedtojump
RESTART or CALL instruction can be inserted to jump
totheinterruptserviceroutine
INTRisenabledanddisabledbysoftware
y
ItisdisabledbyResetandimmediatelyafteran
interruptisaccepted

Externally initiated signals / Interrupts

Externallyinitiatedsignals/Interrupts
INTA(Output)
INTA (Output)
INTERRUPTACKNOWLEDGE
Usedinsteadof(andhasthesametimingas)RD
Used instead of (and has the same timing as) RD
duringtheInstructioncycleafteranINTRis
accepted

Externally initiated signals / Interrupts

Externallyinitiatedsignals/Interrupts
RST5.5,RST6.5,RST7.5(Inputs)
RST 5 5 RST 6 5 RST 7 5 (Inputs)
RESTARTINTERRUPTS
ThesethreeinputshavethesametimingasINTR
These three inputs have the same timing as INTR
excepttheycauseaninternalRESTARTtobe
automatically inserted
automaticallyinserted
Orderofpriority
RST7.5>>RST6.5>>RST5.5

TheseinterruptshavehigherprioritythanINTR

Externally initiated signals / Interrupts

Externallyinitiatedsignals/Interrupts
TRAP(Input)
TRAP (Input)
Trapinterruptisanonmaskable restartinterrupt
ItisrecognizedatthesametimeasINTR
It is recognized at the same time as INTR
UnaffectedbyanymaskorInterruptEnable
Ithasthehighestpriorityofanyinterrupt
It h th hi h t i it f
i t
t

Externally initiated signals / Interrupts

Externallyinitiatedsignals/Interrupts
RESETIN(Input)
RESET IN (Input)
SetstheProgramCountertozeroandresetsthe
Interrupt Enable and HLDA flipflops
InterruptEnableandHLDAflipflops
Noneoftheotherflagsorregisters(exceptthe
instruction register) are affected
instructionregister)areaffected
CPUisheldintheresetconditionaslongasReset
isapplied
pp

Externally initiated signals / Interrupts

Externallyinitiatedsignals/Interrupts
RESETOUT(Output)
RESET OUT (Output)
IndicatesCPUisbeingreset
CanbeusedasasystemRESET
Can be used as a system RESET
Thissignalissynchronizedtotheprocessorclock

Serial I/O ports

SerialI/Oports
SID(Input)
SID (Input)
Serialinputdataline
Dataonthislineisloadedintoaccumulatorbit7
Data on this line is loaded into accumulator bit 7
wheneveraRIMinstructionisexecuted

SOD(output)
SOD (output)
Serialoutputdataline
TheoutputSODissetorresetasspecifiedbythe
Th
t t SOD i
t
t
ifi d b th
SIMinstruction

Power supply
Powersupply
Vcc
+5voltsupply

Vss
GroundReference

Clock frequency
Clockfrequency
X1,X2(Input)
, ( p )
CrystalorR/Cnetworkconnectionstosettheinternal
clock
GeneratorX1canalsobeanexternalclockinput
Generator X1 can also be an external clock input
insteadofacrystal
Inputfrequencyisdividedby2togettheinternal
operating freq enc
operatingfrequency

CLK(Output)
Clock
ClockOutputforuseasasystemclockwhenacrystal
Output for use as a system clock when a crystal
orR/CnetworkisusedasaninputtotheCPU
TheperiodofCLKistwicetheX1,X2inputperiod

InternalArchitectureof8085
Microprocessor

Control and Computing

ControlandComputing
ControlUnit
Generatessignalswithinmicroprocessortocarryout
theinstruction,whichhasbeendecoded
Causescertainconnectionsbetweenblocksofthe
Causes certain connections between blocks of the
microprocessor,sothatdatagoeswhereitisrequired
andALUoperationoccurs

ArithmeticLogicUnit
A ith ti L i U it
ALUperformstheactualnumericalandlogic
operationsuchasadd,subtract,AND,OR,etc.
p
UsesdatafrommemoryandAccumulatortoperform
operationandstorestheresultinAccumulator.

8085 Programming Model

8085ProgrammingModel
8085
8085programmingmodelincludessix
programming model includes six
registers,oneaccumulator,andoneflag
register In addition it has two 16bit
register.Inaddition,ithastwo16
bitregisters:
registers:
thestackpointerandtheprogramcounter

Registers
Registers
8085
8085hassixgeneral
has six generalpurpose
purposeregisterstostore
registers to store
8bitdata
IdentifiedasB,C,D,E,H,andL
Identified as B C D E H and L
Thesecanbecombinedasregisterpairs BC,
DE d HL toperform16bitoperations
DE,andHL
f
16 bi
i
programmercanusetheseregisterstostore
orcopydataintotheregistersbyusingdata
copyinstructions.

Accumulator
Accumulator
Accumulator
Accumulatorisan8
is an 8bit
bitregisterthatisapart
register that is a part
ofarithmeticlogicunit(ALU)
Usedtostore8bitdataandtoperform
Used to store 8 bit data and to perform
arithmeticandlogicaloperations
Resultofanoperationisstoredinthe
R l f
i i
di h
accumulator
AccumulatorisalsoidentifiedasregisterA

Flags
ALU
ALUincludesfiveflip
includes five flipflops,
flops,whicharesetor
which are set or
resetafteranoperationaccordingtodata
conditionsoftheresultintheaccumulator
andotherregisters
Zero(Z)
Carry(CY)
Sign(S)
Parity(P)
AuxiliaryCarry(AC)

Flags
Flags
Flagsarestoredinthe8
are stored in the 8bit
bitregistersothat
register so that
theprogrammercanexaminetheseflags(data
conditions) by accessing the register through
conditions)byaccessingtheregisterthrough
aninstruction

microprocessorusestheseflagstotestdata
conditions

Program Counter (PC)

ProgramCounter(PC)
16bit
16 bitmemorypointerregister
memory pointer register
Dealswithsequencingtheexecutionof
instructions
Pointtothememoryaddressfromwhichthe
nextbyteistobefetched
b
i
b f h d
Whenabyte(machinecode)isbeingfetched,
theprogramcounterisincrementedbyoneto
pointtothenextmemorylocation

Stack Pointer (SP)

StackPointer(SP)
Stack
Stackpointerisalsoa16
pointer is also a 16bit
bitregisterusedasa
register used as a
memorypointer
PointstoamemorylocationinR/Wmemory,
Points to a memory location in R/W memory
calledthe
Beginningofthestackisdefinedbyloading
B i i
f h
k i d fi d b l di
16bitaddressinthestackpointerstack

Timing diagram
Timingdiagram
Timing
Timingdiagramisthedisplayofinitiationof
diagram is the display of initiation of
read/writeandtransferofdataoperations
under the control of 3status
underthecontrolof3
statussignalsIO/M,S
signals IO/M S1,
andS0
Uniquecombinationofthese3statussignals
Unique combination of these 3 status signals
identifyreadorwriteoperationandremain
valid for the duration of the machine cycle
validforthedurationofthemachinecycle

Machinecyclestatusandcontrol
signals
l

Processor cycle
Processorcycle
For
Forexecutinganyprogram,2stepsare
executing any program 2 steps are
followedsequentiallywiththehelpofclocks
Fetch
Execute

SSumofthefetchandexecutecycleiscalled
f th f t h d
t
l i
ll d
theinstructioncycle

Opcode
Op
codefetchcycle
fetch cycle
1st machinecycleofanyinstructionisalways
machine cycle of any instruction is always
anOpCodefetchcycle
Inittheprocessordecidesthenatureof
In it the processor decides the nature of
instruction
Itisofatleast4
It is of at least 4states
statesandmaygoupto6
and may go up to 6states
states
DuringM1cycle,theprocessorputstheprogram
counter contents on the address bus and reads
countercontentsontheaddressbusandreads
theopcodeoftheinstructionthroughread
process

Opcode
Op
codefetchcycle
fetch cycle
T1,TT2,andT
and T3 clockcyclesareusedforbasic
clock cycles are used for basic
memoryreadoperationandtheT4 clockand
beyond are used for its interpretation of the
beyondareusedforitsinterpretationofthe
opcode
Basedontheseinterpretations,theP
Based on these interpretations the P
proceedsfurtherfor1or2machinecycleof
memory read and writes
memoryreadandwrites

OPCODE FETCH TIMING DIAGRAM

OPCODEFETCHTIMINGDIAGRAM

OPCODE FETCH
OPCODEFETCH
AlowIO/Mmeansmicroprocessorwantstocommunicate
withmemory
ThePsendsahighonstatussignalS1 andS0 indicating
fetchoperation
ThePsends16bitaddress.ADbushasaddressin1st
clockofthe1stmachinecycle,T1
AD7 toAD
to AD0 addressislatchedintheexternallatchwhen
address is latched in the external latch when
ALE=1
ADbusnowcancarrydata
InT
In T2,theRDcontrolsignalbecomeslowtoenablethe
the RD control signal becomes low to enable the
memoryforreadoperation
ThememoryplacesopcodeontheADbus

OPCODE FETCH
OPCODEFETCH
Thedataisplacedinthedataregister(DR)andthenitis
transferredtoinstructionregister(IR)
DuringT3,theRDsignalbecomeshighandmemoryis
disabled
DuringT4,theopcodeissentfordecodinganddecodedin
T4.
TheexecutionisalsocompletedinT
The execution is also completed in T4 iftheinstructionis
if the instruction is
singlebyte
Moremachinecyclesareessentialfor2or3byte
instructions. The 1st machine cycle M1 is meant for
instructions.The1stmachinecycleM1ismeantfor
fetchingtheopcode.ThemachinecyclesM2 andM3 are
requiredeithertoread/writedataoraddressfromthe
memoryorI/Odevices
y
/

Read Cycle
ReadCycle
The
Thehighorderaddress(A
high order address (A15 A8)andlow
) and low
orderaddress(AD7 AD0)areassertedon1st
low going transition of the clock pulse
lowgoingtransitionoftheclockpulse
A15 A8 remainsvalidinT1,T2,andT3 i.e.
duration of the bus cycle but AD7 AD0
durationofthebuscycle,butAD
remainsvalidonlyinT1
ALEisassertedatthebeginningofT
ALE i
d
h b i i
f T1 ofeach
f
h
buscycleandisnegatedtowardstheendofT1

Memory read timing diagram

Memoryreadtimingdiagram

I/O Read timing diagram

I/OReadtimingdiagram

Write Cycle
WriteCycle
After
Aftertheterminationoftheloworderaddress,at
the termination of the low order address at
thebeginningoftheT2,dataisassertedonthe
address/databusbytheprocessor
/
y
p
WRcontrolisactivatednearthestartofT2 and
becomes inactive at the end of T3
becomesinactiveattheendofT
TheprocessormaintainsvaliddatauntilafterWR
is terminated. This ensures that the memory or
isterminated.Thisensuresthatthememoryor
porthasvaliddatawhileWRisactive

Memory write timing diagram

Memorywritetimingdiagram

I/O Write timing diagram

I/OWritetimingdiagram