A General EM-Based Design Procedure for Single-Layer Substrate

Integrated Waveguide Interconnects with Microstrip Transitions

Jose E. Rayas-Sanchez (1) and Vladimir Gutierrez-Ayala (2)
(1) Department of Electronics, Systems and Informatics, ITESO (Instituto Tecnol6gico y
de Estudios Superiores de Occidente), Tlaquepaque, Jalisco, 45090 Mexico
http://iteso.mx/--erayas e-mail: erayas@iteso.mx
(2) Intel - Guadalajara Design Center, Tlaquepaque, Jalisco, 45600 Mexico
e-mail: vladimir.gutierrez.ayala@intel.com
Abstract - We propose in this work a general procedure to
efficient EM-based design of single-layer SIW interconnects,
including their transitions to microstrip lines. Our starting point
is developed by exploiting available empirical knowledge for
SIW. We propose an efficient SIW surrogate model for direct EM
design optimization in two stages: first optimizing the SIW width
to achieve the specified low cutoff frequency, followed by the
transition optimization to reduce reflections and extend the
dominant mode bandwidth. Our procedure is illustrated by
designing a SIW interconnect on a standard FR4-based
substrate.
Index Terms - Substrate integrated waveguides, SIW, EMbased optimization, high-speed interconnects, microstrip-to-SIW
transitions.

I. INTRODUCTION
When used as transmission media, classic rectangular
waveguides (RWG) are optimal to reduce electromagnetic
susceptibility and crosstalk due to their hardened structure.
However, conventional waveguides are bulky and difficult to
embed in typical multilayer printed circuit boards (PCB). In
the microwave range, the physical dimensions of planar
interconnects and conventional RWG are quite different [1],
imposing the need of complex transition structures that
usually require high-precision manufacturing processes and
even some kind of tuning [2], making them unsuitable for
low-cost massive-production PCB structures.
Substrate integrated circuits aim at exploiting the
advantages of both RWG and microstrip lines (high Q-factor,
high power capacity, low-cost, small size and simplicity of
integration). Substrate integrated waveguide (SIW) structures
are promising candidates for a new generation of low-cost
PCB interconnects for high-speed digital applications [3],
given their simplicity, their adequacy for planar and
multilayer structures, and their low radiation losses and low
sensitivity to electromagnetic interference (EMI) [4].
However, poorly designed transitions can make higher-order
modes to propagate along the SIW, which deteriorates the
signal integrity and reduce the effective channel bandwidth.
In this work we propose a general procedure to EM-based

This work was supported by CONACYT (Consejo Nacional de

Ciencia y Tecnologia, Mexican Government) under Grant C0242930A-I, and by Intel Guadalajara Design Center.

978-1-4244-1780-3/08/$25.00 2008 IEEE

design optimization of single-layer SIW interconnects,

including the transitions to microstrip lines. An initial design
is developed by applying empirical formulas and design
criteria available in the literature for SIW. A full-wave
electromagnetic simulation of the initial design is realized. We
propose a suitable SIW surrogate model for direct EM
optimization, which is implemented in two stages: optimizing
the SIW width to achieve the desired low cutoff frequency,
followed by the transition optimization to minimize reflections
and extend the dominant mode bandwidth. The optimal
solution found is applied to the original structure, for a final
EM-verification. We illustrate our general procedure by
designing an SIW interconnect with a broad bandwidth on a
standard FR4-based substrate for high-speed digital
applications.
II. SIMPLIFIED ApPROXIMATIONS FOR THE SIW
The fundamental parameters of a substrate integrated
waveguide are shown in Fig. 1. The SIW emulates a
dielectric-filled waveguide whose lateral walls are formed
through rows of vias sufficiently close to each other. The SIW
has a width W (center-to-center distance between the rows of
vias). Each via has a diameter d and is separated from its
neighboring via by a center-to-center spacing s. The SIW is
embedded in a dielectric layer with height H, relative
dielectric constant en and loss tangent tan y. If properly
designed, the behavior of a SIW is similar to that one of a
conventional RWG [5].
A. CutoffFrequencies

Let a and b denote the width and height of the conventional

RWG, respectively. Assuming a > b, the propagating mode

er
Fig. 1
Fundamental physical parameters of a substrate integrated
waveguide (SIW).

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with the lowest cutoff frequency is the TE lo (dominant mode).

We calculate a using [6]
c
a=
(1)

2fcloF;
where;;10 is the cutoff frequency of the TE IO mode, and c is
the speed of light in free space. The cutoff frequencies of each
propagating mode on the waveguide are given by [6]
femn

2F: (~r +(~

(2)

where m and n are the mode indexes. We know that TM

modes impose longitudinal surface currents on the lateral
walls. These currents can not flow in a SIW due to the
dielectric gaps created by the via separations. On the other
hand, vertical surface currents can flow in the SIW through
the lateral vias, such that TE rnO modes can be preserved [5].
It is well known that signal degradation occurs when more
than one mode is propagating (overmoded waveguide). If the
feeding microstrip line at the connecting point to the SIW is
sufficiently wide, it is unlikely to have the TE 20 mode
propagating along the SIW. From (2), an approximate single
mode bandwidth for the SIW interconnect can be estimated if
the first higher-order mode propagating is the TE 30 mode,
c
(3)
BWS1W ~ fc30 - felo = 2felo =
r:-

a-yG r

Under the above assumptions, it is seen that a relative

bandwidth of 100% is achievable for the SIW interconnect. If
the excitation of the SIW is designed in such a way that the
first higher-order mode is the TE40 mode, then the
approximate single mode relative bandwidth for the SIW
would be 1200/0.

B. Metallic and Dielectric Losses

The Q- factor of a SIW is smaller than that one of a classic
air-filled metal RWG, because of the dielectric filling and the
volume reduction. We know that attenuation due to conductor
losses for the TE IO mode, of a classic RWG, decreases with
the substrate height b [6], while the attenuation constant due
to dielectric loss (as long as the waveguide is completely filled
with the dielectric) decreases with a. Finally, using dielectrics
with small Gr yields lower dielectric losses.

Fig. 2
Substrate integrated waveguide interconnect (SIW) with
microstrip transitions.

978-1-4244-1780-3/08/$25.00 2008 IEEE

C. Radiation Losses
If the separation s between vias is too large, radiation losses
occur due to EM field leakage in the SIW. Additionally, via
diameter d may significantly affect the return loss of the SIW
transition.
Two useful empirical criteria (obtained from EM simulation
results [7]) to establish upper bounds for sand dare s ::; 2d
and d::; Ag /5, where Ag is the guided wavelength, which for the
dominant mode is given by
AgIO

= 21< /

[c~~2 )-( ~

(4)

If the first higher-order mode propagating along the SIW is

the TE mo mode, from (2) and (4) an upper limit for the via
diameter is given by

d<

2a

(5)

- 5~m2 -1

Assuming a 100% relative bandwidth (m = 3), the upper

limit for the via diameter d ::; 0.1414a should be used. If a
1200/0 relative bandwidth is achievable through a suitable
excitation of the SIW, the more demanding upper limit d ::;
0.1033a should be used. Finally, to reduce manufacturing
costs, sand d should be selected as large as possible.

D. Physical Width ofthe SIW

A good approximation (provided that the separation sand
the ratio dlW are sufficiently small) to calculate the effective
width, a, of a substrate integrated waveguide is given by [5]

d2

d2

a = W -1.08-+0.1s
W
Substituting s = 2d in (6), and solving for W,
W=
a + ~(a + 0.54d)2 - OAd 2 ] + 0.27d

O.5[

(6)

(7)

where the value of d can be chosen according to the expected

bandwidth using (5).
III. INITIAL DESIGN FOR THE SIW
We now apply the equations and criteria described in
previous section to arrive to an initial design of a particular
single-layer SIW interconnect with tapered microstrip
transitions, as that one shown in Fig. 2, with L S1W = 1.575
inches. The SIW interconnect is implemented on a standard
substrate for high speed digital applications, N -4000-13 I,
with Gr = 3.6 and tan y= 0.008 at 10GHz. The initial substrate
height is H = 16 mil. The desired cutoff frequency for the
dominant mode is;;1O = 10GHz, and a relative bandwidth of
120% is desired.

1 Nelco Advanced Circuitry Materials Park Electrochemical Corp.,

Nelco N-4000-13 High-Speed Multifunctional Epoxy Laminate &
Prepreg Technical Data Sheet, http://www.parkelectro.com/. 2007.

984

Fig. 3
Detailed 3D view of the SIW as implemented in Sonnet.
and Ygap are selected to avoid box resonances. Sonnet's box top
cover is defined as free-space.

Hair

from the intended lew, it shows transmission deterioration due

to the TE30 mode, and significant reflections in the passband.

'.a

Fig. 5
Coarse model of the SIW including microstrip transitions.
It uses squared vias, very low-resolution in the horizontal direction
'
and very short length (only 10 vias along the SIW).

0.8
~

~VJ
II

0.6

IV. OPTIMIZING A COARSE MODEL OF THE SIW INTERCONNECT

0.4

Following the space mapping concepts [8], we declare as

the fine model the previously described SIW with microstrip
transitions simulated with Sonnet with a high-resolution
discretization, using the full physical length for the
waveguide. Due to the long time required by each EM
simulation of this fine model, we use for direct EM
optimization the coarse model illustrated in Fig. 5. It is a short
(L = 9s + d) replica of the original model, with squared vias
and low resolution grid in the x-direction but very high
resolution grid the y-direction. It consumes only 9 minutes
and 43 seconds per frequency sweep (48 frequency points).
The coarse model response at the initial design is shown in
Fig. 6, which also presents the same deviation in lew as the
fi~e model. We first correct this deviation by optimizing 182 II
WIth respect to WSIW to satisfy in a minimax sense the design
speci~cations indicated in Fig. 6. The optimal solution is
WSIW = 391.18 mil, and its corresponding response is also in
Fig. 6. The evolution of the objective function is shown in
Fig. 7. The 21 coarse model evaluations consume 44.55
minutes using the same computer (during optimization we
only evaluate frequencies within design specification ranges).
Next we optimize the coarse model to extend the dominant

2.-C+-o
~

~
Q)
"'C
0

0.2

s::

10

20

30

40

50

Frequency (GHz)
~ig.

4. EM r~sponses of the initial SIW interconnect (fine model),

Including the mlcrostrip transitions.

Using (1) we obtain a = 311.25 mil. Taking d = 0.1 033a =

32.15 mil, and substituting in (7) we get W = 328.29 mil. The
external width of the SIW interconnect is WSIW = W + d =
360.45 mil. A detailed view of the transition structure is
shown in Fig. 3. The complete SIW interconnect (including
the microstrip transitions and ground plane) uses copper with
a conductivity O'Cu = 5.8 x 107 Sim and thickness t = 0.65 mil
(half-ounce copper). To reduce losses and preserve hardened
most of the interconnect, we use L tap = 10d, and L p = 5d.
The initial transition dimensions are as follows (see Fig. 3):
Wp = 35.32 mil (for a 50-0 microstrip line at low frequencies)
and the tapered microstrip width, intended to provide the field
matching, initially uses fftap = 0.5(W - d) = 148.07 mil.
We implement this structure in the full-wave EM simulator
Sonnet 2. We keep a distance Ygap = 3WSIW between the SIW
walls and Sonnet's box lateral walls. An air layer whose
height is Hair = 4H, exists between the SIW and the top cover
of Sonnet's box, which we define as free-space. By using
these values of Ygap and Hair we avoid the effects of unwanted
EM interaction and potential resonances with Sonnet's box.
Fig. 4 shows the reflection and transmission responses of
the SIW structure using the dimensions mentioned above and
a high-resolution grid. One linear frequency sweep (48
frequencies) using a computer with a 3 GHz Pentium IV
processor with 1.5 GB of RAM consumes 5 hours 16 minutes.
It is seen that our initial design has a significant deviation

Sonnet vi 1.53, Sonnet Software Inc., North Syracuse, NY, 2007.

978-1-4244-1780-3/08/$25.00 2008 IEEE

0.8
0.6

~~
0.4
-----

0.2
L...J

x~O) = WS1W (initial)

--x;=W;IW

o0'------'~-1'----0---2L-0- - - 3 O---4O-------l50
L

Frequency (GHz)
Fig. 6
EM responses of the SIW interconnect (coarse model),
before and after optimizing the cutoff dominant mode frequency.

985

0.6

- -

- - - - - - I - - - - - - - -- - - - - - - -

0.4

- - - -

0.2

- - -

r- - - - - - r- - - - - -

1- -

I
1
I
I

I
I
I
I

1
I
1
I

I
I
1

I
I
1

r - - - - -

- -

I
I
I

1- -

1
-

- 1- -

- I

1
I
I
I

I
I
I
I

- 1- -

- 1

I
I
I

I
I
I

--~---- ~-----~-----~-----:

o --

I
1

-0.2 '----_ _

- ' - - -_ _------"--_-----.J

---L-_ _----'-

10

15

20

25

coarse model evaluations,j

Fig. 7
Evolution of the minimax objective function during the
coarse model optimization to find WSIW*.
1

----------------------

I
I
I
I
_____ I

0.8
0.6
CI:)-

I
I

I
I
I

___ J

0.4

_
I

0.2
0

20

10

50

40

30

Frequency (GHz)
I

0.8

0.4

- -

----:

J.

L - -

l- A- }- -

..

~,~\-

II

I I I"

\ I

I
1

-.J

I ~:
-.1_11

I
L

\1

1
I

I
I

I :
I'

I
1

I
I

atx(O) = [~O)
c
SIW

:- - - - -

:
10

~: ~

W<0) IfO)]
tap

--atx;=[W;IWW:apH*]:
20

30

40

50

Frequency (GHz)
Fig. 8
EM responses of the SIW interconnect (coarse model)
before and after optimizing ~ap and H.

*~

p.,

*~s 0.8

~
*~ 0.6
II

4-0

0.4

10

20

30

40

The authors thank Dr. 1. C. Rautio, President of Sonnet

Software, Inc., for making em available.

.....,

'i l

0.2

I.

\'

- - - - - - - - - -.J -

0.6
c:::i

CI:)

ACKNOWLEDGMENT
I
I
I

l :"'--=--~-~;-"-""::I ~ - - - - - ~

-I

IV. CONCLUSIONS
An efficient procedure to EM-based design of SIW
interconnects with microstrip transitions was described. The
initial design is developed from available empirical equations.
An efficient SIW surrogate model is used for direct EM
optimization, first optimizing the SIW width, and then
optimizing the transition structure. By this procedure we
obtained a significant improvement in the return and insertion
loss for the original SIW structure in the passband. The
optimized SIW interconnects can be used for ultra-high speed
data transmission.

I
I

... ,

matching. We do this by optimizing ISlll and IS211 with respect

to fftap and H, to satisfy in a minimax sense the design
specifications indicated in Fig. 8, where we also show the
initial and final coarse model responses. The optimal solution
is Wtap * = 200.95 mil and H* = 21.46 mil, found after 33
coarse model frequency sweeps.
Finally we evaluate the original fine model at Xc * = [WS1W *
fftap * H*] T, with the rest of the parameters as in the initial
design. The corresponding fine model response is in Fig. 9. It
is seen a remarkable improvement in the SIW performance
(compare with Fig. 4).

50

Frequency (GHz)
Fig. 9
EM responses of the optimized SIW interconnect (fine
model), including the microstrip transitions.

REFERENCES

[1] H-W. Yao, A. Abdelmonem, J-F. Liang and K. A. Zaki,

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[2] N. Kaneda, Y. Qian and T. Itoh, "A broad-band microstrip-towaveguide transition using quasi-Vagi antenna," IEEE Trans.
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[3] D. Deslandes and K. Wu, "Integrated microstrip and rectangular
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[4] A. Suntives and R. Abhari, "Experimental evaluation of highspeed data transmission in a waveguide-based interconnect," in
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[5] F. Xu and K. Wu, "Guided-wave and leakage characteristics of
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[6] D. M. Pozar, Microwave Engineering. Amherst, MA: Wiley,
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[7] D. Deslandes and K. Wu, "Design consideration and
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[8] 1. W. Bandler, Q. Cheng, S. A. Dakroury, A.S. Mohamed, M.
H. Bakr, K. Madsen and 1. Sendergaard, "Space mapping: the
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pp.337-361,Jan.2004

mode bandwidth and to improve the input/output field

978-1-4244-1780-3/08/$25.00 2008 IEEE

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