DigitalElectronics StateEquations Diagrams

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D
Digital
E
Electron
nics
State
S
E
Equatio
ons & Diagra
D
ams
A statte euqtion is an algeebraic exprression thaat specifiess the
condittion for a flip-flop sttate transittion. The left
l side off the
co
m
equatio
on denotess the next state of th
he flip-flop
p and the right
r
side of the equattion is a Boolean exp

pression that specifiess the
equal to
t 1.
1
State Table:
T
ed
uc
at
io
n.
nt state an
nd input co
onditions tthat make the next state
presen
The State Table consists off four sectiions labeled present sstate, inputt, next state,
n shows thee states of the flip-flo
ops
and ouutput. The present staate column
and
at any given timee . The neext state co

olumn show
ws the statees of the fliip-flops on
ne
the value of
1, for given valuee of . Th

he output section
s
givees
hi
clock period lateer at time
fo
or each present state. B
Both the next
n state an
nd output sections wiill
0 and the otther for
ks
have tw
wo sub collumns, onee for
Next Staate (NS)
.s
a
Prresent
1.
Ou
utput
w
w
S
State
(PS)
(
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In general, a sequential circuit with
2
flip-flops, and
input variables, will have
rows, one for each state. The next state and ouput columns will have 2
columns one for each input combination.

State Diagram:
co
m
The information available in a State Table can be represented graphically in a

state diagram. In this, a state is represented by a circle, and the transition between
states is indicated by directed lines connecting the circles. The state diagram
provides the same information as the State Table. The binary number inside each
ed
uc
at
io
n.
circle represent the state of the flip-flops. The directed lines are labeled with two
binary numbers separated by a slash. The input value during the present state is
labeled first and th number after the slash gives the output during the present
state. A directed line connecting a circle with itself indicates that no change of
.s
a
ks
hi
state occurs.
w
w
Flip-flop input functions:

The logic diagram of a sequential circuit consists of flip-flops and gates. The
knowledge of the type of flip-flops and a list of the Boolean functions of the
combinational circuit provide all the information needed to draw the logic
diagram. The part of the combinational circuit that generates external outputs is
described algebraically by the circuit output functions. The part of the circuit that
generaates the inp
puts to flip
p-flops are described algebraicallly by a sett of Booleaan
ed
uc
at
io
n.
co
m
functio
ons called flip-flop
f
inp
put functio
ons.
The fliip-flop input function

ns for the aabove circuuit are
State Diagrams
D
s and Statee Tables off flip-flopss:
w
w
.s
a
ks
hi
SR Fliip-flop:
N
Next Statee (NS)
P
Present
State
(PS)
0
N
Next Statee (NS)
P
Present
State
ed
uc
at
io
n.
(PS)
0
1
.s
a
ks
hi
D Flip
p-flop:
w
w
co
m
JK Fliip-flop:
P
Present
Next Sttate
State
(NS))
(PS)
0
Next Sttate
State
(NS))
ed
uc
at
io
n.
P
Present
co
m
T Flip
p-flop:
(PS)
0
hi
R
and
a Assign
nment:
State Reduction
ks
Any dessign processs must con

nsider the problem
p
off minimizin
ng the costt of the final
circuit. The
T two most
m obviouus cost reduuctions are reductionss in the num
mber of flip
p-
.s
a
flops an
nd the num
mber of gaates. The reduction
r
o the num
of
mber of flip
p-flops in a
sequentiial circuit is
i referred to as the sstate reduction probleem. Since
flip-flop
ps
producee 2 states, a reductio

on in the number of states
s
may result in a reduction in
i
w
w
the num
mber of flip-flops.
Two states
s
are saaid to be equivalent iff, for they give exactlly the samee output an
nd
send thee circuit eitther to the same state or to an eqquivalent state. Wheen two statees
are equivvalent, onee of them can
c be remo
oved.
ed
uc
at
io
n.
co
m
Example:
hi
State Table for the given state diagram:
ks
Next State
(NS)
w
w
.s
a
PS
Output
In the above State Table, e and g are equivalent and hence g can be removed and in
place of g, e is placed. Then, again we look for equivalent states and we see that d
and f are equivalent. Hence, the reduced Table will consists of 5 states and requires
3 flip-flops again.
(NS)
PS
ed
uc
at
io
n.
Output
co
m
Next State
b
c
d
e
State Assignment:
State assignment procedures are concerned with methods for assigning binary
.s
a
ks
drives the flip-flops.
hi
values to states in such a way as to reduce the cost of the combinational circuit that
Three possible binary State Assignments

Assignment 1
Assignment 2
Assignment 3
001
000
000
010
010
100
011
011
010
100
101
101
101
111
111
w
w
State
Reduced State Table with Binary Assignment 1
Present State
Next State
Output
x=1
x=0
x=1
001
001
010
010
011
100
011
001
100
100
101
100
101
001
ed
uc
at
io
n.
co
m
x=0
w
w
.s
a
ks
hi
100
0
1
1

DigitalElectronics StateEquations Diagrams

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side of the equattion is a Boolean exp

at any given timee . The neext state co

1, for given valuee of . Th

clock period lateer at time

Next Staate (NS)

input variables, will have

columns one for each input combination.

The information available in a State Table can be represented graphically in a

Flip-flop input functions:

The fliip-flop input function

Any dessign processs must con

producee 2 states, a reductio

State Table for the given state diagram:

drives the flip-flops.

Three possible binary State Assignments

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