IEEE
JOURNAL
OF SOLID-STATE
CIRCUITS,
SC-20, NO. 6,
VOL.
1985
DECEMBER
A High-Performance
Micropower
Switched-Capacitor
Filter
RINALDO
CASTELLO
AND PAUL
R. GRAY,
power-supply
high-performance
power-supply
from
a single
combined
fifth-order
low-pass
with input-to-output
and switched-capacitor
prototype
switched-capacitor
fabricated
uses a fully
class A B amplifier
common-mode
differential
design, dynamic
operating
topology
biasing,
(CMFB). An experimental
feedback
in a 5- p m CMOS
filter
technology
requires
orlly 350 pW of
to meet
about
3900 milz.
the PCM
been described
for
INTRODUCTION
PERFORMANCE
of
switched-capacitor
filters
of CMOS operational
amplifiers.
This improvement
has
been particularly
evident in the PCM channel filter application [1][6]. However, the most recent commercial PCM
filter
implementations
still require a power-per-pole
of
1 mW
recently
and
been
standpoint,
operate
shown
from
a ~ 5 V supply.
the absolute
minimum
from
It has
a fundamental
achievable
power
dis-
while
maintaining
have important
operated
high-performance
implications
analog/digital
A second
formance
in the realization
levels,
requiring
rejection,
applications
low-power
limited
dynamic
such as PCM
off a low
and
for high-per-
telephony.
This paper
describes a fifth-order
CMOS PCM channel filter operated
from a single 5-V supply and dissipating about 70-pW per
pole which embodies a combination
of circuit techniques
including
input-to-output
class All amplifier
design, fully
differential
topology,
dynamic
biasing,
and switchedcapacitor
common-mode
1O-V
The
commercial
paper
fundamental
low-pass
These techniques
or improved
realizations,
and operating
is organized
limit
to the achievable
available
while
In
IV
discusses
the actual
devices. In Section
test
the
design.
the
structure
of the
low-pass
filter
level
performance
of
Finally,
prototype
Section
III
II.
LIMITS
supply.
Section
II
the
for a
range
fifth-order
switched-
V presents
the
new
some experimental
with
re-
would
dissipating
of given dynamic
with
operational
amplifier,
which represents
filter reported in this paper, is described
capacitor
pro-
respect to
power dissipation
filter
and compared
with
on a 5-V power
as follows.
switched-capacitor
is computed
mercially
feedback.
comparable
TO POWER DISSIPATION
of battery-
consideration
filters
in the realization
of
These, however,
can be preserved
AND DYNAMIC
RANGE
interfaces.
important
switched-capacitor
tion
about
[8]-[14],
voltage.
applications
current
IEEE
vide performance
I.
HE
FELLOW,
MOS
switched-capacitor
filters
have
Power consumption
VLSI
systems.
reduction
Present
is always a major
commercial
issue in
switched-capacitor
filters consume far more power than the theoretical minimum required. For this reason, this section examines some
fundamental
limitations
to the achievable minimum
power
dissipation
for a low-pass switched-capacitor
filter of given
dynamic range. This analysis has been carried out in detail
in a previous paper [20], [21], and in this section only the
main results are summarized stressing their intuitive interpretation.
0018-9200/85
In present
dc bias
normally
/1200-1122$01
day switched-capacitor
filters,
the quiescent
.00 01985
IEEE
CASTELLO
AND
GRAY:
MICROPOWER
SWITCHED
CAPACITOR
1123
+v~~
+VSs
100
130
120
/
110
/
+ (dB)
-%s
100
4-
---
---
-vs~
---
--
90
Fig. 1.
Minimum
I
1
I
I
t
$
1
80
/
the supply
in order
the sampling
1
70
and integrating
capacitor within the filter. We assume for
this analysis, however, that, through improved circuit techniques, the op amp static power dissipation can eventually
be reduced to the point of being negligible with respect to
I
1
/ /
,.-1
,()-2
Mm
is then analogous
to that of a CMOS
95dB
Fig, 2,
tor.
pling
one clock
During
period
for a switched-capacitor
capacitor
supply
~ is present
switched-capacitor
at the output
integra-
of the integrator,
the
filter
can be obtained
associated
however,
clock
as in a CMOS
to the
of the
which
gate. As an example
this power is on
frequency
band
should
of
interest,
the
size of
then be reduced.
constrained
the
integrating
The integrating
to be larger
dynamic
noise contribution.
should
intuitively
if it is noticed
correct
This
to the supply
III.
voltage
range
appear
band
dominate
in typical
and l/~
for a factor
is therefore
noise).
of two or so.
feasible
if op amps
are designed.
OPERATIONAL
As just illustrated,
capaci-
of the filter
is proportional
with
to the frequency
and not
to
the fact that the above analysis neglects the noise contribuThis,
Here it is important
frequency
8.51JW
times
emphasize
,04
bandwidth
is shown. A dynamic range of 95 dB requires
only 8.5 pW of power. Commercially
available switchedcapacitor
PCM filters of similar performance
use almost
tion
of the signal.
(pW)
minimum
power dissipation
is proportional
to the maximum energy that can be stored on the integrating
capacitor
the frequency
Power
,.3
lot
integra-
10
logic gate. Fig. 1 shows the flow of power from the supplies
during
AMPLIFIER
ARCHITECTURE
tends to
new
concepts.
circuit
The first
configuration
is fully
is based
differential
on four
architecture
main
which
as energy stored on
capacitors,
increasing
the maximum
energy that can be
stored is equivalent
to increasing
the maximum
signal
energy level that the filter can process and therefore is
equivalent
to increasing the filter dynamic range. In fact,
the dynamic
in the following
capacitor
filter
range
is related
to the ratio
of maximum
and applying
them
to
sections.
A. Fully Dijjferential
Topology
A fully differential
switched-capacitor
integrator is shown
in Fig. 3. The two input voltages ~~ and ~; are symmetrical with respect to the common-mode
input voltage V&l,
and the two output voltages VO+ and VO- are symmetrical
1124
IEEE
JOURNAL
OF SOLID-STATE
CIRCUITS.
VOL.
(-)
Ou
1A
v2-
Fig. 4.
Fig, 3.
with
respect
This
structure
Fully differential
to the common-mode
doubles
the
output
output
voltage
swing,
which
VCMO.
is of
paramount
importance
for low-voltage
applications,
and
provides a reduction on the sensitivity to supply and clock
noise so that good PSRR can be obtained without having
to decouple
the input
it is instead
required
in
a simplified
low-voltage
proach
in the single-ended
design.
allows
structure
much
Furthermore,
the designer
summing
input
a fully
suitable
differential
common-mode
performance.
as
to independently
and output
choose
for
apthe
voltages ( PC,,
Although
for maxi-
n-channel
threshold
is the increased
this design
circuit
mately
power
of the fully
common-mode
the power
40 percent,
60-70 percent,
realization.
consumption
while
the total
approach
however,
feedback
increase
in
(CMFB)
to approxi-
area increase
B. Class AB Single-Stage
Reduction
differential
an efficient
limits
Vcmz. In the
V,mO by an
voltage.
is about
single-ended
of the quiescent
power
that
the
quiescent
power
precisely
controlled
consumed
by the op
schematic
of the class AB amplifier
used in the filter
without CMFB circuit. This circuit is a modified version of
a previously proposed structure [1 8]. The circuit is perfectly
symmetric about the axis A A. For zero applied differential input
signal, the two matched
current
sources 1
uniquely
define the circuit quiescent current level. In fact,
if for simplicity
it is assumed that the four NMOS input
devices
are identical,
PMOS
devices,
II=
current
11 goes practically
the circuit
is
sources in
to zero. As a consequence,
half
voltage applied.
to the outputs
discharge
the load
capacitance.
charge
The comparison
and
between
the currentvoltage
characteristic
of a class A and a class
AB amplifier
can be seen from Fig. 5(b). Notice that, in the
example shown, for an input voltage of 300 mV the current
in the class AB circuit is already several times larger than
the current
sentative
of the actual
behavior
reported
in
this paper.
Although
of Fig.
current
mirrors
for
this point,
the linear
region
of operation,
the value of
possible
VCW1is important
performance
all
point
current
in
differential
therefore
enter
level be-
the four
or M4 or both)
comes practically
constant independently
of the value of
the input voltage. This problem becomes more and more
severe as the supply voltage is reduced, and represents the
limiting
factor to the maximum achievable peak current for
since
branches
in
current
12 = 1. Furthermore,
then
consumption
Configuration
the output
switched-capacitor integrator,
between
the two
configuration,
in order to obtain
in the op amp.
threshold
supplies,
In fact,
voltage
the best
increasing
as allowed
by the fully
level.
in-
CASTELLO
AND
GRAY:
MICROPOWER
SWITCHED
CAPACITOR
1125
OUT(-)
1,
4Jl A
3p A 2pA
I pA
M15
-400
-200
v ,.
M13
/1
Fig. 5.
By utilizing
a class All
configuration,
a saving on the
?OUT
.1
--ID
vBIAS 2
and
makes
the
problem
class AB
operation.
of
designing
is particularly
for
stable
compensation
single-stage
tions,
closed-loop
is required.
topology,
is the
reduced
response,
The
main
particularly
output
However,
problem
as shown below,
so that
due
of
the
(vG5-vT~
,
(vG~ -VT
Required
100m
7oomv
VB, A~
VT
the significance
of this
280m
VT
1 9Volts
(b)
Fig. 6.
of adaptively
)15
design.
Biasing
in the amplifier
(a)
applica-
section.
The necessity
mirrors
T 13
to the cascode
the amplifier
must be able to deliver all of the peak input
current to the load, without
unacceptably
compromising
the output
voltage swing. This requires use of a novel
biasing scheme for the cascode devices as explained in the
C. Dynamic
no extra
drawback
for low-voltage
swing
devices.
following
,*
rejec-
CL
the
suitable
M15
GS
biasing
is illustrated
of Fig.
The numbers
of
of
the
possible
circuit
the
first
1126
IEEE JOURNAL
OF SOLID-STATE
CIRCUITS,
VOL.
sC-~0,
NO.
6, DECEMBER1985
1,( I )(2pA-90#A)
M20
1,(?
OUT(+)
(-)
124
JI,
M30
lrM60A
M19
Fig. 7,
Complete
of NMOS
mirror.
M15
M9
,
biased current
M13
l-
Fig. 8.
M25
M21
dynamically
--lC
27-
M 10
lr-
schematic
M60B
that both
quiescent
must
during
be kept
the entire
in the saturation
transient.
This require
column
cases differs
of M13.
Notice
shown
that
CM
a %alUe of V~L4s*
than
voltage
to the value
of operation
greater
threshold
or equal
region
in the second
performance
The solution
of the circuit.
to the problem
Fig. 9.
to simultaneously
capability.
obtain
optimum
variable
A simple
the
drive
t) during
current
2 PA
some margin
of safety in the ~~~ of Ml 3 even in the
presence of process variations.
Fig.
current
lJ
i
\/ -
transient
LP
8 shows
common-mode
the
entire
feedback
amplifier
schematic
and illustrates
ing currents,
the dynamic
biased
ated.
biased
There
current
mirrors,
cascode
current
operation
of
mirrors
without
dynamically
of
D. Dynamic
of the linear
region
with
its drain
one threshold
voltage
swing, increases the noise, and slows down the op. amp.
These are particularly
undesirable effects in a low-voltage
low-power
transients,
such a biasing
system.
The
circuit.
circuit
differential
lower than its gate. This bias condition gives the maximum
possible output swing while, at the same time, guarantees a
design
Besides requiring
limits the output
reported
here
uses
switched-capacitor
CMFB circuit similar to one proposed
by Senderowicz
et al. [3]. A simplified
schematic of the
circuit architecture
used in this design is shown in Fig. 9.
Capacitors
Cl
and C2 provide
an ac feedback
path from
scheme is called dynamic biasing. Notice that, in actuality, the aspect ratio of M30 must be smaller than shown in
the two outputs of the op amp VOI and VOZto the feedback
node A. The common-mode
gain from node xl to the
the above
output
example
due to body
gain
CASTELLO
from
the
AND
GRAY:
MICROPOWER
SWITCHED
constant
value
ferential
gain
The
value
dc
however,
is ideally
output
while,
of
voltage
is kept
is almost
unaffected
TABLE I
AMPLIFIER DEVICE SIZES
that
at an almost
by the CMFB
the common-mode
1127
CAPACITOR
output
circuit.
voltage
DEVICE
Z(#m)
L(pm)
Ml
M2
M3
M4
M5
M6
M7
M8
M9
MIO
Mll
M12
M13
tv14
M15
M 16
M17
M 18
M 19
M 20
M71
M 22
M 23
M 24
M 25
M 26
M 27
M 30
180
180
140
140
150
150
200
200
22
22
29
29
22
29
22
29
29
22
22
29
70
6
28
6
6
is,
voltages
common-mode
these
voltages
switched-capacitor
on the phase
output,
to
and to periodically
compensate
integrator
for
re-
leakages.
In
opposite
to that
associated
circuit
is particularly
with
the input
signal.
This CMFB
low-power
applications
for two main reasons. First, it does
not require any extra power consumption,
with the excep-
..-
amps.
output
the
Second,
swing
it
does not
degrade
capacitor
Cl
and
C2 is not
limited
the
differential
performed
by
Although
the maximum
current
the voltage
CORE
AMPLIFIER
(o-5
100I.IW
output
UNITY
are guaranteed
maximum
device
speed.
channel
It
to have a positive
is guaranteed
turns
lengths
speed considerations,
out
that
the above
is also desirable
as explained
polarity
to always work
from
volts
Quiescent
DIFFERENTIAL
circuit
2:
6
28
6
circuit
-.
TABLE II
AMPLIFIER SPECIFICATIONS
signal it is limited
to 21 (about 2 p A). This makes the
CMFB circuit unacceptably
slow for the case of a negative
common-mode
output transient. However, by chosing the
1:
6
6
9
12
6
14
9
12
6
14
by
supplies.
can supply
:
6
6
6
6
10
10
7
7
10
7
6
6
GAIN
SPECIFICATIONS
supply)
Power
GAIN
>
2 MHz
noise
140
NOISE
of
and
OUTPUT
10000
FREOUENCY
at its
choice
Dissipation
nV/fi
O 5 Volts
SWING
300
E. Noise Considerations
consumption
optimum
both
tend
of the amplifier
low
to
voltage
noise performance
large as possible.
be as simple
the
complicated
than
the classical
For
structure
referred
should
noise due
source-coupled
pair
by 4, when
since their
noise propagates
referred
back
only
to the input
through
Inferred
frorh
hlter
m,lsz
measurement
power
devices should be as
the input
low
range.
SUP DIY
is of particular
and
dynarmc
the input
Furthermore,
as possible,
supply
degrade
from
concern
lKHz
whfte
50 nVlfi
node,
signal propagates
through
noise produced by Ml- M8
of one n plus one p device
a source-coupled
pair.
the devices, other than the
First notice that, as in the
therefore
divided
their
noise
by 4 when referred
this would
not
power
contribution
should
Notice
be
that
was operated
length
of the current-mirror
devices should
be
current
mirrors
(while
the devices
in
the n-type
1128
IEEE
JOURNAL
OF SOLID-STATE
CIRCUITS,
VOL.
&utFig. 10.
current
mirrors
circuit
without
performance.
devices other
l/~
length
overall
and white
noise
by all
15 percent
components
while
of the value
channel
the
the frequency
40 percent
minimum
degrading
In this design
of the total
achievable
by
at
is kept
using
devices. It is interesting
all
to note
that, to achieve this result, the device length is such that the
n-type current mirrors are slower than the p-type ones.
As a final point notice that since the cascode devices
M15,
nel length
noise contribution,
their chan-
requirement)
thereby
improving
the frequency
response.
F. Op Amp Summary
The device sizes for the circuit of Fig. 8 are shown in
Table I, and the main amplifier
performance
for a total
supply
Table
II.
measured
Some
of
directly
the entries
but inferred
dissipation
on
the
is shown in
table
where
not
IV.
PROTOTYPE
FILTER
Fig. 11.
DESCRIPTION
elliptic
h
op amp, a low-pass
built
A
and will
full
capacitor
schematic
filter
achievable
switched-capacitor
be described
for
is shown
filter
was
filter
the realized
low-pass
10. It
switched-
is a fifth-order
with
four
transmission
next.
in Fig.
Chip microphotograph.
[15]
switched-capacitor
associated
with
and
utilizes
integrators
the ladder
zeros that
requires
parasitic-free
[4]. The
structure
6-dB
bottom-plate
signal
loss
is compensated
by
CASTELLO
AND
GRAY:
MICROPOWER
~2.5V,
SWITCHED
25 C,
1129
CAPACITOR
fclock
128 KHz
kHz
(a)
(a)
.20
20
:
.?
Z
~
.40
=
K
3
z
60
60
,
0
Frequency
10
( kH z )
800
(b)
Fig. 12.
neqotwe
40 -
(a) Detailed
20
adding
an extra sampling capacitor
at the input
gives a gain close to O dB in the passband. This
inputs
hand,
at frequencies
no extra
amplification
at all output
and integrated
a resistive
from
low-power
to drive a capacitive
a 5-V supply
two
the output
buffer
signal off-chip,
amplifier
load of 10 kfl
with
supplied
differentially
to
to single-ended conversion
a new low-voltage
supplied
and
the two-clock
complements
transmission
gates which are
designed
which
causes
was designed
The amplifier
was
and
capacitor
is almost
lation
of
the
oxide
perfectly
spurious
100
layer.
Positive and negative PSRR: (a) in the O-6 kHz range, and (b)
in the 1100 kHz range.
The power
level in both
the filter
of the picture
buffer
is the fifth-order
filter
the output
circuits
of the filter
are necessary
from
outside
part
designed
to
off-chip
differentially.
The top portion of the chip shows some test
structure. Although
the test buffer amplifier was functional
and showed performance corresponding
to the design values
[16], due to some layout errors in the interconnections
of
the buffers
bypassed
using
at the filter
and
some
output
these circuits
source
followers
reported
externally
biased
had
to be
were taken
as output
buffers.
time to
eo
&
60
(kHz)
(b)
Fig. 13.
some peaking
the bandedge
40
Frequency
thickness
symmetrical
signals
of
1000 ~.
The
to maximize
coupled
into
chip
cancel-
the syst,em.
Some small asymmetries were impossible to avoid (crosscoupled devices), but they were all limited
to the metal
V.
EXPERIMENTAL
RESULTS
rejection
for both
interval
for
kHz.
the interval
1-100
At
program
supplies
in Fig.
the PSRR
is well
1130
IEEE
*IO%
Supply
Voltage
JOIJRNAL
OF SOLID-STATE
CIRCUITS,
DISTORTION
Variation
1 KHz
,
o15~
012 -
009
input
signal
~55v
006
003
000
-003
0
z
.oo~
-009
::::~
VOL.
10
05
15
25
20
30
35
(a)
.90
1
1
2345678
Fig, 15,
Output
Voltage
PP
(d! fferentiol)
(V)
TABLE III
SUMMARY
Frequency
PERFORMANCE
I
10
OF THE FILTER
25 C +2.5
(kHz)
elk
128 KHz
1
PARAMETER
(b)
VALUE
CONDITION
I
Fig. 14.
MINIMUM
POWER
DISSIPATION
PSRR
bandedge;
however,
that can be
TOTAL
it is only about
+0.01
dB
HARMONIC
?Opv
NOISE
WEIGHTED
SWING
<1%
THD
DIFFERENTIAL
behaves
linearly
the supplies.
helps produce
A summary
The linearity
of the CMFB
are larger
circuit
also
CM ES SAGE
IDLE
OUTPUT
distortion
dB
52
dB. No appre-
70 pv.
harmonic
56
SUPPLY
DISTORTION
+SUPPLY
detected
lKHz
lKHz
performance
is shown
DYNAMIC
3 l[RMS)V
RANGE
by typical commercially
manufactured
filters operated from
~ 5-V supplies and requiring
1015 times more power
than this device. Another
point of interest is the low
distortion
achieved in the filter
73 dB for a 2-V rms
differential
the
fully
results
l-kHz
output
differential
of Fig.
topology
16, which
pure sinusoidal
as demonstrated
input
spectrum
by
the
for a
differential
output. This plot is obtained by feeding one of
the two filter outputs directly
to the spectrum analyzer
without
passing through
the differential
to single-ended
converter. As can be seen, the only appreciable harmonic is
the second one. On this plot the harmonic content of the
differential
totally
output
canceled
is depicted.
The
second
harmonic
is
of the struc-
CASTELLO
AND
GRAY:
MICROPOWER
SWITCHED
1131
CAPACITOR
SE
FD
Fig. 16 Comparison between the harmonic distortion for a fully differential and a single-ended output for a differential output voltage of
44 p-p v.
t
130pw
012
\
.
0 b8
004
000
004
750,,
IAI n
--+-~- -+-
/
,!,, /
..,l,
O 08
I
Fig.
17.
J.
10
20
30
Variation
signal paths,
differential
For grounded
the clock
for the
inputs,
feedthrough
Flg
18.
......
ml
TOTAL
QUIESCENT
Maximum
SUPPLY
2 MHz)
to accurately
in the
settle in about
CURRENT
the subthreshold
is increased
(mA)
which
case.
,._+
46812
?.
02
on the
devices of the op
to strong inversion
as the
from 60 p A to 3 mA.
For very
low power the filter is still functional but the op amp is not
capable to settling very accurately within one phase of the
clock and peaking
occurs. However,
channel
filter
require-
ment are met over a change in the power level of more than
40 to 1. Here
the power
by varying
the
VI.
An
experimental
described which
communications
supply
voltage
switched-capacitor
of 5 V is used. Good
for proper
log
is approximately
3 V. A smaller value
chip
filter
has
where
PSRR
up to high
dissipation
make this approach
as a part of a large digital/ana-
noise immunity
and power
consumption
reduction
are of paramount
importance.
This circuit
implemented
using 5-pm technology
and requires
approximately
+0.8-V thresholds.
Finally, Fig. 18 shows the total amount
mil 2/pole.
of supply quies-
cent current
that is necessary for the filter to operate
properly when the clock rate is increased. This experiment
was carried out by chosing a value of the clock rate and
then increasing
required
ripple
until
The
the
last
been
CONCLUSIONS
It is, however,
projected
was
700
technology
an area per pole of less than 200 milz can be
achieved without compromising
the level of performance.
ACKNOWLEDGMENT
The cooperation
provided
by INTEL
Corporation
the fabrication
acknowledged.
with
is gratefully
the contribu-
1132
IEEE
and
of the prototype.
JOURNAL
[22]
OF SOLID-STATE
CIRCUITS,
VOL.
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