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1122

IEEE

JOURNAL

OF SOLID-STATE

CIRCUITS,

SC-20, NO. 6,

VOL.

1985

DECEMBER

A High-Performance
Micropower
Switched-Capacitor
Filter
RINALDO

CASTELLO

AND PAUL

R. GRAY,

,4mtract MOS technology scaling requires the use of lower supply


voltages. Analog circuits operating from a low supply and achieving a
sufficiently farge dynamic range must be designed if analogidigital interfaces are to be implemented in scaled technologies. This paper describes a

power-supply

high-performance

power-supply

from

a single

combined

fifth-order

low-pass

5-V supply. The filter

with input-to-output

and switched-capacitor
prototype

switched-capacitor

fabricated

uses a fully

class A B amplifier

common-mode

differential

design, dynamic

operating
topology
biasing,

(CMFB). An experimental

feedback

in a 5- p m CMOS

filter

technology

requires

orlly 350 pW of

channel filter requirements. Typical measured


results are a dynamic range of 92 dB, a supply rejection (PSRR) of 40 dB
over the entire Nyquist range, and a total harmonic distortion (THD) of
73 dB for a 2-V rms dlfferentiaf
output signal. The chip active area is
power

to meet

about

3900 milz.

the PCM

been described
for

INTRODUCTION

PERFORMANCE

of

switched-capacitor

filters

of CMOS operational
amplifiers.
This improvement
has
been particularly
evident in the PCM channel filter application [1][6]. However, the most recent commercial PCM
filter
implementations
still require a power-per-pole
of
1 mW

recently

and

been

standpoint,

operate

shown

from

a ~ 5 V supply.

[20], [21] that,

the absolute

minimum

from

It has

a fundamental

achievable

power

dis-

sipation in a voice-band filter with a dynamic range of 90


dB in a 3-pm technology operated from a +-5 V supply is
less than 1 pW per pole. A large margin for improvement
in power consumption
over existing filter designs is therefore possible in principle.
The realization
of such a reduction,

while

maintaining

have important
operated

high-performance

implications

analog/digital

A second

formance

in the realization

levels,

requiring
rejection,

applications

low-power

limited

dynamic

such as PCM

off a low

have been intended


range

and are not suitable

and

for high-per-

telephony.

This paper

describes a fifth-order
CMOS PCM channel filter operated
from a single 5-V supply and dissipating about 70-pW per
pole which embodies a combination
of circuit techniques
including
input-to-output
class All amplifier
design, fully
differential
topology,
dynamic
biasing,
and switchedcapacitor

common-mode
1O-V

The

commercial

paper

fundamental
low-pass

These techniques

or improved

realizations,

and operating

is organized
limit

to the achievable

available

while
In

IV

discusses

the actual

devices. In Section

test

the

design.

the

structure

of the

low-pass

filter

level

performance

of

Finally,

prototype

Section

sults for both the filter

III

II.

LIMITS

supply.

Section

II

the
for a

range

value in coma new class AB

the core of the


in detail. Section

fifth-order

switched-

which has been used to


achievable

V presents

the

new

some experimental

with

re-

and the op amp which demonstrates

that high performance


in analog circuits
when the supply voltage is reduced.

would

dissipating

of given dynamic

with

operational
amplifier,
which represents
filter reported in this paper, is described
capacitor

pro-

respect to

power dissipation

filter

and compared

with

on a 5-V power

as follows.

switched-capacitor

is computed
mercially

feedback.

comparable

TO POWER DISSIPATION

of battery-

consideration

filters

in the realization

of

is the fact that the technological

scaling of the mainstream


MOS technologies
dictates the
use of lower power-supply
voltages [7]. This fact, and the
need for an analog/digital
compatible
technology, create a
strong motivation
for developing new analog circuit techniques suitable for low-voltage operation.
Recently several circuit approaches to the implementaof

These, however,

can be preserved

AND DYNAMIC

RANGE

interfaces.

important

switched-capacitor

tion

some of them operating

much less power

has steadily improved


during the last several years,
primarily
as a result of improvements
in the performance

about

[8]-[14],
voltage.

applications

current

IEEE

vide performance
I.

HE

FELLOW,

MOS

switched-capacitor

filters

have

Power consumption
VLSI

systems.

reduction

Present

is always a major

commercial

issue in

switched-capacitor

filters consume far more power than the theoretical minimum required. For this reason, this section examines some
fundamental
limitations
to the achievable minimum
power
dissipation
for a low-pass switched-capacitor
filter of given
dynamic range. This analysis has been carried out in detail
in a previous paper [20], [21], and in this section only the
main results are summarized stressing their intuitive interpretation.

Manuscript received October 25, 1985; revised August 1, 1985. This


work was supported by NSG Grants ECS-8023872 and ECS-81OOO12,
The authors are with the Department of Electrical Engineering and
Computer Science, University of California, Berkeley, Berkeley, CA 94720.

0018-9200/85

In present
dc bias
normally

/1200-1122$01

day switched-capacitor

filters,

the quiescent

power drawn by the operational


amplifiers
is
much larger than the dynamic power drawn from

.00 01985

IEEE

CASTELLO

AND

GRAY:

MICROPOWER

SWITCHED

CAPACITOR

1123

+v~~
+VSs

100

130

120
/

110
/

+ (dB)

-%s

100

4-

---

---

-vs~

---

--

90

Fig. 1.

Minimum

I
1
I

power dissipation for a switched-capacitor integrator,

I
t
$
1

80
/
the supply

in order

to charge and discharge

the sampling

1
70

and integrating
capacitor within the filter. We assume for
this analysis, however, that, through improved circuit techniques, the op amp static power dissipation can eventually
be reduced to the point of being negligible with respect to

I
1

/ /
,.-1

,()-2

Mm

the dynamic power. This condition


can be approached, in
principle,
by appropriate
use of class B amplifier architectures. The situation

is then analogous

to that of a CMOS

95dB
Fig, 2,

tor.
pling

one clock

During

period

for a switched-capacitor

phase 1 the positive

capacitor

via the previous

supply

~ is present

switched-capacitor

at the output

integra-

of the integrator,

the

filter

can be obtained

associated
however,

clock

as in a CMOS

to the

A very large improvement

of the

which

gate. As an example

this power is on

frequency

band
should

of

interest,

the

size of

then be reduced.

tor is, however,

constrained

the

integrating

The integrating

to be larger

than some mini-

mum value in order to achieve the required

dynamic

due to the kT/C

noise contribution.

should

intuitively

if it is noticed

correct

This

are more efficient

to the supply

III.

voltage

range
appear

that, since in a switched-

band

Part of the disresults is due to

dominate

in typical

and l/~

for a factor

is therefore

noise).

of two or so.

feasible

if op amps

and achieve a signal swing closer

are designed.

OPERATIONAL

As just illustrated,

capaci-

of the filter

filter with a 3.4-kHz

the op amp (white

is proportional

the order of 12 pW per integrator


for a typical switchedcapacitor voice-band filter.
In order to reduce the power consumption,
for a given
capacitor

with

can only account

to the frequency

that the power dissipation


of the signal

and not

to

given the value

the fact that the above analysis neglects the noise contribuThis,

Here it is important

frequency

8.51JW

three orders of magnitude


more power.
crepancy between theoretical
and actual

times

emphasize

,04

bandwidth
is shown. A dynamic range of 95 dB requires
only 8.5 pW of power. Commercially
available switchedcapacitor
PCM filters of similar performance
use almost

tion

of the signal.

(pW)

edge. In Fig. 2 the case of a fifth-order

minimum
power dissipation
is proportional
to the maximum energy that can be stored on the integrating
capacitor
the frequency

Power

,.3

lot

integra-

charges the sam-

tor, and during phase 2 the energy stored on the sampling


capacitor
is discharged
by the feedback action of the
second op amp through the integrating
capacitor to the
negative supply. Assuming
that a full swing sinusoid of
frequency

10

Minimum power dissipation versus dynamic range for a 3,4-kHz


fifth-order low-pass switched-capacitor filter

logic gate. Fig. 1 shows the flow of power from the supplies
during

AMPLIFIER

ARCHITECTURE

op amp power consumption


filters.

tends to

Next the design of a low power

class AB op amp is described.


The

new

concepts.

circuit

The first

configuration
is fully

is based

differential

on four

architecture

main
which

as energy stored on

results in better swing and supply rejection. A class AB


structure is used for low power dissipation.
A single-stage

capacitors,
increasing
the maximum
energy that can be
stored is equivalent
to increasing
the maximum
signal
energy level that the filter can process and therefore is
equivalent
to increasing the filter dynamic range. In fact,

topology with dynamically


biased cascode is used for optimum
current
drive
capability
and output
swing. A
switched-capacitor
common-mode
feedback is used for
minimum
power. These feature will be discussed in detail

the dynamic

in the following

capacitor

filter

signals, are represented

range

is related

to the ratio

of maximum

stored energy to thermal energy, kT dictating a minimum


capacitor
size for a given supply voltage to achieve the
required filter dynamic range.
By combining

these two results,

and applying

them

to

the case of a low-pass filter implemented


using switchedcapacitor
integrators,
a plot of achievable signal-to-noise
ratio versus minimum
power dissipation
for a low-pass

sections.

A. Fully Dijjferential

Topology

A fully differential
switched-capacitor
integrator is shown
in Fig. 3. The two input voltages ~~ and ~; are symmetrical with respect to the common-mode
input voltage V&l,
and the two output voltages VO+ and VO- are symmetrical

1124

IEEE

JOURNAL

OF SOLID-STATE

CIRCUITS.

SC-20, NO. 6. DECEMBER1985

VOL.

(-)

Ou

1A

v2-

Fig. 4.
Fig, 3.

with

respect

This

structure

Fully differential

to the common-mode
doubles

the

output

output

voltage

swing,

which

VCMO.
is of

paramount
importance
for low-voltage
applications,
and
provides a reduction on the sensitivity to supply and clock
noise so that good PSRR can be obtained without having
to decouple

the input

it is instead

required

in

a simplified

low-voltage
proach

nodes from the supplies

in the single-ended

design.

allows

structure

much

Furthermore,

the designer

value of the input


and

summing

input

a fully

suitable

differential

common-mode

performance.

as

case. This results


more

to independently

and output

VC~O) for optimum

choose

for
apthe

voltages ( PC,,

Although

for maxi-

mum swing VcmOshould be equal to half of the total supply


voltage,
present

the same may not be the case for


design, in fact, V& is higher than

n-channel

threshold

is the increased
this design
circuit
mately

power

of the fully
common-mode

the power

40 percent,

60-70 percent,
realization.

consumption

while

the total

approach
however,

feedback
increase

in

(CMFB)

to approxi-

area increase

with respect to a corresponding

B. Class AB Single-Stage
Reduction

differential

and area requirement;

an efficient

limits

Vcmz. In the
V,mO by an

voltage.

The main disadvantage

is about

single-ended

of the quiescent

power

that

the

quiescent

power

precisely

controlled

by the two matched

consumed

by the op

speed can be obtained by


Fig. 4 shows a simplified

schematic
of the class AB amplifier
used in the filter
without CMFB circuit. This circuit is a modified version of
a previously proposed structure [1 8]. The circuit is perfectly
symmetric about the axis A A. For zero applied differential input
signal, the two matched
current
sources 1
uniquely
define the circuit quiescent current level. In fact,
if for simplicity
it is assumed that the four NMOS input
devices

are identical,

and the same is true

PMOS

devices,

II=

current

11 goes practically

the circuit

is

sources in

to zero. As a consequence,

of the devices in the circuit

half

become cut off and have not

been shown on Fig. 5(a). Current 12, on the other hand,


increases to a peak value which, in principle, is only limited
by the value of the input
is mirrored

voltage applied.

to the outputs

discharge

the load

The same current

and can quickly

capacitance.

charge

The comparison

and

between

the currentvoltage
characteristic
of a class A and a class
AB amplifier
can be seen from Fig. 5(b). Notice that, in the
example shown, for an input voltage of 300 mV the current
in the class AB circuit is already several times larger than
the current
sentative

in the class A circuit.

of the actual

behavior

These values are repreof the circuit

reported

in

this paper.
Although

in the above consideration

the peak value for current

it was assumed that

12 in the class AB circuit

of Fig.

5 is only a function of the applied input voltage, in practice


another limiting
factor is the total supply voltage. In fact as

current

mirrors

for

this point,

some of the devices (Ml

the linear

region

of operation,

the value of
possible

VCW1is important

performance

Vcmz by one n-channel

all

point

have a gain of 1, the quiescent

current

in

differential

therefore

enter

level be-

a 5-V total supply voltage. The achievable value for the


peak current is also strongly dependent on the value of the
input common-mode
voltage Vcm,. An optimum
choice of

the four

is also equal to 1. It follows,

or M4 or both)

and the current

comes practically
constant independently
of the value of
the input voltage. This problem becomes more and more
severe as the supply voltage is reduced, and represents the
limiting
factor to the maximum achievable peak current for

since

branches

in

current

the input stage. The dynamic behavior of the circuit is


shown in Fig. 5.
In response to a large positive differential
input signal,

12 = 1. Furthermore,

then

consumption

the current level increases, the sum of the voltage drops


across devices Ml,
M4, M9, and M14 in Fig. 5 also
increases, until it is equal to the total supply voltage. At

Configuration

amp while retaining


sufficient
using a class AB configuration.

the output

Simplified schematic of the class A B amplifier,

switched-capacitor integrator,

between

the two

configuration,

crease on the achievable

in order to obtain

in the op amp.
threshold
supplies,

In fact,

voltage

the best
increasing

above the middle

as allowed

by the fully

gives more than a threefold


peak current

level.

in-

CASTELLO

AND

GRAY:

MICROPOWER

SWITCHED

CAPACITOR

1125

OUT(-)
1,
4Jl A
3p A 2pA
I pA

M15
-400

-200

v ,.

M13

/1

Fig. 5.

By utilizing

a class All

Active portion of the amplifier for a positive input signal.

configuration,

a saving on the

?OUT

quiescent power dissipation for a given speed can therefore


be achieved. Furthermore,
the low quiescent current level
on the output
devices improves the voltage swing, and

.1
--ID

vBIAS 2

gives a larger dc gain. The class AB structure, however, has


also some disadvantages.
In particular
it tends to be more
complicated,

and

makes

the

problem

class AB

operation.

of

designing

is particularly

tion at high frequencies


gives no high-frequency

for

an effect which can greatly reduce the dynamic range of a


sampled data system due to aliasing effects. Furthermore,
in the present design the load capacitance is enough to
guarantee

stable

compensation
single-stage
tions,

closed-loop

is required.
topology,

is the

reduced

response,
The

main

particularly
output

However,

problem

can be reduced by careful

as shown below,

In order to take full advantage

so that

due

of

the

(vG5-vT~
,

(vG~ -VT

Required

100m

7oomv

VB, A~

VT

the significance

of this

280m

VT

1 9Volts

(b)
Fig. 6.

Output devices of an NMOS current mirror.

of the class AB structure


required to keep both devices in saturation for two different conditions
of operation. In the first column the current
through the two devices is equal to the quiescent value. In
the second column the current through the two devices is
equal to the peak value that occurs during the transient
resulting from applying a full swing signal at the input of
the circuit.

of adaptively

)15

design.

Biasing

in the amplifier

(a)

applica-

section.

The necessity
mirrors

T 13

to the cascode

the amplifier
must be able to deliver all of the peak input
current to the load, without
unacceptably
compromising
the output
voltage swing. This requires use of a novel
biasing scheme for the cascode devices as explained in the

C. Dynamic

no extra

drawback

for low-voltage

swing

devices.

following

,*

rejec-

(beyond the dominant


pole) and
second-stage noise contribution,

CL

the

suitable

Also it has good power-supply

M15

GS

CMFB circuit more difficult.


A single-stage configuration

biasing

is illustrated

the cascode current


by the circuit

of Fig.

6. Fig. 6(a) shows the two output devices of the NMOS


cascode current mirror, which is active for a positive input
signal. Fig. 6(b) is a table of value for the V& VT of the
two devices together with the minimum
value of VB1As2

The numbers

on the table are representative

of

the actual values for the amplifier reported in this paper.


To obtain a large output swing V~~As~ must be as small
as possible,
tees proper

and the minimum


operation

of

the

possible
circuit

value that guaranis, from

the

first

column of Fig. 6(b), equal to 280 mV more than the value


of the threshold voltage of device it413. This is because to
obtain the full gain of the circuit it is necessary to insure

1126

IEEE JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL.

sC-~0,

NO.

6, DECEMBER1985

1,( I )(2pA-90#A)

M20

1,(?
OUT(+)

(-)

124

JI,
M30

lrM60A

M19

Fig. 7,

Complete

of NMOS
mirror.

M15

M9
,

biased current

M13

l-

Fig. 8.

M25

M21

dynamically

--lC

27-

M 10
lr-

schematic

M60B

Detailed schematic of the entire amplifier without CMFB

that both
quiescent

M13 and MIS are in saturation at least in the


state, i.e., when all transients have died away.
For this value of V~~*~~, however, as the output current
increases Ml 3 quickly enters the linear region of operation

and the current limits to a value much smaller than the


peak current in the input stage.
To guarantee full current driving capability
to the load,
M13

must

during

be kept

the entire

in the saturation

transient.

This require

column

of Fig. 6(b), i.e., 1.9 V more than the value of the

cases differs

of M13.

Notice

shown
that

CM

a %alUe of V~L4s*

than

voltage

to the value

of operation

greater
threshold

or equal

region

in the second

V~I~s2 in the two

the bias voltage V~I~s2 is used between the two extreme


cases shown on the table will result in a severe degradation
of the overall

performance

The solution

of the circuit.

to the problem

Fig. 9.

to simultaneously
capability.

obtain

optimum

variable

bias scheme is shown in Fig. 7, The input


the transient

A simple

the

swing and full

drive

t) during

way to achieve such a

is assumed to varies from

current
2 PA

Sirnphfied dynamic common-mode feedback cmcult

some margin
of safety in the ~~~ of Ml 3 even in the
presence of process variations.
Fig.

is to vary V~I~sz during

current
lJ

i
\/ -

by more than 1.6 V. In a fixed bias condition,

therefore, there is a basic conflict between maximum


current driving and maximum
swing and whichever value of

transient

LP

8 shows

common-mode

the

entire

feedback

amplifier

schematic

and illustrates

ing currents,

that are necessary for the proper

the dynamic

biased

ated.
biased

There

current

mirrors,

are two p-type

cascode

current

operation

of

can be easily gener-

and two n-type

mirrors

without

how the two track-

dynamically

at the top and bottom

of

to a peak value of 90 PA as an example. M9, M13, and


M15 makeup
the NMOS current mirror and for simplicity
are shown to have the same size. M30 has an aspect ratio 4
times smaller than the other devices. Assuming
that the

the figure. As an example, consider the bottom right one.


The current in M30 is forced to track the current in M9 by
mirroring
12 from the top via current mirror M12, M27.

current on M30 and M9 is the same, a high swing cascode


[17] current mirror results where M13 is biased at the edge

D. Dynamic

of the linear

region

with

its drain

one threshold

voltage

Common - Mode Feedback

The main drawback

associated with the fully

approach is the need for a CMFB


extra area and power, the CMFB

current gain of 1 in the mirror and a very large output


resistance at the output node. By forcing M30 and M9 to

swing, increases the noise, and slows down the op. amp.
These are particularly
undesirable effects in a low-voltage

carry the same current during the all transient,


the full
90-pA current driving capability
is achieved together with
the same output swing of a fixed bias cascode biased to
carry only 2 p A of current. Since the voltage at the gate of

low-power

the cascode device varies during

transients,

such a biasing

system.

The

circuit.
circuit

differential

lower than its gate. This bias condition gives the maximum
possible output swing while, at the same time, guarantees a

design

Besides requiring
limits the output

reported

here

uses

switched-capacitor
CMFB circuit similar to one proposed
by Senderowicz
et al. [3]. A simplified
schematic of the
circuit architecture
used in this design is shown in Fig. 9.
Capacitors

Cl

and C2 provide

an ac feedback

path from

scheme is called dynamic biasing. Notice that, in actuality, the aspect ratio of M30 must be smaller than shown in

the two outputs of the op amp VOI and VOZto the feedback
node A. The common-mode
gain from node xl to the

the above

output

example

due to body

effects and to guarantee

is very large and negative, while the differential

gain

CASTELLO

from
the

AND

GRAY:

MICROPOWER

SWITCHED

node A to the output


common-mode

constant

value

ferential

gain

The

value

dc

however,

is ideally

output

while,
of

zero. This implies

voltage

is kept

at the same time,

is almost

unaffected

TABLE I
AMPLIFIER DEVICE SIZES

that

at an almost

the op amp dif-

by the CMFB

the common-mode

not well defined.

1127

CAPACITOR

output

circuit.

voltage

It depends on the initial

DEVICE

Z(#m)

L(pm)

Ml
M2
M3
M4
M5
M6
M7
M8
M9
MIO
Mll
M12
M13
tv14
M15
M 16
M17
M 18
M 19
M 20
M71
M 22
M 23
M 24
M 25
M 26
M 27
M 30

180
180
140
140
150
150
200
200
22
22
29
29
22
29
22
29
29
22
22
29
70
6
28

6
6

is,

voltages

across capacitors Cl and Cz. The purpose of Cl. and C2.


is to establish the voltage drops across Cl and C2 that gives
the desired
store

common-mode

these

voltages

switched-capacitor
on the phase

output,

to

and to periodically

compensate

integrator

for

re-

leakages.

In

Clo and C2. are switched-in

opposite

to that

associated

circuit

is particularly

with

the input

signal.
This CMFB

suited for low-voltage

low-power
applications
for two main reasons. First, it does
not require any extra power consumption,
with the excep-

..-

tion of the replica circuit that defines the proper value of


VA (M3, 1, and M6) which is, however, shared by all the
op

amps.

output
the

Second,

swing

it

does not

degrade

since the level shift operation

capacitor

Cl

and

C2 is not

limited

the

differential

performed
by

Although

the maximum

current

the voltage

that the CMFB

is quite large for a positive

CORE

AMPLIFIER
(o-5

100I.IW

output

UNITY

are guaranteed

maximum
device

speed.

channel

It

to have a positive

is guaranteed
turns

lengths

speed considerations,

out

that

the above

is also desirable

as explained

polarity

to always work
from

volts

Quiescent

DIFFERENTIAL

circuit

2:
6
28
6

circuit

signal, for a negative

device sizes in such a way that the p-type current mirrors


are faster than the n-type current mirrors, all common-mode
transients

-.

TABLE II
AMPLIFIER SPECIFICATIONS

signal it is limited
to 21 (about 2 p A). This makes the
CMFB circuit unacceptably
slow for the case of a negative
common-mode
output transient. However, by chosing the

and the CMFB

1:
6
6
9
12
6
14
9
12
6
14

by

supplies.
can supply

:
6
6
6
6
10
10
7
7
10
7
6
6

GAIN

SPECIFICATIONS
supply)
Power

GAIN

>

2 MHz

noise

140
NOISE

of
and

OUTPUT

10000

FREOUENCY

at its

choice

Dissipation

nV/fi

O 5 Volts

SWING

300

E. Noise Considerations

The noise performance


since

consumption
optimum

both
tend

of the amplifier

low
to

voltage

noise performance

large as possible.
be as simple

the

complicated

than

the classical

For

structure
referred

should

noise due

source-coupled

pair

(eight devices instead of two). However, the noise power


associated with each one of the eight input devices should
be divided

by 4, when

since their

noise propagates

referred

back

only

signal paths while the input


both. The overall input referred
is, therefore, equivalent to that
which is comparable
to that of
The noise contribution
of all
input ones, is next considered.

to the input

through

Inferred

frorh

hlter

m,lsz

measurement

power

devices should be as

the input

and the input

low

range.

to all the devices, other than the input ones, should be


made as small as possible (ideally negligible).
~
In this design, the input structure (Ml M8) is much
more

SUP DIY

is of particular
and

dynarmc

the input

Furthermore,

as possible,

supply

degrade

from

in the next section.


AREA

concern

lKHz
whfte

50 nVlfi

node,

one of the two

signal propagates
through
noise produced by Ml- M8
of one n plus one p device
a source-coupled
pair.
the devices, other than the
First notice that, as in the

case of the input


and

therefore

divided

devices, they only affect one signal path

their

noise

by 4 when referred

this would

not

power

contribution

should

back to the input.

be the case if the amplifier

Notice

be
that

was operated

single ended. Furthermore


the ratio of the noise power
contributed
by one of these devices over that of an input
transistor
is inversely proportional
to the ratio of their
transconductances
for the white component
and inversely
proportional
to the ratio of the square of the channel
lengths for the l/~ component [19].
In order to simultaneously
reduce both kinds of noise,
the channel

length

of the current-mirror

devices should

be

made as long as possible. This increases the amplifier


voltage gain but reduces the frequency of the first nondominant
pole. However, because of the fact that p-type
devices are slower but less noisy than n-type devices [14], it
is possible to use devices close to minimum
size in the
p-type

current

mirrors

(while

the devices

in

the n-type

1128

IEEE

JOURNAL

OF SOLID-STATE

CIRCUITS,

sC-20, NO. 6, DECEMBER1985

VOL.

&utFig. 10.

current

mirrors

circuit

without

are longer). This achieves good speed in the


appreciably

performance.
devices other

than the input


for both

the same time


within

l/~

length

overall

ones is only about

and white

noise
by all

15 percent

components

while

of the second pole

of the value

channel

the

the noise contributed

the frequency

40 percent

minimum

degrading

In this design

of the total

Full schematic of the low-pass filter prototype

achievable

by

at

is kept
using

devices. It is interesting

all

to note

that, to achieve this result, the device length is such that the
n-type current mirrors are slower than the p-type ones.
As a final point notice that since the cascode devices
M15,

J416 give a negligible

nel length

noise contribution,

their chan-

can be made very short (consistent

requirement)

thereby

improving

with the gain

the frequency

response.

F. Op Amp Summary
The device sizes for the circuit of Fig. 8 are shown in
Table I, and the main amplifier
performance
for a total
supply

of 5 V and 100-I.LA power

Table

II.

measured

Some

of

directly

the entries

but inferred

dissipation
on

the

is shown in

table

where

not

from the filter results. Notice

the very good output swing particularly


for a cascoded
output. The relatively large area is due to the fully differential topology. In fact, the dynamic common-mode
feedback
circuit alone takes more than one-third of the total amplifier area.

IV.

PROTOTYPE

FILTER

Fig. 11.

DESCRIPTION

elliptic
h

order to test the performance

op amp, a low-pass
built
A

and will
full

capacitor

schematic
filter

achievable

switched-capacitor

be described
for

is shown

filter

with the new


prototype

was

filter

the realized

low-pass

10. It

switched-

is a fifth-order

with

four

transmission

total of five op amps. The filter


ladder
architecture,
for its low
variations,

next.
in Fig.

Chip microphotograph.

[15]

switched-capacitor
associated

with

and

utilizes

integrators
the ladder

zeros that

requires

uses the standard active


sensitivity
to parameter

parasitic-free
[4]. The
structure

6-dB

bottom-plate
signal

loss

is compensated

by

CASTELLO

AND

GRAY:

MICROPOWER

~2.5V,

SWITCHED

25 C,

1129

CAPACITOR

fclock

128 KHz

kHz
(a)

(a)

.20
20

:
.?

Z
~

.40

=
K

3
z
60

60

,
0

Frequency

10

( kH z )
800

(b)
Fig. 12.

neqotwe
40 -

(a) Detailed

20

adding
an extra sampling capacitor
at the input
gives a gain close to O dB in the passband. This

inputs
hand,

(less than 6 dB) at the internal nodes near


which degrades the filter linearity
for large

at frequencies
no extra

close to the band edge. On the other

amplification

is needed at the output

the overall noise is reduced.


The two-phase
clock is externally
on-chip
inverters
providing
necessary to drive CMOS
implemented
input
is
differential

at all output

and integrated
a resistive
from

low-power

to drive a capacitive

a 5-V supply

two

the chip, and the


is done off chip.

the output

buffer

signal off-chip,

amplifier

on the chip prototype.

load of 10 kfl

with

node due to the large swing. The

supplied
differentially
to
to single-ended conversion

a new low-voltage

supplied

and

the two-clock
complements
transmission
gates which are

In order to be able to provide

designed

which
causes

was designed

The amplifier

was

load of up to 100 pF and/or

of only 350 pW, and a settling

and

capacitor
is almost

lation

of

the

oxide
perfectly

spurious

100

layer.

Positive and negative PSRR: (a) in the O-6 kHz range, and (b)
in the 1100 kHz range.

The power

level in both

the filter

can be externally controlled.


The central part of the picture
which

of the picture
buffer

and the amplifier

is the fifth-order

filter

has an active area of 3500 mi12. In the bottom


are visible

the output

circuits

the two amplifiers

of the filter

are necessary

from

outside

part

designed

to

the chip. Two

because the signal is taken

off-chip

differentially.
The top portion of the chip shows some test
structure. Although
the test buffer amplifier was functional
and showed performance corresponding
to the design values
[16], due to some layout errors in the interconnections
of
the buffers
bypassed
using

at the filter
and

some

output

these circuits

all the measurements

source

followers

reported

externally

biased

had

to be

were taken
as output

buffers.

time to

Fig. 11. A p-well 5-pm CMOS process was used. The


process allows for a single level of metal and has a minimum channel length of 5 pm, device oxide thickness of 400
layout

eo

or more with a power dissipation

an accuracy of 0.1 percent for a 2.5-V step of less than


3 ps.
A microphotograph
of the experimental
chip is shown in

&

60

(kHz)

(b)
Fig. 13.

some peaking
the bandedge

40

Frequency

passband response. (b) Coarse frequency response


of the filter.

thickness
symmetrical
signals

of

1000 ~.

The

to maximize

coupled

into

chip

cancel-

the syst,em.

Some small asymmetries were impossible to avoid (crosscoupled devices), but they were all limited
to the metal

V.

EXPERIMENTAL

RESULTS

Both detailed and coarse filter response are shown on


Fig. 12 for a total power consumption
of 350 pW. The
supply used is ~ 2.5 V, the clock frequency is 128 kHz. The
total in-band ripple is 0.13 dB. The transmission
zeros are
at 4.5 and 6.7 kHz and the attenuation
in the stopband is
more than 35 dB. This agrees well with the simulation
results obtained
supply

rejection

from the DIANA


ratio

for both

13(a) for the frequency

interval

for

kHz.

the interval

1-100

At

program
supplies

[22]. The power


is shown

in Fig.

O-6 kHz and in Fig. 13(b)


1 kHz

the PSRR

is well

1130

IEEE

*IO%

Supply

Voltage

JOIJRNAL

OF SOLID-STATE

CIRCUITS,

DISTORTION

Variation

1 KHz
,

o15~

012 -

009

input

signal

~55v

006

003

000

-003

0
z

.oo~

-009

::::~

SC-20, NO, 6, DECEMBER1985

VOL.

10

05

15

25

20

30

35

(a)
.90
1
1

2345678

Fig, 15,

Output

Voltage

PP

(d! fferentiol)

Total harmonic distortion as a function


for a l-kHz signal

(V)

of the output voltage

TABLE III
SUMMARY

Frequency

PERFORMANCE

I
10

OF THE FILTER

25 C +2.5

(kHz)

elk

128 KHz
1

PARAMETER

(b)

VALUE

CONDITION
I

Fig. 14.

Changes in the (a) passband response and (b) overall filter


response for ~ 10 percent variation in the supply voltage.

MINIMUM

POWER

DISSIPATION

above 50 dB for both supplies and stays close to 40 dB up


to 100 kHz.
The effect of a ~ 10 percent variation
voltage

PSRR

is in the detail passband

bandedge;

however,

that can be

TOTAL

plot and it occurs at the

it is only about

+0.01

dB

HARMONIC

?Opv

NOISE
WEIGHTED

for a 2-V rms differential

SWING

<1%

THD

DIFFERENTIAL

output at 1 kHz is about 73 dB. The good linearity of the


filter is further shown in Fig. 15 where the total harmonic
distortion
(THD)
at the output for the nominal
supply
voltage of 5 V and a l-kHz input signal is plotted versus
the output signal amplitude.
The THD stays below 40
dB up to a differential
output of approximately
4.6-V peak
(3.3 V rms), i.e., 200 mV from both supply rails. The large
output swing is primarily
due to the use of dynamic biasing
for the cascode devices and to the fact that the CMFB
circuit
than

behaves

linearly

the supplies.

helps produce
A summary

even for signals which

The linearity

the low distortion

of the CMFB

are larger
circuit

also

achieved in the filter.

of the achieved filter

CM ES SAGE
IDLE

OUTPUT

distortion

dB

52

dB. No appre-

70 pv.
harmonic

56

SUPPLY

DISTORTION

ciable change can be seen on a coarse scale. The position of


the zeros is essentially unaffected by the change in supply
voltage. The total C-message weighted integrated
noise is
The total

+SUPPLY

in the total supply

is shown in Fig. 14. The only variation

detected

lKHz
lKHz

performance

is shown

in Table III. The operating conditions


are a total supply
voltage of 5 V, a clock rate of 128 kHz, and a power
dissipation
of 350 pW. The total measured
C-message
weighted noise of 70-pV rms combined with the maximum
differential
output
swing that gives less than l-percent
THD
for a l-kHz
signal of 3.3-V rms gives a dynamic
ranste of 93 dB. which is com~arable
with the value achieved
,

DYNAMIC

3 l[RMS)V

RANGE

by typical commercially
manufactured
filters operated from
~ 5-V supplies and requiring
1015 times more power
than this device. Another
point of interest is the low
distortion
achieved in the filter
73 dB for a 2-V rms
differential
the

fully

results
l-kHz

output

signal. One reason for this is the use of

differential

of Fig.

topology

16, which

pure sinusoidal

as demonstrated

shows the output

input

spectrum

by

the
for a

that gives a 4.4-V peak-to-peak

differential
output. This plot is obtained by feeding one of
the two filter outputs directly
to the spectrum analyzer
without
passing through
the differential
to single-ended
converter. As can be seen, the only appreciable harmonic is
the second one. On this plot the harmonic content of the
differential
totally

output

canceled

is depicted.

The

second

out because of the symmetry

harmonic

is

of the struc-

CASTELLO

AND

GRAY:

MICROPOWER

SWITCHED

1131

CAPACITOR

SE

FD

Fig. 16 Comparison between the harmonic distortion for a fully differential and a single-ended output for a differential output voltage of
44 p-p v.

t
130pw

012

\
.

0 b8

004
000
004

750,,

IAI n

--+-~- -+-
/

,!,, /

..,l,

O 08
I

Fig.

17.

J.

10

20

30

t.ure. On the other hand, a small amount of third harmonic


is now present. The total improvement
in THD from right
to left is more

than 12 dB. The clock feedthrough

two cases was also compared.


gives matched
fully

of the passband response for different power levels.

Variation

signal paths,

differential

For grounded
the clock

for the

inputs,

feedthrough

Flg

18.

......

ml

TOTAL

QUIESCENT

Maximum

SUPPLY

At this clock rate (almost

2 MHz)

to accurately

in the

slope of the curve indicates

case is 30 dB less than in the single-ended

settle in about

amp move from


current

CURRENT

the op amp must be able

200 ns. The change

that the input

the subthreshold

is increased

(mA)

clock frequency versus required supply current,

which

case.

,._+
46812

?.

02

on the

devices of the op

to strong inversion

as the

from 60 p A to 3 mA.

Fig. 17 shows the change in the shape of the passband


for different

values of the total power dissipation.

For very

low power the filter is still functional but the op amp is not
capable to settling very accurately within one phase of the
clock and peaking

occurs. However,

channel

filter

require-

ment are met over a change in the power level of more than
40 to 1. Here

the power

level was varied

by varying

the

VI.
An

experimental

described which
communications
supply

voltage

switched-capacitor

of 5 V is used. Good

frequency and low power


very suitable for operation

for proper

log

is approximately

3 V. A smaller value

chip

filter

has

where

PSRR

up to high

dissipation
make this approach
as a part of a large digital/ana-

noise immunity

and power

consumption

could be used if a low threshold process had been used


instead of the conventional
(not scaled) process featuring

reduction
are of paramount
importance.
This circuit
implemented
using 5-pm technology
and requires

approximately
+0.8-V thresholds.
Finally, Fig. 18 shows the total amount

mil 2/pole.
of supply quies-

cent current
that is necessary for the filter to operate
properly when the clock rate is increased. This experiment
was carried out by chosing a value of the clock rate and
then increasing
required
ripple

the current level in the filter


in the passband was obtained.

until
The

the
last

point to the right shows that with a total supply quiescent


current of about 3 mA, a 50-kHz filter could be obtained.

been

shows that a dynamic range adequate for


applications
can be achieved when a total

bias current to the op amps with an external resistor.


The minimum
value of the total supply voltage required
operation

CONCLUSIONS

It is, however,

projected

was
700

that by using a 3-Pm

technology
an area per pole of less than 200 milz can be
achieved without compromising
the level of performance.
ACKNOWLEDGMENT

The cooperation

provided

by INTEL

Corporation

the fabrication

of one of the chip prototypes

acknowledged.

The authors also acknowledge

with

is gratefully
the contribu-

1132

IEEE

tion of M. WJong and W. E. Matthews


testing

with the layout

and

of the prototype.

JOURNAL

[22]

OF SOLID-STATE

CIRCUITS,

VOL.

SC-20, NO. 6, DECEMBER1985

H, DeMan, J. Rabaey, L. Claesen, and J. Vandewafle, DIANA-SC:


A complete CAD system for switched-capacitor
filters,
in
ESSCIRC
Dig. Tech. Papers, Sept. 1981, pp. 130-133,

REFERENCES
[1]
[2]

[3]

[4]

[5]

[6]

[7]

[8]
[9]
[10]
[11]
[12]

W. C, Black, Jr., D, J. Allstot, and R. A. Reed, A high-performance low-power CMOS channel filter, IEEE J. Solid-State Circuits, vol. SC-15, pp. 929938, Dec. 1980,
Y. A, Haque, R. Gregorian-+ D. Blasco, R. Mao, and W. Nicholson,
A two-chip PCM codec with filters, IEEE J. Solid-State Circui~s,
vol. SC-14, pp. 961969, Dec. 1979.
D. Senderowicz, S. F. Dreyer, J, H, Huggins, C. F. Rahim, and
C. A. Laber, A family of differential NMOS analog circuits for a
PCM codec filter chip; IEEE J, Solid-State Circuits, vol. SC-17,
pp. 1014-1023, Dec. 1982,
R. Gregorian and W, A. Nicholson Jr,, <CMOS switched-capacitor
filters for a PCM voice CODEC, IEEE J. So/id-State Circuits, vol.
SC-14, pp. 970-980, Dec. 1979.
H. Ohara, P. R. Gray, W. M. Baxter, C. F. Rahim, and J. L.
McCrearv A rmecision low-r)ower PCM channel filter with on chirr
power supply ;egulation~ IEEE J. So[id-Sta~e Circuits, vol. SC-15,
rm. 10051013. Dec. 1980.
~. G, Marsh,B. K. Ahuja, M. R. Dwarakanath, P, E, Fleisher, and
V. R, Saari, A single-chip CMOS PCM CODEC with filters)
IEEE J. So/id-State Circuits, vol. SC-16, pp. 308-315, Aug. 1981.
S. Wonz and C. A. T. Safama. ImDact of scalinsz on MOS analog
perform-ace, IEEEJ.
So[id-State ~ircuits, vol. S~-18, pp. 106-11~
Feb. 1983.
B. J. Hosticka, Dynamic CMOS amplifiers, IEEE J. So/id-State
Circuits, vol. SC-15, pp. 887-894, Oct. 1980.
M. G. Degrauwe, J. Rijmenants, E. A. Vittoz, and H. J, De Man,
Adaptive biasing CMOS amplifiers, IEEE J. Solid-State Circuits,
vol. SC-17, pp. 522528, June 1982.
F. Krummenacher, Micropower SC biquadratic cell, IEEE J.
So[id-State
Circuits, vol. SC-17, pp. 507-512, June 1982.
M. G, Degrauwe and W. C. Sansen, A multipurpose micropower
SC filter: IEEE J. Solid-State Circuits, vol. SC-19, .PP.
. 343-348,
June 1984.
H. Pinier, F. Krummenacher, and V, Vafencic, A pP sixth-order
SC leapfrog low-pass filter, in Proc. ESSCIRC
82, Sept. 1982,
on. 223225.
B. J. Hosticka, D. Herbst, B. Hoefflinger, U. Kleine, J. Pandel, and
R. Schweer, Real-time programmable SC bandpass filter, IEEE
J. Solid-State
Circuits, vol. SC-17, pp. 499-506, June 1982.
E. Vittoz and F. Krummenacher. Micro~ower SC filters in Si-zate
CMOS technology
in Proc. ECCTD kO (Warsaw, Poland), ~ol.
1, Sept. 1980, pp. 61-72.
D. J. Allstot, MOS switched capacitor ladder filter, Ph. D.
dissertation, Univ. of California, Berkeley, May 1979.
R. Castello, Low-voltage low-power S.C. signal processing technique, Ph. D. dissertation, ERL Memo. M84/67, Univ. of California, Berkeley, Aug. 1984.
P, R. Gray and R. G. Meyer, Analysis and Design of Analog
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New York: Wiley, 1977.
W. C. Black, High speed CMOS A/D conversion technique,
Ph. D. Dissertation, Univ. of California, Berkeley, Nov. 1980.
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amplifier design, IEEE ~, S;id-State
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vol. SC-14, pp.
774776. Au!z. 1979.
R. Castello a%d P. R. Gray, Performance limitations in switchedcapacitor filters, IEEE Trans. Circuits Syst. vol. CAS-32, no. 10,
pp. 865-876, Sept. 1985.
P. R, Gray and R. Castello, Performance limitations in switchedcapacitor filters, in Proc. IEEE Int. Symp. Circuits Syst. (Kyoto,
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L.

[13]

[14]

[15]
[16]
[17]
[18]
[19]
[20]
[21]

Castello was born in Geneva, Itafy, in


1953. He received the degree of Ingegnere (summa
cum laude) from the University di Geneva,
Geneva, Itafy in 1977, In 1979 he began his
graduate study at the University of California,
Berkeley, where he received the M, S.E.E. degree
in 1981 and the Ph.D. degree in August 1984.
While at the University of California he was a
Teaching Assistant and a Research Assistant.
Both in 1983 and in 1984 he was a Visiting
Professor during part of the academic vear at the
University di Geneva. Since the acadern~c year 198485 he has been a
Visiting Assistant Professor at the University of California, Berkeley,
where he is currently. His main interest is in MOS integrated-circuit
design, particularly in the area of telecommunications and analog\digital
-.
interfaces,
Rinaldo

Paul R. Gray (S65-M69-SM76-F81)

was born

in Jonesboro, AK, on December 8, 1942. He


received the B.S., M. S., and Ph.D. degrees from
the University of Arizona, Tucson, in 1963, 1965,
and 1969, respectively,
In 1969 he joined the Research and Development Laboratory, Fairchild Semiconductor, Pafo
Alto, CA, where he was involved in the application of new technologies for analog integrated
circuits, including power integrated circuits and
data conversion circuits. In 1971 he joined the
Department of Electrical Engineering and Computer Sciences, University
of California, Berkeley, where he is now a Professor. His research interests
during this period have included bipolar and MOS circuit design, electrothermal interactions in integrated circuits, device modeling, telecommunications circuits, and analog/digitaf interfaces in VLSI systems.
Dr. Gray is the coauthor of a college textbook on analog integrated
circuits. He has been corecipient of Best Paper Awards at the International Solid-State Circuits Conference and the European Solid-State Circuits Conference and was corecipient of the IEEE R. W. G. Baker Prize in
1980. He served as Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS from 1977 through 1979, and as Program Chairman of the 1982
International Solid-State Circuits Conference.

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