RS NAND Latch diclock

Dengan menambahkan sepasang gerbang NAND pada input rangkaian dari RS latch,
kita mempunyai 2 tujuan yaitu : normal daripada input-inputnya diinverter, dan
sebuah input yang ketiga pada kedua gerbang dimana kita dapat mensinkronkan
rangkaian.
RS NAND latch yang diclock digambarkan dibawah.
Rangkaian RS latch yang diclock
sangat mirip dengan operasi latch
dasar yang anda lihat pada
halaman sebelumnya. Input S dan
R umumnya berlogika 0,dan harus
dirubah ke logika 1 untuk
mengubah kondisi dari latch.
Bagaimanapun, dengan input
ketiga, faktor baru telah
ditambahkan. Inputnya
dilambangkan C atau CLK,
karena dikontrol oleh sebuah
rangkaian clock, yang digunakan
untuk mensinkronkan beberapa
dari rangkaian latch satu sama
lain. Outputnya hanya dapat
berubah ketika input CLK
berlogika 1. Ketika CLK berlogika
0, input S dan input R tidak
mempunyai efek pada outputnya.
Untuk operasi yang benar, input R
dan input S seharusnya berlogika
1, kemudian input CLK
seharusnya berlogika 1 dan
berlogika 0 kembali. Pada
akhirnya , input yang telah dipilih
seharusnya kembali berlogika 0.

RS latch yang diclock memecahkan beberapa masalah pada rangkaian RS latch, dan
kontrol yang lebih tepat pada proses latch. Bagaimanapun juga, RS latch yang diklok
ini tidak memberikan solusi yang sempurna. Sebuah masalah yang penting pada
rangkaian latch ini dapat dengan mudah berubah pada input S dan input R ketika
masih pada input CLK berlogika 1. Ini mengakibatkan rangkaian untuk sering
berubah state sebelum input CLK yang berubah ke logika 0.

Salah satu cara untuk mengurangi masalah ini adalah menjaga CLK berlogika 0
hampir disemua waktu, dan membolehkan hanya satu perubahan menjadi logika 1.
Bagaimanapun juga, cara ini belum dapat menjamin bahwa latch akan hanya berubah
state saat sinyal clock pada logika 1. Sinyalnya harus mempunyai durasi waktu yang
tepat untuk memastikan semua latchnya mempunyai waktu untuk meresponnya, pada
waktu itu, semua latch dapat merespon semua perubahan.
Jalan yang terbaik adalah memastikan latchnya hanya dapat mengubah outputnya
pada satu siklus clock. Halaman berikutnya akan ditunjukkan sebuah rangkaian yang
memecahkan masalah ini dengan mudah, dengan berubah state hanya pada sebuah
transisi tertentu, ujung dari clock.

Edge-Triggered RS Flip-Flop
Untuk mengatur clocked RS latch untuk edge triggering, kita sebenarnya harus
menggabungkan dua rangkaian clocked latch yang identik, tetapi harus
mengoperasikannya berlawanan untuk setengah sinyal clock. Rangkaian yang
dihasilkan disebut sebuah flip-flop, karena outputnya dapat flip dan kemudian flop
kembali. clocked RS latch juga sering disebut sebagai flip-flop, meskipun lebih tepat
sebagai sebuah rangkaian latch.
Kedua bagian flip-flop juga dikenal sebagai master-slave flip-flop, karena input latch
beroperasi sebagai tuan/master, sedangkan bagian output tunduk kepada master
selama setengah setiap satu siklus waktu/clock cycle.
Edge-triggered RS NAND flip-flop dapat ditunjukkan dibawah ini.

Edge-triggered RS flip-flop sebenarnya terdiri dari 2 buah rangkaian RS latch, seperti

ditunjukkan seperti diatas. Bagaimanapun juga, inverter dihubungkan antara dua buah
input CLK yang memastikan bahwa dua buah bagian akan bekerja selama berlawanan
setengah dari siklus waktu. Ini kunci operasi dari rangkaian.

Jika kita memulai dengan input CLK berlogika 0, input S dan input R diputuskan dari
input(master) latch. Bagaiamanpun juga, perubahan apapun tidak dapat
mempengaruhi kondisi terakhir dari output.
Ketika sinyal CLK berlogika 1, input S dan input R tidak dapat mengontrol keadaan
dari input-input latch, seperti satu buah rangkaian RS latch telah dipelajari.
Bagaimanapun juga, pada waktu yang sama sinyal CLK yang dimasukkan output
(slave) latch mencegah kondisi input latch terpengaruh. Maka, tidak ada perubahan
pada sinyal input R dan input S yang berjalan bila CLK berlogika 1, tidak terbut are
not reflected at the Q and Q' outputs.
Ketika CLK jatuh kembali ke logika 0, input S dan input R akan diisolasi dari input
latch. Pada waktu yang sama, sinyal CLK yang diinverter sekarang membolehkan
keadaan sekarang dari input latch untuk mencapai output latch. Maka, output Q dan
output Q' hanya dapat berganti keadaan ketika sinyal CLK jatuh dari logika 1 ke
logika 0. Ini dikenal sebagai falling edge dari sinyal CLK l; maka disebut edgetriggered flip-flop.
Dengan mempunyai master-slave dan flip-flop edge-triggered, kita sudah dapat
memastikan bahwa kita mempunyai kontrol momen yang tepat ketika semua flip-flop
akan berubah keadaan. Kita juga mempunyai banyak waktu agar master latch untuk
merespon sinyal input, dan agar sinyal input berubah dan mengatur sesuai keadaan
sebelumnya.
Masih ada satu problem yang belum diselesaikan: kemungkinan keadaan race: yang
mungkin terjadi jika kedua input S dan input R berlogika 1 ketika CLK jatuh dari
logika 1 ke logika 0.
Solusinya dengan menambahkan feedback dari slave latch menuju master latch.
Rangkaian yang dihasilkan disebut JK flip-flop.

FLIP-FLOP JK
Untuk mencegah kemungkinan keadaan "race" yang terjadi jika kedua input S dan
input R berlogika 1 dan input CLK turun dari logika 1 ke logika 0, kita harus
mencegah salah satu dari input mempengaruhi master latch pada rangkaian. Pada
waktu yang sama, kita juga ingin flip-flop tersebut berganti kondisi pada setiap saat
input CLK " falling edge". Maka dari itu, input S atau R perlu dimatikan tergantung
pada keadaan sekarang dari slave latch output.
Jika output Q berlogika 1 (flip-flopnya dalam keadaan "Set"), input S tidak dapat
merubah kondisi itu. Maka dari itu, kita dapat mematikan input S tanpa perlu
mematikan flip-flop. Di samping itu, jika output Q berlogika 0 (flip-flop dalam
keadaan Reset), input R dapat dimatikan tanpa menimbulkan kerusakan. Jika dapat
menyelesaikan tanpa ada kerusakan, sudah dapat memecahkan masalah keadaan
"race".

Rangkaiannya dapat digambar dibawah ini. Pada RS flip-flop akan ditambahkan 2

jalur baru dari output Q dan output Q' menuju ke input gate sebenarnya. Mengingat
bahwa sebuah NAND dapat mempunyai banyak input, sehingga tidak menyebabkan
masalah. Untuk membedakan input dari RS maka S digantikan J, dan R digantikan K.
Keseluruhan rangkaian disebut JK flip-flop.

Pada umumnya, JK flip-flop mirip dengan RS flip-flop. Output Q and output Q' akan
berubah state pada saat sinyal CLK jatuh , dan input J & K akan mengontrol output
yang akan datang. Tetapi terdapat beberapa perbedaan penting.
Karena satu dari dua input yang selalu didisabled sesuai dengan keadaan output yang
telah dicapai oleh flip-flop, master latch tidak dapat berganti keadaan sebelumnya dan
maju jika input CLK berlogika 1. Meskipun begitu, input yang dienabled inputnya
dapat mengubah keadaan dari master latch sekali, setelah itu latch tidak dapat berubah
lagi. Ini yang tidak benar dari flip-flop RS.
Jika kedua input J dan input K berlogika 1 dan sinyal CLK berjalan terus, output Q
dan output Q' akan berubah keadaan untuk setiap falling edge dari sinyal CLK.
( rangkaian master latch circuit akan berubah keadaan untuk setiap rising edge dari
CLK.) Kita dapat menggunakan karakteristik ini untuk memanfaatkannya dalam
beberapa cara. Sebuah flip-flop yang dibuat khusus untuk beroperasi dengan cara ini
disebut (Toggle) flip-flop.
Flip-flop JK harus diedge triggered untuk bekerja.
Karena perilaku dari Flip-flop JK dapat seluruhnya diduga dalam segala kondisi,
maka Flip-flop tipe inilah yang paling banyak digunakan dalam desain rangkaian
logika. RS flip-flop hanya digunakan pada aplikasi dimana dapat dipastikan bahwa R
dan S tidak berlogika 1 pada waktu yang sama.
Pada halaman berikutnya, kita akan melihat konfigurasi penting. Kita akan melihat
banyak flip-flop atau latch dapat disatukan untuk mengasilkan fungsi atau operasi
yang berguna

D Latch
Satu variasi rangkaian RS latch yang berguna adalah Data latch, atau D latch. Seperti
yang ditunjukkan pada diagram logika dibawah ini, D latch dibangun dengan
menggunakan input S yang diinverter S sebagai sinyal input R. Input disimbolkan "D"
untuk membedakan operasi ini dengan tipe latch yang lain. Hal ini tidak berbeda
bahwa sinyal input R diclock dua kali, sejak sinyal CLK akan membolehkan sinyalsinyal untuk lewat melalui kedua gerbang itu atau tidak lewat.
Sebagai perbandingan, kita dapat mereview RS NAND latch .

Pada D latch, jika input CLK

berlogika 1, output Q akan selalu
mengeluarkan logika sesuai input
dari D, tidak mempedulikan
perubahannya. Ketika input CLK
jatuh ke logika 0, kondisi terakhir
dari input D terkurung dan
disimpan pada latch, untuk
digunakan rangkaian lain yang
membutuhkan sinyal ini.
Karena input D juga diinverter
untuk menghasilkan sinyal untuk
mereset latch, rangkaian latch ini
tidak mengalami kondisi "race"
disebabkan semua inputnya
berlogika 1 secara bersamaan.
Maka rangkaian D latch dapat
digunakan dengan aman pada
rangkaian apapun.
Meskipun D latch tidak harus diedge triggered untuk operasi yang aman, dalam
beberapa aplikasi dimana edge-triggered flip-flop D tidak diinginkan. Hal ini dapat
dicapai dengan menggunakan sebuah rangkaian D latch sebagai bagian master dari
flip-flop RS. Kedua tipe tersebut berguna, sehingga keduanya dibuat secara komersial.
Selain perubahan dalam rangkaian inputnya, sebuah Flip-flop D bekerja seperti Flipflop RS .

Introduction - Basic Flip-Flop Circuit

A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These
flip-flops are shown in Figure 2 and Figure 3. Each flip-flop has two outputs, Q and
Q', and two inputs, set and reset. This type of flip-flop is referred to as an SR flip-flop
or SR latch. The flip-flop in Figure 2 has two useful states. When Q=1 and Q'=0, it is

in the set state (or 1-state). When Q=0 and Q'=1, it is in the clear state (or 0-state).
The outputs Q and Q' are complements of each other and are referred to as the normal
and complement outputs, respectively. The binary state of the flip-flop is taken to be
the value of the normal output.
When a 1 is applied to both the set and reset inputs of the flip-flop in Figure 2, both Q
and Q' outputs go to 0. This condition violates the fact that both outputs are
complements of each other. In normal operation this condition must be avoided by
making sure that 1's are not applied to both inputs simultaneously.

(a) Logic diagram

(b) Truth table

Figure 2. Basic flip-flop circuit with NOR gates

(a) Logic diagram

(b) Truth table

Figure 3. Basic flip-flop circuit with NAND gates
The NAND basic flip-flop circuit in Figure 3(a) operates with inputs normally at 1
unless the state of the flip-flop has to be changed. A 0 applied momentarily to the set

input causes Q to go to 1 and Q' to go to 0, putting the flip-flop in the set state. When
both inputs go to 0, both outputs go to 1. This condition should be avoided in normal
operation.
Back to Contents

Introduction - Clocked SR Flip-Flop

The clocked SR flip-flop shown in Figure 4 consists of a basic NOR flip-flop and two
AND gates. The outputs of the two AND gates remain at 0 as long as the clock pulse
(or CP) is 0, regardless of the S and R input values. When the clock pulse goes to 1,
information from the S and R inputs passes through to the basic flip-flop. With both
S=1 and R=1, the occurrence of a clock pulse causes both outputs to momentarily go
to 0. When the pulse is removed, the state of the flip-flop is indeterminate, ie., either
state may result, depending on whether the set or reset input of the flip-flop remains a
1 longer than the transition to 0 at the end of the pulse.

(a) Logic diagram

(b) Truth table

Figure 4. Clocked SR flip-flop
Back to Contents

Introduction - D Flip-Flop
The D flip-flop shown in Figure 5 is a modification of the clocked SR flip-flop. The D
input goes directly into the S input and the complement of the D input goes to the R
input. The D input is sampled during the occurrence of a clock pulse. If it is 1, the

flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop
switches to the clear state.

(a) Logic diagram with NAND gates

(b) Graphical symbol

(c) Transition table

Figure 5. Clocked D flip-flop
Back to Contents

Introduction - JK Flip-Flop
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the
SR type is defined in the JK type. Inputs J and K behave like inputs S and R to set and
clear the flip-flop (note that in a JK flip-flop, the letter J is for set and the letter K is
for clear). When logic 1 inputs are applied to both J and K simultaneously, the flipflop switches to its complement state, ie., if Q=1, it switches to Q=0 and vice versa.
A clocked JK flip-flop is shown in Figure 6. Output Q is ANDed with K and CP
inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1.
Similarly, ouput Q' is ANDed with J and CP inputs so that the flip-flop is set with a
clock pulse only if Q' was previously 1.
Note that because of the feedback connection in the JK flip-flop, a CP signal which
remains a 1 (while J=K=1) after the outputs have been complemented once will cause

repeated and continuous transitions of the outputs. To avoid this, the clock pulses
must have a time duration less than the propagation delay through the flip-flop. The
restriction on the pulse width can be eliminated with a master-slave or edge-triggered
construction. The same reasoning also applies to the T flip-flop presented next.

(a) Logic diagram

(b) Graphical symbol

(c) Transition table

Figure 6. Clocked JK flip-flop
Back to Contents

Introduction - T Flip-Flop
The T flip-flop is a single input version of the JK flip-flop. As shown in Figure 7, the
T flip-flop is obtained from the JK type if both inputs are tied together. The output of
the T flip-flop "toggles" with each clock pulse.

(a) Logic diagram

(b) Graphical symbol

(c) Transition table

Figure 7. Clocked T flip-flop
Back to Contents

Introduction - Triggering of Flip-flops

The state of a flip-flop is changed by a momentary change in the input signal. This
change is called a trigger and the transition it causes is said to trigger the flip-flop.
The basic circuits of Figure 2 and Figure 3 require an input trigger defined by a
change in signal level. This level must be returned to its initial level before a second
trigger is applied. Clocked flip-flops are triggered by pulses.
The feedback path between the combinational circuit and memory elements in Figure
1 can produce instability if the outputs of the memory elements (flip-flops) are
changing while the outputs of the combinational circuit that go to the flip-flop inputs
are being sampled by the clock pulse. A way to solve the feedback timing problem is
to make the flip-flop sensitive to the pulse transition rather than the pulse duration.
The clock pulse goes through two signal transitions: from 0 to 1 and the return from 1
to 0. As shown in Figure 8 the positive transition is defined as the positive edge and
the negative transition as the negative edge.

Figure 8. Definition of clock pulse transition

The clocked flip-flops already introduced are triggered during the positive edge of the
pulse, and the state transition starts as soon as the pulse reaches the logic-1 level. If
the other inputs change while the clock is still 1, a new output state may occur. If the
flip-flop is made to respond to the positive (or negative) edge transition only, instead
of the entire pulse duration, then the multiple-transition problem can be eliminated.
Back to Contents

Introduction - Master-Slave Flip-Flop

A master-slave flip-flop is constructed from two seperate flip-flops. One circuit serves
as a master and the other as a slave. The logic diagram of an SR flip-flop is shown in
Figure 9. The master flip-flop is enabled on the positive edge of the clock pulse CP
and the slave flip-flop is disabled by the inverter. The information at the external R
and S inputs is transmitted to the master flip-flop. When the pulse returns to 0, the
master flip-flop is disabled and the slave flip-flop is enabled. The slave flip-flop then
goes to the same state as the master flip-flop.

Figure 9. Logic diagram of a master-slave flip-flop

The timing relationship is shown in Figure 10 and is assumed that the flip-flop is in
the clear state prior to the occurrence of the clock pulse. The output state of the
master-slave flip-flop occurs on the negative transition of the clock pulse. Some
master-slave flip-flops change output state on the positive transition of the clock pulse
by having an additional inverter between the CP terminal and the input of the master.

Figure 10. Timing relationship in a master slave flip-flop

Back to Contents

Introduction - Edge Triggered Flip-Flop

Another type of flip-flop that synchronizes the state changes during a clock pulse
transition is the edge-triggered flip-flop. When the clock pulse input exceeds a
specific threshold level, the inputs are locked out and the flip-flop is not affected by
further changes in the inputs until the clock pulse returns to 0 and another pulse
occurs. Some edge-triggered flip-flops cause a transition on the positive edge of the
clock pulse (positive-edge-triggered), and others on the negative edge of the pulse
(negative-edge-triggered). The logic diagram of a D-type positive-edge-triggered flipflop is shown in Figure 11.

Figure 11. D-type positive-edge triggered flip-flop

When using different types of flip-flops in the same circuit, one must ensure that all
flip-flop outputs make their transitions at the same time, ie., during either the negative
edge or the positive edge of the clock pulse.
Back to Contents

Introduction - Direct Inputs

Flip-flops in IC packages sometimes provide special inputs for setting or clearing the
flip-flop asynchronously. They are usually called preset and clear. They affect the flipflop without the need for a clock pulse. These inputs are useful for bringing flip-flops
to an intial state before their clocked operation. For example, after power is turned on
in a digital system, the states of the flip-flops are indeterminate. Activating the clear
input clears all the flip-flops to an initial state of 0. The graphic symbol of a JK flipflop with an active-low clear is shown in Figure 12.

(a) Graphic Symbol

(b) Transition table

Figure 12. JK flip-flop with direct clear
Back to Contents

Preparation
Prepare the following in your prac book:
Basic Flip-Flop
i.
ii.

Draw the logic circuit for an unclocked NOR gate flip-flop.

Enter the expected timing diagram for signals Q and Q' in Figure 13.

Figure 13. NOR gate flip-flop timing diagram

iii.
iv.

Draw the logic circuit for an unclocked NAND gate flip-flop.

Enter the expected timing diagram for signals Q and Q' in Figure 14.

Figure 14. NAND gate flip-flop timing diagram

Master-Slave Flip-Flop
i.
ii.

Draw the logic circuit implemented with gates for the SR master-slave flipflop in Figure 9. Use NOR gate flip-flops.
Enter the expected timing diagram for the signals Y, Y', Q, and Q' in Figure
15.

Figure 15. SR master-slave flip-flop timing diagram

Edge Triggered Flip-Flop

i.
ii.

Draw the logic circuit for the D-type positive-edge triggered flip-flop in
Figure 11.
Enter the expected timing diagram for the signals S, R, Q, and Q' in Figure 16.

Figure 16. D-type edge triggered flip-flop timing diagram

The Master-Slave Flip-Flop

One way of overcoming the problem with oscillation that occurs with a JK Flip-when
J=K=1 is to use a so-called master-slave flip-flop which is illustrated below.

The master-slave flip-flop is essentially two back-to-back JKFFs, note however, that
feedback from this device is fed back both to the master FF and the slave FF.
Any input to the master-slave flip-flop at J and K is first seen by the master FF part of
the circuit while CLK is High (=1). This behaviour effectively "locks" the input into
the master FF. An important feature here is that the complement of the CLK pulse is
fed to the slave FF. Therefore the outputs from the master FF are only "seen" by the
slave FF when CLK is Low (=0). Therefore on the High-to-Low CLK transition the
outputs of the master are fed through the slave FF. This means that the at most one
change of state can occur when J=K=1 and so oscillation between the states Q=0 and
Q=1 at successive CLK pulses does not occur.

Pulse-Triggered (Master-Slave) Flipflops

The term pulse-triggered means that data are entered into the flip-flop on the
rising edge of the clock pulse, but the output does not reflect the input state until
the falling edge of the clock pulse. As this kind of flip-flops are sensitive to any
change of the input levels during the clock pulse is still HIGH, the inputs must be
set up prior to the clock pulse's rising edge and must not be changed before the
falling edge. Otherwise, ambiguous results will happen.
The three basic types of pulse-triggered flip-flops are S-R, J-K and D. Their
logic symbols are shown below. Notice that they do not have the dynamic input
indicator at the clock input but have postponed output symbols at the outputs.

The truth tables for the above pulse-triggered flip-flops are all the same as that
for the edge-triggered flip-flops, except for the way they are clocked. These flipflops are also called Master-Slave flip-flops simply because their internal
construction are divided into two sections. The slave section is basically the same
as the master section except that it is clocked on the inverted clock pulse and is
controlled by the outputs of the master section rather than by the external
inputs. The logic diagram for a basic master-slave S-R flip-flop is shown below.

Data Lock-Out Flip-flops

The data lock-out flip-flop is similar to the pulse-triggered (master-slave) flipflop except it has a dynamic clock input. The dynamic clock disables (locks out)
the data inputs after the rising edge of the clock pulse. Therefore, the inputs do

not need to be held constant while the clock pulse is HIGH.

The master section of this flip-flop is like an edge-triggered device. The slave
section becomes a pulse-triggered device to produce a postponed output on the
falling edge of the clock pulse.
The logic symbols of S-R, J-K and D data lock-out flip-flops are shown below.
Notice they all have the dynamic input indicator as well as the postponed output
symbol.

Again, the above data lock-out flip-flops have same the truth tables as that for
the edge-triggered flip-flops, except for the way they are clocked.

Flip-flop (electronics)
History
The first electronic flip-flop was invented in 1919 by William Eccles and F. W. Jordan
[1]
. It was initially called the Eccles-Jordan trigger circuit and consisted of two
active elements (radio-tubes). The name flip-flop was later derived from the sound
produced on a speaker connected with one of the backcoupled amplifiers output
during the trigger process within the circuit.

[edit] General implemention

Flip-flops can be either simple or clocked. Simple flip-flops consist of two crosscoupled inverting elements transistors, or NAND, or NOR-gates perhaps
augmented by some enable/disable (gating) mechanism. Clocked devices are specially
designed for synchronous (time-discrete) systems and therefore ignores its inputs
except at the transition of a dedicated clock signal (known as clocking, pulsing, or
strobing). This causes the flip-flop to either change or retain its output signal based
upon the values of the input signals at the transition. Some flip-flops change output on
the rising edge of the clock, others on the falling edge.
Clocked flip-flops are typically implemented as master-slave devices* where two
basic flip-flops (plus some additional logic) collaborate to make it insensitive to
spikes and noise between the short clock transitions; they nevertheless also often
include asynchronous clear or set inputs which may be used to change the current
output independent of the clock.

Flip-flops can be further divided into types that have found common applicability in
both asynchronous and clocked sequential systems: the SR ("set-reset"), D ("delay"),
T ("toggle"), and JK types are the common ones; all of which may be synthetisized
from (most) other types by a few logic gates. The behavior of a particular type can be
described by what is termed the characteristic equation, which derives the "next" (i.e.,
after the next clock pulse) output, Qnext, in terms of the input signal(s) and/or the
current output, Q.
* Early master-slave devices actually remained (half) open between the first and
second edge of a clocking pulse; today most flip-flops are designed so they may be
clocked by a single edge as this gives large benefits regarding noise immunity,
without any significant downsides.

[edit] Set-Reset flip-flops (SR flip-flops)

See SR latch.

[edit] Toggle flip-flops (T flip-flops)

A circuit symbol for a T-type flip-flop, where > is the clock input, T is the toggle input
and Q is the stored data output.
If the T input is high, the T flip-flop changes state ("toggles") whenever the clock
input is strobed. If the T input is low, the flip-flop holds the previous value. This
behavior is described by the characteristic equation:
(or, without benefit of the XOR operator, the equivalent:
)
and can be described in a truth table:
T Q Qnext Comment
0 0 0 hold state
0 1 1 hold state
1 0 1
toggle
1 1 0
toggle
A toggle flip-flop composed of a single RS flip-flop becomes an oscillator, when it is
clocked. To achieve toggling, the clock pulse must have exactly the length of half a
cycle. While such a pulse generator can be built, a toggle flip-flop composed of two
RS flip-flops is the easy solution. Thus the toggle flip-flop divides the clock
frequency by 2 ie. if clock frequency is 4 MHz, the output frequency obtained from
the flip-flop will be 2 MHz. This 'divide by' feature has application in various types of
digital counters.

[edit] JK flip-flop

JK flip-flop timing diagram

The JK flip-flop augments the behavior of the SR flip-flop by interpreting the S = R =
1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0
is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset
the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e.,
change its output to the logical complement of its current value. Setting J = K = 0
does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a
D flip-flop, simply set K equal to the complement of J. The JK flip-flop is therefore a
universal flip-flop, because it can be configured to work as an SR flip-flop, a D flipflop or a T flip-flop.

A circuit symbol for a JK flip-flop, where > is the clock input, J and K are data inputs,
Q is the stored data output, and Q' is the inverse of Q.
The characteristic equation of the JK flip-flop is:

and the corresponding truth table is:

J K Qnext Comment
0 0
hold state
0 1
reset
1 0
set
1 1
toggle
The origin of the name for the JK flip-flop is detailed by P. L. Lindley, a JPL engineer,
in a letter to EDN, an electronics design magazine. The letter is dated June 13, 1968,
and was published in the August edition of the newsletter. In the letter, Mr. Lindley
explains that he heard the story of the JK flip-flop from Dr. Eldred Nelson, who is
responsible for coining the term while working at Hughes Aircraft.
Flip-flops in use at Hughes at the time were all of the type that came to be known as
J-K. In designing a logical system, Dr. Nelson assigned letters to flip-flop inputs as
follows: #1: A & B, #2: C & D, #3: E & F, #4: G & H, #5: J & K. Given the size of

the system that he was working on, Dr. Nelson realized that he was going to run out of
letters, so he decided to use J and K as the set and reset input of each flip-flop in his
system (using subscripts or somesuch to distinguish the flip-flops), since J and K were
"nice, innocuous letters."
Dr. Montgomery Phister, Jr., an engineer under Dr. Nelson at Hughes, in his book
"Logical Design of Digital Computers" (Wiley,1958) picked up the idea that J and K
were the set and reset input for a "Hughes type" of flip-flop, which he then termed "JK flip-flops." He also defined R-S, T, D, and R-S-T flip-flops, and showed how one
could use Boolean Algebra to specify their interconnections so as to carry out
complex functions.

[edit] D flip-flop
The D flip-flop can be interpreted as a primitive delay line or zero-order hold, since
the data is posted at the output one clock cycle after it arrives at the input. It is called
delay flip flop since the output takes the value in the Data-in.
The characteristic equation of the D flip-flop is:

and the corresponding truth table is:

D Q > Qnext
0 X Rising 0
1 X Rising 1
These flip flops are very useful, as they form the basis for shift registers, which are an
essential part of many electronic devices.
The advantage of this circuit over the D-type latch is that it "captures" the signal at the
moment the clock goes high, and subsequent changes of the data line do not matter,
even if the signal line has not yet gone low again.

[edit] Master-slave D flip-flop

A master-slave D flip-flop is created by connecting two gated D latches in series, and
invert the enable input to one of them. It is called master-slave because the second
latch in the series only changes in response to a change in the first (master) latch.

A master slave D flip flop. It responds on the negative edge of the enable input
(usually a clock).

For a positive-edge triggered master-slave D flip-flop, when the clock signal is low
(logical 0) the enable seen by the first or master D latch (the inverted clock
signal) is high (logical 1). This allows the master latch to store the input value when
the clock signal transitions from low to high. As the clock signal goes high (0 to 1) the
inverted enable of the first latch goes low (1 to 0) and the value seen at the input to
the master latch is locked. Nearly simultaneously, the twice inverted enable of the
second or slave D latch transitions from low to high (0 to 1) with the clock signal.
This allows the signal captured at the rising edge of the clock by the now locked
master latch to pass through the slave latch. When the clock signal returns to low (1
to 0), the output of the "slave" latch is "locked", and the value seen at the last rising
edge of the clock is held while the master latch begins to accept new values in
preparation for the next rising clock edge.

An implementation of a master-slave D flip-flop that is triggered on the positive edge

of the clock.
By removing the left-most inverter in the above circuit, a D-type flip flop that strobes
on the falling edge of a clock signal can be obtained. This has a truth table like this:
D Q > Qnext
0 X Falling 0
1 X Falling 1
Most D-type flip-flops in ICs have the capability to be set and reset, much like an SR
flip-flop. Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops.
Inputs
Outputs
S R D > Q Q'
0 1 X X 0
1
1 0 X X 1
0
1 1 X X 1
1
By settting S = R = 0, the flip-flop can be used as described above.

[edit] Edge-triggered D flip-flop

A more efficient way to make a D flip-flop is not as easy to understand, but it works
the same way. While the master-slave D flip flop is also triggered on the edge of a

clock, its components are each triggered by clock levels. The "edge-triggered D flip
flop" does not have the master slave properties.

A positive-edge-triggered D flip-flop.

[edit] Uses

A single flip-flop can be used to store one bit, or binary digit, of data.
Static RAM, which is the primary type of memory used in registers to store
numbers in computers and in many caches, is built out of flip-flops.
Any one of the flip-flop types can be used to build any of the others.
The data contained in several flip-flops may represent the state of a sequencer,
the value of a counter, an ASCII character in a computer's memory or any
other piece of information.
One use is to build finite state machines from electronic logic. The flip-flops
remember the machine's previous state, and digital logic uses that state to
calculate the next state.
The T flip-flop is useful for constructing various types of counters. Repeated
signals to the clock input will cause the flip-flop to change state once per highto-low transition of the clock input, if its T input is "1". The output from one
flip-flop can be fed to the clock input of a second and so on. The final output
of the circuit, considered as the array of outputs of all the individual flip-flops,
is a count, in binary, of the number of cycles of the first clock input, up to a
maximum of 2n-1, where n is the number of flip-flops used. See: Counters
One of the problems with such a counter (called a ripple counter) is that the
output is briefly invalid as the changes ripple through the logic. There are two
solutions to this problem. The first is to sample the output only when it is
known to be valid. The second, more widely used, is to use a different type of
circuit called a synchronous counter. This uses more complex logic to ensure
that the outputs of the counter all change at the same, predictable time. See:
Counters

Frequency division: a chain of T flip-flops as described above will also

function to divide an input in frequency by 2n, where n is the number of flipflops used between the input and the output.

[edit] Timing and metastability

A flip-flop in combination with a Schmitt trigger can be used for the implementation
of an arbiter in asynchronous circuits.
Clocked flip-flops are prone to a problem called metastability, which happens when a
data or control input is changing at the instant of the clock pulse. The result is that the
output may behave unpredictably, taking many times longer than normal to settle to
its correct state, or even oscillating several times before settling. Theoretically it can
take infinite time to settle down. In a computer system this can cause corruption of
data or a program crash.
In many cases, metastability in flip-flops can be avoided by ensuring that the data and
control inputs are held constant for specified periods before and after the clock pulse,
called the setup time (tsu) and the hold time (th) respectively. These times are
specified in the data sheet for the device, and are typically between a few
nanoseconds and a few hundred picoseconds for modern devices.
Unfortunately, it is not always possible to meet the setup and hold criteria, because the
flip-flop may be connected to a real-time signal that could change at any time, outside
the control of the designer. In this case, the best the designer can do is to reduce the
probability of error to a certain level, depending on the required reliability of the
circuit. One technique for suppressing metastability is to connect two or more flipflops in a chain, so that the output of each one feeds the data input of the next, and all
devices share a common clock. With this method, the probability of a metastable
event can be reduced to a negligible value, but never to zero. The probability of
metastability gets closer and closer to zero as the number of flip-flops connected in
series is increased.
So-called metastable-hardened flip-flops are available, which work by reducing the
setup and hold times as much as possible, but even these cannot eliminate the problem
entirely. This is because metastability is more than simply a matter of circuit design.
When the transitions in the clock and the data are close together in time, the flip-flop
is forced to decide which event happened first. However fast we make the device,
there is always the possibility that the input events will be so close together that it
cannot detect which one happened first. It is therefore logically impossible to build a
perfectly metastable-proof flip-flop.
Another important timing value for a flip-flop is the clock-to-output delay (common
symbol in data sheets: tCO) or propagation delay (tP), which is the time the flip-flop
takes to change its output after the clock edge. The time for a high-to-low transition
(tPHL) is sometimes different from the time for a low-to-high transition (tPLH).
When connecting flip-flops in a chain, it is important to ensure that the tCO of the first
flip-flop is longer than the hold time (tH) of the second flip-flop, otherwise the second

flip-flop will not receive the data reliably. The relationship between tCO and tH is
normally guaranteed if both flip-flops are of the same type.

[edit] Flip-Flop integrated circuits

Integrated circuit (ICs) can be found with one or more Flip-flop circuits on board. For
example, the 7473 Dual JK Master-Slave Flip-flop or the 74374, an octal D Flip-flop,
in the 7400 series.