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TA: Mark DeMarie

If this is your first time running cadence then you must copy and paste each of the
above lines starting with cp into your terminal window at this time followed by the
ENTER key.
*[Note: This does not need to be done each time you open Cdence, only the first time.]
After typing use cadence and hitting ENTER proceed by typing virtuoso. This should
open the Virtuoso Log Window (Fig.2) and the Library Manager (Fig.3).
*[Note: By typing virtuoso, after Cdence has opened you will no longer be able to access your terminal
window while cadence is open. If you wish to use the terminal while Cdence is open type virtuoso &
instead of virtuoso.]

Fig.2 Virtuoso Log Window

 Fig.3 Library Manager

*[Note: Your Library Manager may not contain any or many Libraries, but they can be added.]
If the Library Manager does not open, it can be opened through the Virtuoso Log
Window by clicking Tools Library Manager
To create a new Library
1. In the Library Manager, File New Library, a new window will open.
2. Here give your library folder a NAME and you may select new directory locations.
3. Click OK and you will be given the option about adding Technology Files.
4. From your choices, select Attach to an existing technology library and select the
NCSU_TechLib_ami16 library.
*[Note: This library is based on the AMI 1.6  process, created by the NCSU group, which is a BiCMOS
process giving you the NMOS, PMOS and NPN transistors as the basic devices.]

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To Create Layout Cell view

1. From the Library Manager, choose File New Cell view
(Make sure that the library you want to create the new cell view in is highlighted in
the Library column)
2. Enter a cell name of your choice next to Cell (the
name should reflect your circuit) and select layout as
your Type. The label next to View should match the
Type.
Fig.4 New File Window
3. The LSW (Layer Select Window) and Virtuoso Layout
(the Layout Editor) windows will open after entering the
design name, see Fig.5. The LSW is where you choose
which layer you need to use while the Virtuoso Layout
window is where your circuit design is created.
Fig.5 LSW & Virtuoso Layout

Layers
Since a circuit has length, width and thickness a circuit is technically 3 dimensional.
However we often only view circuits in a 2D plane (i.e. Layout). Different Layers are at
different heights from the substrate. Each layer has its own unique color/pattern so we
can keep track of wires at different heights. The thickness of each layer is uncontrollable
by the designer. It is determined by the semiconductor foundry. MOSIS provides data
sheets on the sheet resistances ( ) and other parameters for the various Foundries
that they deal with.
*[Note: MOSIS is an organization at Univ. Southern California that acts as middle man between Fab users
and various Semiconductor Foundries such as IBM, TSMC, ON Semi (used to be AMI), Peregrine, etc.].

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When drawing, any paths that cross in a given layer will always be connected !
Sometimes you will need to re-route wires so that you avoid unwanted connections or
use layers at different levels (such as Metal-1 and Metal-2). It is alright if different layers
appear to be crossing over each other. Remember each layer represents a different
material that is at a different height. There will be oxides between layers to isolate
wires. Also each layer has many design rules that determine minimum spacings and
thicknesses that wires/regions may be from one another within the same layer.

The NMOS Layout

1. A bare MOSFET will require the use of 5 layers in the LSW:
nactive, pactive, nselect, pselect, poly, active contacts (cc), and metal1
2. Drawing the active region (nactive for an NMOS)
Select the nactive layer from the LSW window and click back to the Virtuoso
Layout window, choose Create  Shape  Rectangle from top of the window.
Select the first corner of the rectangle, click once (do not hold), and then move the
mouse cursor to the opposite corner to complete the rectangle. Draw a rectangle
that is 4.0  in vertical height and 9.6  wide similar to Fig.6 below.
Fig.6 nactive layer

The minimum width of an active layer is 4  in the SCMOS 1.6  process.

This mask defines the active area of the MOSFET device that will have a thin gate
oxide covering it. The surrounding area outside of this mask will have thick field
oxides and thus, is not device active.
Sizing your Layout
The Cdence Virtuoso tool measures all distances in microns, not . You can
use the Tools  Create Ruler command to measure distances (in microns) with the
ruler. This is highly useful, but note once a ruler is placed it remains on the screen until
you clear all rulers Tools  Clear All Rulers. You cannot remove only one ruler at a time.
When creating a ruler you can uncheck the box in the ruler window so that a ruler does
not remain on the screen after you click the mouse.
*[Note: is an important parameter, for any process     . For the 1.6 
process  0.8 . This is important and design rules are based upon this parameter. There are many

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Design rules and you will become accustomed to many of them through practice, so do not spend extra
time trying to memorize these rules. Realize that Design rule spacings tend to be multiples of .]

If you pay attention to the bottom of your Layout editor you can see your cursors
position relative to a zero point. More useful are two parameters dX and dY.
When drawing, after your first click to start a rectangle these values will reset and show
your position relative to your first click. This means you dont need to use rulers to
determine the size of your rectangles.
The default grid spacing in the layout window is 1.0 , which is not convenient for
our process. To make things easier do the following (numbers are in microns).
Go to Options
Display
Set minor spacing to 0.8 (This is for our process)
Set major spacing to 3.2
Set X Snapping Spacing 0.4
Set Y Snapping Spacing 0.4
You should perform a Design Rule Check (DRC) after each step of drawing to verify
that your layout does not violate any design rules. This helps to keep your layout error
free and makes finding your errors much easier.
*[Note: Do not get hung up with DRC skip and move on with the rest of layout tutorial if this DRC step
takes you too much time.]

Notes on Checking Design Rules

The Cdence Virtuoso layout tool does not automatically check for design rule
violations. It is a very good idea to save and verify your design frequently as you are
doing your layout. Dont wait until you are done to find that you have dozens of rule
violations to fix. It will be much easier to fix the errors if there are only a few of them.
The Design Rule Check (DRC) uses the design rules defined in the divaDRC.rul file to
check for design rule violations. The DRC flags the errors it finds by creating white
polygons around the errors. Details about the errors are also displayed in the Log
Window. Use the following procedure in the Layout Editor window to run a DRC.
1. Choose File  Save to save your design.
*[Note: It is not absolutely necessary to save before verifying your design, but you should
save your design frequently to avoid losing your work if the computer crashes.]

2. Choose Verify  DRC...

Click OK

If you have errors, youll see a highlighted polygon marking the first error. Fix your
errors and run DRC until there are no more errors in your design. DRC violations
only tell you if you have made layers too small or too close together. It does not tell
you if you are wasting area by making things bigger or farther apart than necessary.
You may need to push things together until a design rule violation occurs and then
move them out the minimum amount needed to remove the violation.

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3. Drawing poly-Si Gate (poly)

Select the poly layer from the LSW and draw a vertical polysilicon rectangle of
width 1.6  across the center of the active region as shown in Fig.7 below, (the
height of the rectangle does not affect any parameters of the MOSFET, but there is a
DRC rule specifying a minimum distance the poly must extend out from the active
region). This creates the MOSFET Gate and the MOSFET channel. Your MOSFET
channel length is equal to the width of this poly rectangle because the green regions
on either side are the Source and Drain regions of the MOSFET).
*[Note: The Source and Drain are not predetermined, but depend on their voltage. For NMOS, the
Source is always the terminal at the lower potential while the Drain is the terminal at the higher
potential. Physically they are identical.]
*[Note: That the sequence various layers are placed in layout does not affect the sequence of
fabrication process. For example, in the fabrication process, the N-type Source/Drain diffusion takes
place after the poly gate is deposited and patterned in a self-aligning process.]

Fig.7 Gate poly

This defines the 

transistor size. The region where the poly and active regions

overlap is the transistors channel. The poly separates what was one active region
into two separate active regions that will be the Source and Drain. Here the width of
the poly is the Length of the channel, while the height of the active layer is then the
Width of the channel. Remember, the current flows across the Length of a
transistor, not its Width.
4. Making an active contact
Select the cc (active contact) layer from the LSW. Create a rectangle of both a
width and height of 1.6 within the active area, see Fig.8. Contacts must always
be a size of 2 . There are design rules on how close a contact can be from the sides
of active regions. Often, especially in Analog Circuits it is smart to use many
contacts. This means you may need larger active regions, but make sure you dont
affect the width of your transistor. Contacts are part of your circuit path, thus
current flows through them. High currents can cause poor designs to short circuit.
To prevent a contact from burning out, create multiply contacts to effectively lower

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the resistance and distribute current flowing from one layer to the next. Draw
another contact on the other side of diffusion. Here, you may use the Edit  Copy
feature to duplicate your contact instead of drawing a new one.
Fig.8 Active Contacts

Select layer metal1 from the LSW and draw two 3.2  # 4.0  rectangles
to cover the contacts as Fig.9 shows. According to the design rules (for AMI16),
metal1 has to extend beyond the contact in all directions by at least 0.8 .
Fig.9 cc & metal1

5. Drawing the nselect layer

Each diffusion area of the transistor must be selected as n-type or p-type.
The active layers, such as nactive and pactive, have no associated doping type, they
are simply named differently and are different colors so that the user can more
easily identify the NMOS and PMOS in their design. The doping type is determined
by defining a special mask layer called nselect (or pselect) for n-type (or p-type)
doping (e.g., by implantation). This mask therefore defines an area on the silicon
wafer that needs to receive the implantation of dopants for the Source and Drain
areas of a MOSFET.
*[Note: That this mask (nselect) must be larger than, and must completely encompass, the active
mask (nactive). The thick field oxide that exists outside of the active masks will stop any dopant
impurities from being implanted into silicon during the fabrication. Also, the polysilicon gate layer will
block the dopants from being implanted into the channel region under the gate. This is the concept of
self-alignment in which the poly gate edge is ensured to line up perfectly with the edges of the
Source/Drain because the poly blocks implants at the edge of Source and Drain regions, which is to
minimize (ideally eliminate) the Gate/Source and Gate/Drain overlap and the parasitic (overlap)
capacitance.]

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To do this, select the nselect layer from LSW. Draw a rectangle surrounding the
active area by 1.6  on all sides as Fig.10 shows. The nselect rectangle is the thin
green line. Fig.10 is a completed NMOS.
Fig.10 nselect

6. Drawing the P-Substrate Contact

The not so often seen terminal of a transistor is its Body. The Body for an NMOS
is typically just the p-type substrate it is placed in. Using the pactive layer, draw a
4  # 4  square somewhere to left of the NMOS (For the figure below the
active layer was used as it can be substituted for both pactive or nactive).Then
switch to your active contact layer (cc) and draw another square contact (or copy
paste) in the center of your active area. Because the substrate we are contacting is
p-type, this active region needs to be surrounded by the pselect layer. Switch to
metal1 and cover the contact with metal1. For the simple inverter we need to
connect the Body to the Source. Do this using metal1 by drawing a rectangle so that
you connect one of the contacts of the transistor to the contact you just made to the
substrate.
Fig.11 NMOS substrate contact (aka ptap)

The PMOS Layout

The steps for drawing a PMOS are basically the same as the NMOS steps with only a
few minor differences.
1. Draw a 10  high P-diffusion (pactive) above the NMOS, see Fig.12 below.
There is a DRC rule specifying how close these transistors must be due to the nwell
we will create later.
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Fig.12 pactive

Fig.13 poly for PMOS

2. Draw a Gate (poly) of width 1.6  as Fig.13 above shows.
3. Exactly as contacts are made with the NMOS, follow the same procedure to place
contacts on the PMOS. This time place three contacts on each side of the gate,
because there is enough room for three, see Fig.14.
Fig.14 PMOS Contacts

Fig.15 pselect
4. Draw the P-select layer (pselect) exactly as we drew the nselect layer (Fig.15).

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5. Drawing N-well layer (nwell)

The silicon substrate is doped p-type. NMOS transistors can be realized in this ptype substrate simply by creating n-type diffusion areas for the Source and Drain.
However, for the PMOS transistors we must create an nwell that will be the Body of
the PMOS. Select the nwell layer from LSW and draw a rectangle extending over the
pselect area by at least 2.4  in all directions as Fig.16 shows. Extend the nwell
an extra 8  to the left as shown for the next step.
*[Note: In fabrication this step would be done before any other steps in fabrication the PMOS.]

Fig.16 nwell

6. Drawing N-substrate contact

The PMOS transistor is placed within the n-well (the Body of a PMOS), which has
to be biased with the Vdd potential. This bias of N-well with the most positive
potential on the die ensures a reverse-biased p-n junction between the N-well and
the p-type Source, Drain or channel regions of PMOS. This will be done with an ntype substrate contact. This is the same as the NMOS substrate contact, but we use
4  # 4 nactive surrounded by nselect. Dont forget to place the contact and
connect it to one of the terminals of the PMOS. See Fig.17 below.
Fig.17 nwell contact (aka ntap)

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Power Rails
All circuits need a source of power. This is usually a high potential (vdd!) and a
ground connection (gnd!). Layouts usually consist of a large number of transistors
and power must be distributed throughout a chip and to the MOSFETS. This is not
always an easy task and one needs to be smart in designing and strategically placing
power lines for optimum operations. Metal1 is suggested to always be used to
supply vdd! and gnd!. Generally, Layers can run wild and get messy, so try to
keep horizontal wires in metal1 while keeping vertical wires in metal2. Try to preplan the layout of your wires when placing transistors.
Draw a Power Rail in metal1 above the PMOS
Draw a Ground Rail in metal1 below the NMOS
Make sure to connect the Power Rail and the Ground Rail to the Source contact
of the PMOS and to that of NMOS, respectively, as in Fig.18. Power rails should
usually be thick (on the order of 4  or more). Transistors may only see a little
current, but with many transistors the power rails will need to handle the sum of all
these currents.
Fig.18 Power rails

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Connections and Labels

Now use metal1 to connect the Drain of NMOS to the Drain of the PMOS. Use poly
to connect the two gates (NMOS and PMOS). The input signal will be fed into this poly
(Gate). Choose Create Pin from menu to create pins at nodes in the circuit.
Cdence likes to see a ! after the vdd and gnd pins/labels. So make it a habit when
creating pins/labels to consistently use vdd! and gnd!. It would be useful to
checkmark  the box Display Terminal Name. Pins must be given a specific I/O
Type. The I/O Type you choose will effect what you can do to the node during
simulations. If you want to force a signal or source at some node for testing it must have
the input for its I/O Type. All nodes do not need to be given a Pin, but only nodes
you want to stimulate or monitor for simulation. Nodes within a circuit will
automatically be generated a label (a net number) when a netlist is created. For clarity
you can also place your own labels on any nodes by using the Create Label
command. Dont forget each node may only have one unique label or you will receive
DRC errors. Pins have a specific layer associated with them. To place a pin on metal1
you must have metal1 selected in the LSW window. Create an in pin on the poly and
an out pin on the connected Drains. Fig.19 is your final layout !

Fig.19: Complete Inverter, labels shown

The CMOS inverter circuit layout is now complete !
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Merging the design

Once you complete the DRC and have fixed any errors in your design, select the
entire design using the left mouse button. Then merge it by choosing Edit  Basic 
Merge. This command combines adjacent and overlapping layers of the same type
together. You can do this manually by selecting touching pieces.
Netlist Extraction
Circuit extraction is performed after the layout is complete. This is to create a netlist
which is a text version of a circuit schematic. This netlist is a text description of the
circuit contained in your physical layout and follows a certain, well defined format. In
this netlist you may add lines for the supply voltages and input signal sources. Also you
may add the command lines for any desired simulation (such as transient, ac sweep, or
dc sweep). These lines have to be added manually because your physical layout does not
have info on supply voltage values, signal sources, etc. The netlist is then the input file
for spice (or spectre) simulation. Therefore it does the same job as the circuit schematic
drawn in the Schematic Capture of PSPICE. The circuit extractor of Cdence is capable of
identifying individual transistors and interconnections, as well as the parasitic
resistances and capacitances that are inevitably present in and between layers. The
"extracted netlist" can provide a very accurate estimation of the actual device
dimensions and the device parasitics. These parasitics ultimately determine the circuit
performance. The extracted netlist file and parameters are subsequently used in the
Layout-Versus-Schematic (LVS) comparison. LVS is used to compare a circuit schematic
to a physical layout (by Virtuoso) of the circuit. It will match nodes and the number of
transistors and resistors between the schematic and layout to determine if they match
perfectly. An extracted layout file can more accurately simulate the way a circuit will
perform as it can take into account parasitics based on physical sizes of regions in the
layout.
After finishing layout (error free), select Verify  Extract from the Layout window.
Leave the default values for most of the fields except for Switch Names. Click on Set
Switches and select Extract_parasitic_caps and Keep_labels_in_extracted_view from
the popup window (hold the SHIFT key to highlight both options at the same time).
This will extract the devices and parasitics based on the divaEXT.rul file from your
layout, and display the labels/pins in the extracted view. The tech library defines the
standard devices (for example, BiCMOS has NMOS, PMOS and NPN as the standard
device and everything else is parasitic; so you wont have PNP, PN diode, etc. in the
extracted netlist).
Click OK,
Check in your Virtuoso Log Window to see if there are any errors. If there are no
errors, you will be able to see the extracted view in the library manager window by
selecting extracted under the View column. Open your extracted circuit under the
view column of the Library Manager.
*[Note: The view on the left is what you will see first. To make things more clear press SHIFT+F to see the
view on the right. To go back to the view on the left, press CTRL+F.]

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Fig.20 Extracted circuit view

From the top select Launch  ADE L. A window will pop up as follows:

Fig.21 Analog Design Environment window

Click on Setup  Simulator/Directory/Host. Make sure spectre is your simulator.
Use the default directory /eng/home/username/cadence/simulation. Then click OK.
*[Note: Spectre is one of many commercially available circuit simulation programs (which include PSPICE,
HSPICE, ICAP, SMASH).]

Fig.22 Choose simulator spectre

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Go to Simulation tab in the Analog Design Environment window and click on

Simulation  netlist  Create. The netlist as in Fig.23 will be displayed in a window
once it has been created. The first line in the netlist tells you in which subdirectory of
your ENG home directory the netlist has been created and saved. Go to this path to edit
the netlist file. For example, if you are simulating the layout of an inverter and the
simulation directory was chosen as ~/cadence/simulation, then the subdirectory and
netlist file name will be ~/cadence/simulation/inverter/spectre/extracted/netlist/netlist.
In this folder you will find a simple text document named netlist that is your netlist.
Realize that when finding this directory, inverter (that was underlined) is the name of
your cellview. So this will change for each assignment.
Fig.23 Extracted netlist

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DRC
The layout must be drawn according to strict design rules. After you have finished
your layout, Cdence can check each and every feature in your layout file against these
design rules and report any violations. This process is called Design Rule Check (DRC).
Generally once the design is finished, you perform DRC to see if there are any errors.
It is a good idea to perform DRC in each step of layout so that you can find any errors as
you make them. This prevents having a large number of errors that may become
confusing to understand at the end of your design.
Choose Verify DRC from menu in Virtuoso Layout Editor. The DRC options dialog
box will pop-up. The default options for the DRC are adequate for most situations.
DRC results and progress will be displayed in the Virtuoso Log Window. A list of your
errors, if any, will be shown in the Virtuoso Log Window with a short description.
For simulations and testing one might create several pins/labels, some of which may
need to be the same. To make things easier you may not want to run a wire to connect
certain nets. Using multiple pins/labels of the same name this will cause a DRC error.
This can be accounted for in the DRC pop-up window by selecting Join Nets With Same
Name so this error is recognized as an intentional part of the design.
Sometimes DRC errors can be hard to find, especially on large layouts. Under
Verify  Markers there are a few options, two of which are Explain and Find.
Explain will provide details to what the error is and Find will move the screen over
the error for easy findings.

Schematic and LVS

After the circuit layout is completed, the layout should be checked against the
schematic circuit. LVS (Layout-Versus-Schematic) check will compare the circuit drawn
in the Schematic with the one extracted from the (physical) layout in order to check if
the two are indeed identical. The LVS step provides an additional level of confidence for
the integrity of your design, and ensures that the layout is a correct realization of the
intended circuit topology. A successful LVS will not guarantee that the extracted circuit
will actually satisfy the performance requirements. There are many errors that can
occur during the LVS check and often they are not obvious.
Here is a simplified procedure to create a circuit schematic for the inverter.
1. From the Library Manager, choose File New Cell view. In the Library Manager,
ensure the correct cell is highlighted. A new window will appear. Change the
Type to schematic and the view should automatically change itself to match.

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Fig.24 Create Schematic view

2. In the schematic editing window, choose Create Instance to create components.
Two windows will open; Component Browser and Add Instance. In the Component
Browser select NCSU_Analog_Parts as your library (This may be missing, in which
case you will have to add it). This Library contains all the schematic analog
components you should need.

Fig.25 Component Browser & Add Instance

3. Choose the components from the list (For instances, get nmos4 from N_Transistors,
pmos4 from P_Transistors, vdd and gnd from Supply Nets) and put them onto
editing window. Before you place components you should set your variables such as
Widths and Lengths. You can edit component properties by selecting the component
first, then choose Edit Properties  Objects or right click on the component
and there will be a Properties options.
4. Make wire connections between each component using Create  Wire(narrow).
Then we need to add pins to the circuit as input, output, or input/output. Go to
Create  Pin then you will be given a window to write the pin name and choose
its direction. If a node will only be an input to a circuit then configure it as an input.

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Same for output. Using input/output as your direction will allow you to choose the
direction when setting up your simulation. The final schematic is like Fig. 26.

Fig.26 Inverter Schematic circuit

Procedure for LVS
You should now have a schematic view and extracted view (and layout) of the
inverter. If you are missing the extracted view see the Netlist Extraction section above.
1. Open the extracted view of the cell in edit mode.
2. From the extracted window, choose Verify  LVS from the menu. The Artist
LVS window will open that looks like Fig.27.

Fig.27 Artist LVS

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3. Towards the top you see Library, Cell, and View. Your Library and Cell
should usually be the same for the schematic and extracted columns. Just
ensure that that the views are correct. To change any of these areas, just click
Browse and a window similar to the Library Manager will appear (this is not your
Library Manager). From here select the correct views.
4. When ready, click Run to start the comparison. You should receive a message
saying the Analysis Job Succeeded. This does not mean your LVS has matched,
but simply the comparison was successful. Often you may get a message saying
your Analysis failed. The most common reason for this is that one of the netlist
(schematic or extracted) doesnt exist yet. Next click on the Output button next
to Run. This will open a window similar to Fig.28 below:
Fig.28 LVS Results

The key is to find either The net-list match or The net-list failed to match
If everything is done correctly The net-list match is what we want. If you fail to match
netlist then check your layout and schematic for missing wires, or mismatched
labels/pins. Sometimes it is time consuming and aggravating to find your errors.

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Note on NPN LAYOUT

For the collector active layer,

- If you want to be able to extract your circuit, use the cactive layer.
- If you want to pass the DRC check, change the layer to active or nactive.
In the end we want to extract the circuit so you may use the cactive layer initially and
just ignore the error it creates when you perform the DRC check.

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