Anda di halaman 1dari 13


12, DECEMBER 2014


A 1.2 nJ/bit 2.4 GHz Receiver With a Sliding-IF

Phase-to-Digital Converter for Wireless
Personal/Body Area Networks
Yao-Hong Liu, Member, IEEE, Ao Ba, Member, IEEE, J. H. C. van den Heuvel, Member, IEEE,
Kathleen Philips, Member, IEEE, Guido Dolmans, Member, IEEE, and Harmke de Groot, Member, IEEE

AbstractThis paper presents an ultra-low power 2.4 GHz

FSK/PSK RX for wireless personal/body area networks.
A single-channel phase-tracking RX based on a sliding-IF
phase-to-digital conversion (SIF-PDC) loop is proposed to directly demodulate and digitize the frequency/phase-modulated
information. The sliding-IF frequency plan reduces the power
consumption of the multi-phase LO generation. A phase rotator
is adopted in SIF-PDC to guarantee frequency stability, i.e., avoid
the frequency pulling by interference or frequency drift. It equivalently transforms the RF signal processing from the I/Q amplitude
domain to a digital-phase domain, which saves up to nearly 40%
on power consumption and relaxes the digital baseband complexity. A phase-domain linear model of the proposed SIF-PDC
is presented to analyze the frequency response. Fabricated in a
90 nm CMOS technology, the presented RX consumes 2.4 mW at
2 Mbps data rate, i.e., 1.2 nJ/b efficiency, and achieves a sensitivity
of 92 dBm.
Index TermsBluetooth low energy receiver, Delta-Sigma
frequency-to-digital converter, Delta-Sigma phase-to-digital
converter, frequency demodulator, frequency digitizer, phase
demodulator, phase digitizer, PLL demodulator, ultra-low power
receiver, ZigBee receivers.


LTRA-LOW-POWER (ULP) transceivers enable shortrange networks of autonomous sensor nodes for wirelesspersonal-area-network (WPAN) and body-area-network (BAN)
applications. In such applications, the RF transceiver can consume up to 90% of the total battery energy in a remote wireless
sensor node. In order to extend the operation lifetime, it is a primary design goal for such a transceiver to improve the energy
efficiency, expressed as power consumption divided by the data
rate, to below 1 nJ/bit.
The power consumption of the receivers (RXs) is mainly set
by the requirements of the sensitivity and the tolerance of interference, which both are relaxed in short-range WPAN/BAN
applications in comparison to long-range applications (e.g.,

Manuscript received May 09, 2014; revised August 07, 2014, October 15,
2014, and October 16, 2014; accepted October 16, 2014. Date of publication
November 13, 2014; date of current version November 20, 2014. This paper
was approved by Guest Editor Sven Mattisson.
The authors are with the IMEC-Holst Centre, Eindhoven, 5656AE The
Netherlands (e-mail:
Color versions of one or more of the figures in this paper are available online
Digital Object Identifier 10.1109/JSSC.2014.2365092

cellular). Many WPAN/BAN radios still prefer to keep sufficient link margin (i.e., TX output powerRX sensitivity)
even for a short communication distance, since the signal
attenuation through or around the human body can be as high as
70 dB. Therefore, assuming that the TX output power is around
0 dBm, RX sensitivity that is better than 80 dBm then is
preferable. Meanwhile, the RXs tolerance to the interference,
especially from the adjacent channels in the same network, is
much more relaxed because of the reduced TX output power.
Frequency hopping or spectrum spreading are commonly used
in short-range radios to mitigate strong interference from other
networks, however, wideband interference (e.g., 20 MHz WiFi
signal) is still difficult to avoid. Fortunately, the energy of such
wideband signal is spreading over a wider bandwidth, thus
causing less impact to a narrow-band RX.
Although energy-detection ASK RXs [1] are extremely efficient, they are vulnerable to any interference that is stronger
than the desired signal (i.e., having an adjacent channel rejection
smaller than 0 dB), which leads to a poor quality of the wireless
link in a crowded 2.4 GHz ISM band. On the other hand, the constant-envelop binary-FSK type RXs, e.g., GFSK, MSK, Halfsine shaped Offset-QPSK (HS-OQPSK) RXs are popular in the
target applications because of their simple demodulation hardware and a better immunity to interference. They are also widely
adopted in many short-range wireless standards for WPAN and
BAN, like ZigBee (IEEE802.15.4) or Bluetooth Low Energy.
Conventional RF/analog front-end of FSK/PSK RXs usually
employees Cartesian I/Q structures e.g., (super)-heterodyne [2]
or homodyne RXs [3], to process phase information in the complex domain, so two parallel channels are required to separately
down-convert, filter and digitize the analog I and Q signals.
While Cartesian I/Q RXs heavily rely on the analog signal
conditioning (i.e., frequency down-conversion, amplification
and analog-to-digital conversion), it minimizes the complexity
of the LO generation that is basically a high-speed digital
circuit. However, as technology scaling dramatically degrades
the performance of the analog circuits (e.g., gain, linearity),
it also offers a better power efficiency and faster switching
speed of digital logics. In order to leverage the benefit in the
nano-scale CMOS technologies, part of the design complexity
is best shifted from the analog I/Q signal channels to the
LO generation.
In this paper, we present an ultra-low power single-channel
RX which tracks the input frequency/phase-modulated signals

0018-9200 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See for more information.



Fig. 1. Phase-domain RXs: (a) conventional Cartesian FSK/PSK RXs with a phase-ADC or a differentiator, (b) single-channel phase tracking RXs, (c)
frequency-to-digital converter-based FSK RXs.

by switching between multiple LO phases, and it saves up to

nearly 40% of total power consumption compare to the previous
work [2] with a conventional Cartesian I/Q RX.
This paper is organized as followed. In Section II, several
conventional phase-domain RXs are reviewed. In Section III,
the proposed phase-domain RX based on a sliding-IF phase-todigital converter (SIF-PDC) is introduced. Section IV presents
the modeling and analysis of the SIF-PDC. Key building blocks
are discussed in Section V. Finally, Sections VI and VII present
the experimental results and conclusions, respectively.
Due to the benefit of constant-envelope nature of FSK/PSKtype modulations which modulate data only on the frequency or
phase of the carrier, the transmitter (TX) hardware can be sim-

plified, while the efficiency can be enhanced by driving the circuits into the switching mode, e.g., PLL-based FSK TXs [2], [4].
Similarly, in the RX counterpart, rather than processing the
signal in the I/Q domain, it can be demodulated in the phase
domain by replacing I/Q ADCs with a phase-ADC [5] or a
phase differentiator [6], as shown in Fig. 1(a). However, such
approaches still require a power-hungry high-frequency quadrature-phase LO generation and a 2-dimensional frequency downconversion, filtering, and digitization circuits.
In the single-channel phase-tracking RX of [7], a free-running VCO is part of the RX carrier recovery and frequency-demodulation loop, as shown in Fig. 1(b). The RX power consumption can be significantly reduced, since it only needs one
channel and does not require high-frequency quadrature LO
generation. However, if it is used as a front-end to directly receive RF modulated signals, the center frequency of a free-run-


ning VCO can be easily pulled away by an interferer that is

stronger than the desired signal during the carrier recovery. This
then leads to a poor RX selectivity. Moreover, the RX sensitivity
is also degraded due to the slow frequency drift of a free-running VCO which translates to low-frequency noise at the RX
output. Finally, an ADC that digitizes the VCO tuning voltage
contributes quantization noise and limits the accuracy of the
frequency digitization.
-frequency-to-digital converter
as a frequency demodulator [8], as shown in Fig. 1(c), uses a counter
as a precise LO phase controller to improve carrier frequency
stability and a quantization noise shaping technique to enhance
the resolution of the frequency digitization. The counter, sampled by a clock
8 times higher than carrier frequency ,
provides its Carry as a time-domain feedback to the phase detector. This approach has a stable center frequency which avoids
the issues of a free-running VCO as mentioned previously, i.e.,
slow frequency drift and center frequency pulling by interference. However, the ADC needs to be sampled at the signal carrier frequency , making it inefficient to directly operate at the
RF input frequency above few-hundred MHz. In addition, the
ADC sampling time
changes along with the modulated data and leads to a non-uniformly-sampled digital output,
which further complicates the hardware of the following digital
signal processing.
A. RF Phase-to-Digital Conversion With a Phase Rotator
Rather than using a counter as the LO phase controller, a
phase rotator [9][12] (consisted of a phase selector and a phase
integrator) is employed in this work to decouple the input center
and the sampling frequency
of the ADC.
Hence, the selection of oversampling clock
becomes flexible and the non-uniform sampling as in [8] is avoided.
Instead of implementing the phase integration in the analog
domain (first integration then quantization [8], [10]), it is moved
to the digital domain (first quantization then accumulation) to
avoid an issue of limited phase integration range, which is critical when demodulating FSK/PSK signals with random data.
For instance, when an FSK RX with an analog phase integrator
receives several consecutive 1s, the integrator output will increase continuously and eventually result in clipping due to the
saturation point (e.g., supply voltage VDD) of the analog integrator or the ADC. On the other hand, the range of digital
phase integration is not limited because its output codes (i.e., 0
) can be designed to match one cycle of the LO phase
range (i.e.,
to ). Therefore, even a digital integrator/accumulator with only few bits of length (e.g., 4 bits in this work)
will not reach a saturation point as it digitally wraps back after
reaching full scale, as illustrated in Fig. 2(b). Furthermore, implementing the phase integration in the digital domain allows
the RX to directly readout the digitized phase information and
to perform a direct RF phase-to-digital conversion (PDC).
Furthermore, rather than using a digital phase detector [8], an
analog phase detector based on a Gilbert-cell mixer is adopted in
the proposed PDC loop because it can accommodate a stronger
interference. A limiting amplifier that is required before the


digital phase detection has extremely non-linear characteristic,

which can seriously distort the phase information of the desired signal when a strong interference is present. Although a
band-pass filter (BPF) can be added before the limiting amplifier to suppress the interference, it needs to have a high quality
when the input frequency is above few-hundred MHz. On the other hand, the mixer-based analog phase
detector has a relatively linear transfer function before the 1 dB
compression point, which allows the RX to accommodate the
interference to a certain level without requiring a high-Q BPF.
The interference is filtered by the LPF after the mixing.
The analog phase detector has an amplitude-dependent
phase-to-voltage transfer function, which makes the proposed
PDC loop sensitive to amplitude fluctuation, e.g., channel
fading or a change of link distance. Since the targeted reception
signals (i.e., FSK, GFSK, HS-OQPSK) contain only binary
frequency-modulated information, a 1 bit comparator is used in
the PDC. The 1 bit quantization not only gets rid of amplitude
information, it also acts as a limiter after the LPF, which allows
the PDC to benefit from the capture effect [13]. When two
constant envelope signals are at the input of a limiter, the
weaker one no longer exists or is significantly weakened at the
output of the limiter. This means that only the desired signal is
present after the limiter (provided the interference is sufficiently
suppressed by the LPF), suppressing leakage of interference
into the digital phase accumulator. Since the SIF-PDC tracks
input modulated phase by selecting the appropriate LO phase,
the feedback path is effectively clamped to the appropriate
channel, and the drift to the interference frequency is prevented, this in turn makes low pass filtering on the interference
effective. The combination of the analog phase detector, the
LPF, and the capture effect from the 1 bit quantization improve
the overall interference robustness of the PDC loop.
Note that the capture effect of the 1 bit quantization also indicates that the interference rejection of the presented PDC loop
heavily relies on the analog filtering. If the interference is not
sufficiently suppressed by the analog LPF, the phase tracking of
the PDC loop will be seriously disturbed, and the signal quality
of the PDC degraded.
B. Sliding-IF Phase-to-Digital Converter (SIF-PDC)
One of the major design challenges of the proposed PDC
based on the phase rotator is to minimize the power consumption of the multi-phase LO generation. In the present work
[14], the PDC further incorporates a sliding-IF frequency plan
(SIF-PDC) because it effectively reduces the power consumption of multi-phase LO generation [2], [4].
As shown in Fig. 2(c), a fractional-N PLL locked to a 32 MHz
reference clock is employed to generate a stable carrier, which
guarantees the carrier frequency stability. The VCO is locked at
8/9 of the input center frequency (e.g.,
2.475 GHz) as the
LO of the RF mixer (e.g.,
2.2 GHz). Then it is further
divided by 8 (e.g.,
275 MHz)) to provide a 16-phase
LO for the IF mixer which also performs the phase detection.
The detected phase difference
is then filtered by the LPF
and digitized by the comparator. The 1 bit comparator output
represents the binary frequency demodulated data



Fig. 2. (a) The proposed phase-to-digital conversion loop with a phase rotator. (b) The output phase range of the analog phase integration/quantization and digital
phase integration. (c) The simplified block diagram of the proposed RX with SIF-PDC.

and a 4 bit digital phase integrator output represents the demodulated phase
. The phase selector picks one of 16
phases according to
. More LO phases can be generated

to reduce the quantization error by further dividing the LO

frequency. However, the image frequency is also moving closer
to the center frequency of the desired signal, and this makes the



Fig. 3. A simulated CFO detection and compensation with the proposed SIF-PDC.

RX being more difficult to filter out the image with an intrinsic

band-pass characteristic of the LNA. With the current frequency
plan, the image signal is approximately 550 MHz away, and the
input impedance matching along with the LC-tank of the LNA
provides approximately 25 dB image rejection.
SIF-PDC forces the selected phase to be synchronized with
the input modulated phase
, and it is independent from
the carrier generation loop, i.e., the fractional-N PLL. Hence,
the signal demodulation bandwidth and the PLL bandwidth can
be separately optimized. While the PLL bandwidth is preferably low (around 100 kHz) to insure optimum phase noise and
a stable carrier frequency, the demodulation bandwidth of the
SIF-PDC can be higher to allow the RX to demodulated the targeted FSK/PSK signals up to few Mbps.
C. The Digital Baseband of the Proposed Phase-Domain RX
In comparison to the Cartesian I/Q RXs, the phase-domain
RXs simplify the digital baseband (DBB) design. First of all,
two high-resolution I/Q ADCs (typically more than 8 bits) are
replaced by a 1 bit comparator and a 4 bit digital phase integrator
in the proposed SIF-PDC, so the input data dimension in DBB
has been reduced significantly. Second, an extra Cartesian-tophase conversion in the digital domain as used in the conventional I/Q RXs is no longer required because the SIF-PDC directly outputs digitized phase information.
Furthermore, when compared to the Cartesian I/Q RXs, the
phase-domain RX is less sensitive to amplitude fluctuation, and
the carrier frequency offset (CFO) can be easily detected and
compensated. This is especially important in certain standard,
e.g., Bluetooth Low Energy, that specifies the digital baseband

should adjust the signal amplitude and detect a large CFO within
a very short preamble.
As mentioned in Section III-A, the 1 bit quantization in the
SIF-PDC makes the proposed RX less sensitive to the amplitude
fluctuation and more tolerant to the amplitude saturation. Cartesian I/Q RXs adapt to different input levels by adjusting both RF
and the analog baseband gain to avoid the saturation due to the
limited ADC dynamic range. On the other hand, the SIF-PDC
increases dynamic range by processing in phase domain, so only
the RF gain needs to be adjusted to protect the phase detector
from compression. Hence, the automatic gain control (AGC) algorithm is largely simplified.
Since the CFO translates to a slow and uni-directional phase
drift, it can be easily detected within a preamble by monitoring
the output digitized phase
of the SIF-PDC. Then it can
be immediately compensated during payload.
Fig. 3 shows the simulated CFO detection and compensation with a short 8-symbol preamble 01010101 (similar to Bluetooth Low Energy), and a repeat test pattern of
01-0000-1111-0101-01 as payload. A CFO up to 100 ppm
is added, which is detected during a short 8-symbol preamble
(01010101) by monitoring the phase output,
, of the
SIP-PDC. It is then directly compensated during payload. In
this simulation, the packet arrives after a random delay. First
the radio detects only noise, then after energy detection the
preamble detector is switched on. The preamble detector is
designed to cope with 100 ppm CFO and only requires a
portion of the preamble. When the preamble is detected, the demodulated output is passed to the DBB for further processing.
In the figure we show both the CFO compensated signal and
the un-compensated signal.



Fig. 4. (a) A equivalent frequency-domain equivalent linear model of SIF-PDC, and the signal and noise transfer functions, (b) simulated LPF and comparator
waveform with and without phase non-linearity.


A phase-domain approximated linear model of the SIF-PDC,
is the
which assumes the digitized frequency output
main interest, is presented in Fig. 4(a) and discussed in detail
further down in this section.
The phase detector implements a phase subtraction and has an
amplitude-dependent phase-difference-to-voltage gain of
, where A is the input amplitude of the phase detector
[16]. The LPF has a low-pass transfer function of
The comparator functions as a bit slicer in the SIF-PDC, detecting only the polarity of the LPF output and boosting it to
a rail-to-rail signal regardless of its input amplitude. The comparator has a non-linear signal-dependent gain
, and introduces frequency quantization noise,
The phase rotator, which functions as a digitally-controlled
oscillator (DCO), has an equivalent continuous-time transfer
function of
, and adds phase quantization noise

due to the discrete phases. The phase rotator gain

is determined by the accumulation rate of the digital
phase integrator. This parameter also represents the full scale
of the frequency digitization range of the SIF-PDC.
Similar to a
ADC, the SIF-PDC performs a 1st-order
1 bit frequency-to-digital conversion. The frequency responses of the signal transfer function (STF), and the noise
transfer function of both frequency and phase quantization noise
, are listed in Fig. 4(a).
Since the comparator gain
is approximately inversely
proportional to its input amplitude, it can be approximated as
The LPF is first modeled as a constant gain in (1). Note the
comparator is an extremely non-linear component and its gain is
strong signal dependent, so it is difficult to model a comparator
as a linear component. Therefore the actual
should be



Fig. 5. The simplified block diagram and schematic of the IF mixer, LPF and the dynamic comparator.

found from extensive numerical simulations to avoid a misleading result predicted by the linear model [17].
The loop bandwidth of the SIF-PDC can be derived from the
linear model as

still valid. The open-loop, signal and noise transfer functions of

the SIF-PDC are re-derived as

Equation (2) indicates the loop bandwidth of the SIF-PDC can
be approximated to the accumulation rate of digital phase integrator,
. In addition, the dependency to the input signal
amplitude A of the phase detector is compensated by the comparator, so the overall SIF-PDC transfer function is now amplitude independent.
The loop bandwidth selection of the SIF-PDC is determined
by the requirements of the interference rejection, quantization
noise suppression, and the frequency digitization range. In-band
quantization noise of the SIF-PDC is suppressed by a high-pass
NTF, so
should not be too low. At the mean time, the lowpass STF helps to suppress out-band unwanted components, so
is preferably low. Moreover, the loop bandwidth is approximately equal to the full scale of the frequency digitization
range, so it has to be at least equal or larger than the deviation
of the targeted frequency-modulated signals.
A LPF with a cut-off frequency of
can be employed in
the SIF-PDC to further assist the suppression of out-band interfere, so the interference rejection requirement is decoupled from
the loop bandwidth selection. However, the presented SIF-PDC
is no longer a simple 1st-order loop when a LPF is used, so the
loop stability should be taken into account. Assuming LPF is
a 1st-order filter to simplify the analysis, and the LPF bandwidth
is significant larger than the loop bandwidth
and the signal bandwidth, so the assumption in (1) and (2) are

The damping factor
expressed as

of this 2nd-order system then can be

To avoid peaking and have a stable 2nd-order system the
damping factor should be larger than 0.7, which indicates
the LPF bandwidth
should be at least twice as the loop
. Therefore, to optimize between interference
rejection, quantization noise suppression, frequency digitization range and the loop stability the loop bandwidth
is chosen to match the deviation frequency f, and the LPF
bandwidth is selected to be approximately 3 times of the loop
bandwidth, i.e.,
Phase quantization noise due to discrete phases degrade
the RX demodulation quality, and it can be reduced by either
increasing the number of LO phases or by employing noise
shaping. The former is not preferred as it leads to higher
power consumption and low image rejection. The high-pass
noise shaping suppresses in-band phase quantization noise



Fig. 6. Simplified schematic of the multi-phase generation and the phase selector.

without increasing RF hardware. It improves phase resolution

by approximately
times [17], where OSR is the
oversampling ratio, i.e.,
/data rate. The OSR in this work
is 16 ( 32 MHz/2 Mbps), and the noise shaping equivalently improves phase resolution from 22.5 degrees (i.e., 360
degrees/16 phases) to below 1 degree.
The phase non-linearity degrades noise shaping and introduces fluctuation at the LPF output, which could increase the
disturbance of the comparator. Fig. 4(c) shows the simulated
LPF and comparator waveform with and without phase non-linearity. A binary-FSK input signal with a slow periodic 0-1-0-1
pattern is provided, allowing SIF-PDC to sweep all of 16 phases
in each symbol. Since the binary frequency-modulated signals
have a large error margin, and the post digital filter can remove
these errors, the phase non-linearity is not a critical issue in the
targeted applications. The simulation shows the phase linearity
can be relaxed to approximately 30 degrees, which suggests a 16
LO phases can already meet the requirement if they are monotonic. The monotonicity can be guaranteed by employing a divider-based multi-phase generator.
Last but not least, 1st-order
modulators have a potential
issue of limit cycle, resulting in idle tones with certain DC excitation [17], and this usually requires dithering with a random
pattern to break the periodicity. The proposed SIF-PDC does not
suffer from such issue as the idle tones are spread by RX thermal
noise and an input signal that modulates with random data.
In this section, the designs of several key building blocks are
described in details.

A. RF Circuits (LNA and RF Mixer)

A single-ended LNA [2], also functions as an image rejection
filter, is used for low power consumption and avoiding a lossy
A push-pull mixer [2] structure is implemented to improve
both the gm efficiency and noise performance. Moreover, this
structure inherently provides a lossless single-ended to differential conversion. The LO feed-through is cancelled by the proposed structure.
The combination of LNA and mixer gain is approximately
30 dB and it achieves a noise figure of 5 dB. The total power
consumption is 1.05 mW.
B. IF and Analog Baseband Circuits
The IF signal is further down-converted by a single-channel
passive mixer, as shown in Fig. 5. A 25% duty-cycling LO
which helps to avoid noise leakage between I and Q channels
[18], is not required because of the single-channel implementation in the SIF-PDC, which simplifies the LO generation.
As mentioned in Section III-A, a higher-order LPF before
hard limiting enhances the capture effect of the FM demodulation. A 3rd-order Butterworth LPF with a programmable bandwidth (0.4 to 2 MHz) is implemented with the active-RC structure, and it provides an extra suppression to the interference and
prevents aliasing.
A dynamic comparator [19] sampled at 32 MHz provides a
1 bit demodulated frequency data. The comparator delay is less
than 2 ns, so the output data will be ready before the rising edge
of the next clock which triggers the digital phase integrator.



Fig. 7. (a) Measured time-domain demodulated waveform of a 2 Mbps HS-OQPSK and a 1 Mbps GFSK with the proposed SIF-PDC. (b) Measured comparator
output spectrum with a sinusoidal frequency-modulated input signal,

C. Multi-Phase Generator and Phase Selector

The implementation of the multi-phase LO generator and the
phase selector are shown in Fig. 6. The 16 LO phases are generated through a frequency division of 8 that is performed in two
cascaded stages (/2 and /4). In comparison to a single stage implementation with 8 D-flip-flops (DFFs) connected as a ring, this
approach relaxes the timing requirements and reduces power
consumption by half. The first divide-by-2 stage (/2) is realized
with dynamic-load DFFs [2] for their high-speed, low-power
and low-voltage features. Its 4-phase output triggers a parallel
divide-by-4 stages (/4) to further produce 16 phases.
A phase sequence reset eliminates the ambiguous state by
is always
guaranteeing the even-phase sequence
triggered before the odd-phase sequence

start up. Finally, the phase selection is implemented by a 4 bit

digital multiplexer.
This RX is implemented in a 90 nm CMOS technology.
The measured time-domain waveform is shown in Fig. 7(a).
A 2 Mbps HS-OQPSK (similar to the modulation of ZigBee)
and a 1 Mbps GFSK (similar to the modulation of Bluetooth
Low Energy) signals are generated with a fixed-pattern of
1111-0000-1010. Long 1s and long 0s test the slow
response of the SIF-PDC, while 1010 tests the fast response.
The proposed SIF-PDC can track the frequency/phase modulations and directly provide demodulated digital outputs.
Fig. 7(b) shows the measured comparator output spectrum. In
order to measure the quantization noise floor of the SIF-PDC, a


sinusoidal frequency modulated (FM) signal is provided as the

input. The phase rotator gain
of the SIF-PDC, i.e., the
full scale of the frequency digitization, is set to 500 kHz. The
input FM signal has a period of 50 kHz, and a deviation frequency of 480 kHz (which is slightly lower than the full scale).
The measured comparator spectrum matches well with the simulation result based on the linear model presented in Section IV.
It shows the in-band quantization noise is high-pass shaped,
and the out-band noise is filtered by the LPF with 1.5 MHz
bandwidth (i.e., 3 times of
for stability). The measured
low-frequency quantization noise is slightly higher than the simulation, which is mainly due to phase non-linearity. This phase
non-linearity can also be observed from the small fluctuation at
LPF output in Fig. 7(a).
Fig. 8(a) shows the measured raw bit error rate (BER) of
2 Mbps HS-OQPSK signal. The proposed RX achieves a sensitivity level of 92 dBm, where the sensitivity is defined as the
input power corresponding to BER of 10 .
The adjacent channel interference rejection (ACR) is measured with an un-modulated CW tone as interference and a modulated desired signal with a level that is 3 dB higher than the
sensitivity [21]. As shown in Fig. 8(b), the measured ACR is
3/12/17 dB at the offset frequency of 2/4/6 MHz, respectively.
The 2nd and 3rd ACR are approximately 810 dB lower than
the conventional I/Q RX in [2] but 2030 dB better than the
super-regenerative RX in [1], which offer sufficient selectivity
for the target applications.
Fig. 8(c) shows the power consumption breakdown of the
SIF-PDC. The RF circuits (i.e., LNA and RF mixer) consume almost 50% of the total power. The proposed SIF-PDC shifts parts
of the RF signal processing and power consumption from the
forward signal path (e.g., mixers, LPF and ADCs) to the feedback LO path (i.e., multi-phase generation), which now consumes the 2nd largest portion of total power (around 25%). This
approach leverages the advantages in nanometer technologies,
as the power consumption and precision of the multi-phase generation can be further improved by the fast switching speed
of the nanoscale CMOS devices. As a result, the continuous
technology scaling will benefit the proposed phase-domain RX
Table I summarizes and compares the performance of the presented RX with the state-of-the-art low-power 2.4 GHz RXs.
The proposed RX further reduces the power consumption by up
to nearly 40% compared to the previous work [2] at 2 Mbps,
thus leading to an excellent energy efficiency of 1.2 nJ/bit, but
without dramatically degrading its sensitivity as in [5] or selectivity as in [1]. A RX figure of merit (FoM) for low-power
applications is defined as an inverse of energy efficiency that
multiplies RX sensitivity, which implies the RX sensitivity can
be improved by either reducing data rate or by increasing power
consumption. The presented phase-domain RX improves the energy efficiency while maintaining excellent sensitivity, thus resulting in an FoM of 181 dB.
Fig. 9 benchmarks the state-of-the-art 2.4 GHz ultra-low
power RXs. Similar to the RX FoM defined in Table I, a general
trend showing the RX sensitivity is inversely proportional to


Fig. 8. (a) Measured bit error rate of a 2 Mbps HS-OQPSK signal, (b) adjacent
channel rejection, and (c) power breakdown of the proposed RX.

its energy efficiency. There are two RX groups benchmarked

in Fig. 9: ASK energy-detection RXs and FSK/PSK RXs. The
energy-detection ASK RXs typically possess excellent energy
efficiency (typically in the range of 0.1 to 1 nJ/bit) mainly
because they only detect the on/off energy of the desired signals. These ASK RXs typically have inferior sensitivity due to
the lack of a precise and stable LO that provides selectivity.
Hence, a wider filter bandwidth is required, leading to a poorer
noise performance. On the other hand, the FSK/PSK RXs typically hold a better sensitivity at the expense of higher power
consumption (i.e., worse energy efficiency), which is mainly




Fig. 9. Benchmark of low-power 2.4 GHz RXs.

consumed by the LO generation (e.g., PLL). The presented

phase-domain RX achieves comparable energy efficiency
(1.2 nJ/b) as energy detection ASK RXs, while maintains a
similar sensitivity level as the FSK/PSK RXs.
The microchip photo is shown in Fig. 10. The total core chip
area is around 0.9 mm .

A new phase-domain RX based on a sliding-IF phase-to-digital converter (SIF-PDC) for directly demodulating and
digitization FSK/PSK signals is presented in this paper.
In comparison to the conventional Cartesian I/Q RXs, the
proposed SIF-PDC saves RX power consumption without



Fig. 10. Micro chip photo.

compromising its sensitivity and selectivity performance. The

proposed SIF-PDC transforms the signal processing from the
analog amplitude domain to the digital phase domain, making
it favorable for low-voltage operation and technology scaling.

The authors would like to thank IMEC-Netherlands
Ultra-low power DSP and Wireless System teams for the
support of digital design and the testing.

[1] M. Vidojkovic et al., A 2.4 GHz ULP OOK single-chip transceiver
for healthcare applications, in IEEE ISSCC Dig. Tech. Papers, 2011,
pp. 458459.
[2] Y.-H. Liu et al., A 1.9 nJ/bit 2.4 GHz multistandard (Bluetooth low
Energy/ZigBee/IEEE802.15.6) transceiver for personal/body area networks, in IEEE ISSCC Dig. Tech. Papers, 2013, pp. 446447.
[3] S. Chakraborty et al., An ultra low power, reconfigurable, multi-standard transceiver using fully digital PLL, in Proc. Symp. VLSI Circuits,
2013, pp. 148149.
[4] A. Wang et al., A 1 V 5 mA multimode IEEE 802.15.6/Bluetooth
low-energy WBAN transceiver for biotelemetry applications, in IEEE
ISSCC Dig. Tech Papers, 2012, pp. 300301.
[5] J. Masuch and M. Delgado-Restituto, A 1.1-mW-RX 81.4-dBm
sensitivity CMOS transceiver for bluetooth low energy, IEEE Trans.
Microw. Theory Tech., vol. 61, no. 4, pp. 16601673, Apr. 2013.
[6] P. Quinlan et al., A multimode 0.3200-kb/s transceiver for the 433/
868/915-MHz bands in 0.25- m CMOS, IEEE J. Solid-State Circuits,
vol. 39, no. 12, pp. 22972310, Dec. 2004.
[7] H. Gustat and F. Herzel, Integrated FSK demodulator with very high
sensitivity, IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 357360,
Feb. 2003.
[8] I. Galton, W. Huff, P. Carbone, and E. Siragusa, A Delta-Sigma
PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10
MHz FM signal, IEEE J. Solid-State Circuits, vol. 33, no. 12, pp.
20422053, Dec. 1998.
[9] J. Craninckx and M. Steyaert, A 1.75-GHz/3-V dual-modulus
divid-by-128/129 prescaler in 0.7- m CMOS, IEEE J. Solid-State
Circuits, vol. 31, no. 7, pp. 890897, Jul. 1996.
[10] S. Kashmiri, S. Xia, and K. Makinwa, A temperature-to-digital converter based on an optimized electrothermal filter, IEEE J. Solid-State
Circuits, vol. 40, no. 7, pp. 20262035, Jul. 2009.
[11] Y.-H. Liu and T.-H. Lin, A wideband PLL-based G/FSK transmitter
in 0.18 m CMOS, IEEE J. Solid-State Circuits, vol. 44, no. 9, pp.
24522462, Sep. 2009.

[12] S. Sidiropoulos and M. Horowitz, A semidigital dual delay-locked

loop, IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 16831692,
Nov. 1997.
[13] K. Leentvaar and J. Flint, The capture effect in FM receivers, IEEE
Trans. Commun., vol. COM-24, no. 5, pp. 531539, May 1976.
[14] Y.-H. Liu, A. Ba, J. van den Heuvel, K. Philips, G. Dolmans, and H. de
Groot, A 1.2 nJ/bit 2.4 GHz receiver with a sliding-IF phase-to-digital
converter for wireless personal/body area networks, in IEEE ISSCC
Dig. Tech Papers, 2014, pp. 166167.
[15] W. Kluge et al., A fully integrated 2.4 GHz IEEE 802.15.4 compliant
transceiver for ZigBee applications, in IEEE ISSCC Dig. Tech Papers,
2006, pp. 372374.
[16] R. E. Best, Phase-Locked Loops, 2nd ed. New York, NY, USA: McGraw-Hill, 2003.
[17] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. New York, NY, USA: Wiley-Interscience, 2005.
[18] A. Mirzaei et al., Analysis and optimization of current-driven passive
mixers in narrowband direct-conversion receivers, IEEE J. Solid-State
Circuits, vol. 44, no. 10, pp. 26782688, Oct. 2009.
[19] P. Harpe et al., A 26 W 8 bit 10 MS/s asynchronous SAR ADC for
low energy radios, IEEE J. Solid-State Circuits, vol. 46, no. 7, pp.
15851595, Jul. 2011.
[20] B. Razavi, K. F. Lee, and R. H. Yan, Design of high-speed, low-power
frequency dividers and phase-locked loops in deep submicron CMOS,
IEEE J. Solid-State Circuits, vol. 30, no. 2, pp. 101109, Feb. 1995.
[21] ETSI EN 300 440-1 V1.3.1, Electromagnetic Compatibility and Radio
Spectrum Matters, Jul. 2001.

Yao-Hong Liu (S04M09) received the Ph.D.

degree from National Taiwan University, Taiwan, in
He joined Terax Communication, Taiwan, from
2002 to 2003, working on RFIC for Bluetooth.
Between 2003 to 2006, he was with VIA technology, Taiwan, where he was involved in GSM and
WCDMA transceiver products. He joined Mobile
Devices, Taiwan, in 2006 to work on OFDM-based
transceivers for WiFi and WiMAX. Since 2010, he
has been a Senior Researcher at IMEC-Holst Centre,
The Netherlands, where his research focuses on the ultra-low power RF/analog
circuits for wireless healthcare and Internet-of-Things (IoTs) applications.

Ao Ba (M14) received the B.E. degree in microelectronics from Sun Yat-Sen University, Guangzhou,
China, in 2009, and the M.S. degree (cum laude)
in electrical engineering from Delft University of
Technology, Delft, The Netherlands, in 2011.
In 2011, he joined Holst Centre/imec, The Netherlands, as a researcher. His technical interests include
ultra-low power RF and mixed-signal IC design and
digitally-assisted RF IC design.

Johan H. C. van den Heuvel (S01M11) received

the M.Sc. and Ph.D. degree in electrical engineering
from the Eindhoven University of Technology, The
Netherlands, in 2006 and 2012, respectively. In
2007, he started working towards the Ph.D. degree
at the Eindhoven University of Technology, in the
Mixed-Signal Microelectronics group and within
Philips Research in the Cosine and ESSI group.
He was awarded the Veder Prijs 2012 for his
contribution to MIMO receiver power reduction.
In April 2011 he moved to IMEC-NL, where he is
working as a wireless research scientist. His current research interests include
low-power and high-speed mixed-signal circuits and architectures, multiple
antenna systems, ultra wideband communication, channel measurements, and
digital baseband algorithms.


Kathleen Philips (M03) received the M.Sc. degree in electrical engineering from the Katholieke
Universiteit Leuven, Belgium, in 1995. She then
joined the Mixed-Signal Circuits and Systems group
of Philips Research Laboratories, Eindhoven, The
Netherlands, where she designed mixed-signal
CMOS circuits. For her work on sigma-delta conversion, she received the Ph.D. degree from Eindhoven
University of Technology, The Netherlands, in 2005.
Since 2007, she has been with the Wireless group
of the Holst Centre/IMEC, The Netherlands, where
she has been working on ultra-low power radio IC design. As a principal researcher, she is now leading this activity and she is a program manager for the
ultra-low-power wireless program.

Guido Dolmans (M13) received the M.Sc. and

Ph.D. degrees in 1992 and 1997, from the Eindhoven
University of Technology, The Netherlands.
He worked at Philips Research Laboratories
from 1997 to 2006 as a senior scientist/project
leader. From 2006, he has been working at Holst
Centre/IMEC, The Netherlands. His current position
is Senior Principal Scientist/R&D manager. His
primary research interest is system architecture/IC
design of ultra-low-power radio transceivers. His
other research interests are wireless communications


PHY and MAC layer design, radio wave propagation, smart antenna design,
and RF and microwave IC design. He has (co)-authored over 100 papers in
scientific/technical journals and proceedings, and holds 14 U.S. patents. He
is also associated with Eindhoven University of Technology (TU/e) as a full
Professor of the chair Person-Centric Sensor Microelectronic Systems.

Harmke De Groot (M11) holds a Master of Science in Electrical and Electronics Engineering from
the University of Technology Eindhoven (1997) and
an MBA from TIAS business school (2013).
She is program director at Holst Centre and imec
in the field of ultra-low power circuits and sensors.
Her team contributes to the Internet of Things revolution by developing innovative short-range radios,
DSP, sensor and harvester solutions that enable smart
sensor networks and other ultra-low power applications. She worked at NXP, Philips Research and Microsoft before joining Holst Centre and imec in 2008.
Harmke De Groot is a member of several expert and standardization groups
and (co-)author of over 60 publications and a book on embedded system design.