Put a transistor here,

what kind of that?

Load resistor

switch

VTC

Logic Symbol

Load resistor
abruptly

switch

vI below the reference voltage VREF

Large change at in
Small change at output

Wave form?

VDD

What is the behavior of this circuit?

Load line

Output characteristics

VDS

VDS =
ID

VDS

= VGS

Deeper look

0.82V

1.42V

Problem

VI

Problem

Triode region

1.42V

Need to know ID to find W/L and how?

R=?

SUMARY

NMOS inverter with resistive load:

used to introduce the concepts
associated with static logic gate design
simple discrete component logic gate
Static power dissipation
IC realizations do not use resistive loads
resistor would take up far too much area.
Resistor with a thickness of 1 m in a silicon region with a resistivity of
0.001 .cm.
A 95-k load resistor would require the ratio of L/W to be

Transistor Alternatives to the Load Resistor

Not used

Saturated load inverter

Linear load inverter.

VGS2 = VDS2 = VDD VDS1

VG2

VO,max

Keep in mind: VO,max = VG2 VTN2

VI = VDD

VG2

Check assumption
VIH = 1.12V; VOL = 0.38 VGS1 VTN1 > VDS1

Need to update iteratively VTNL and VOL

Pinchoff, VDS2 = -VTN2

VDS2 = VDD VDS1

VDS2 = 0

Pinchoff, VDS2 = -VTN2

VI = VGS1

VDS2 = VDD VDS1

VDS2 = 0

VO= VDS1

For VI near VIL, VDS of Ms will be large

and that of ML will be small
switching device is saturated
load device is in its linear region

vSB = VDD

VTNL = -0.5V VIL= 0.9V

Check operating region assumptions:

VGS1 VTN1 = 0.9V - 0.6V = 0.3V < VDS1 = 2.37 M1: Saturation
VGS2 VTN2 = 0V (- 0.5V) = 0.5V > VDS2 = 2.5V - 2.37V M2: Triode

VTNL = -1V;
VIL = 0.965V; VO = 2,41V

vSB = VDD

VTNL = -0.52V;
VIL = 0.79V; VO = 2,456V

(2)

VTNL = -0.51V;
VIL = 0.787V; VO = 2,456V

(1)

Initiate with VTNL = -1V

1. Choose a starting value for VTNL.

2. Calculate the corresponding value of VIL using Eq. (1).
3. Use the values VTNL and VIL to calculate a new estimate of
vO using Eq. (2).
4. Use vO to calculate an updated value for VTNL.
5. Repeat steps 2 and 3 until the convergence is achieved.

MS in the linear region

ML in the saturation region

VTNL = -1V;
VO = 0.52V; VIH = 1,64V
VTNL = -0.858V;
VO = 0.447V; VIH = 1,493V

(1)

VTNL = -0.875V;
VO = 0.456V; VIH = 1,511V
VTNL = -0.873V;
VO = 0.455V; VIH = 1,51V

Iterative Update of VIH and vO

(2)

Initiate with VTNL = -1V

1. Choose an initial value of VTNL.

2. Calculate the corresponding values of VO and VIH from Eq. (1)
3. Use the new value of VO and Eq. (2) to improve the estimate
of VTNL.
4. Repeat steps 2 and 3 until the process converges.

MS in the linear region

ML in the saturation region
Check operating region assumptions:
MS : VGS VTNS = 1.51V 0.6V = 0.91V > VDSS = VO = 0.46V Linear

ML : VGS VTNL = 0 (-0.873V) < VDSL = VDD - VO = 2.5V -0.46V Saturation

0.33
0.93

 depletion-mode NMOS logic was the dominant technology

for many years in the design of microprocessors.
large static power dissipation inherent in NMOS logic
eventually limited further increases in IC chip density
rapid shift took place to the more complex CMOS technology