Features
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Marking Information
Applications
RT7247Ax
GSPYMDNN
x : H or L or N
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Wireless AP/Router
Set-Top-Box
Industrial and Commercial Low Power Systems
LCD Monitors and TVs
Green Electronics/Appliances
Point of Load Regulation of High-Performance DSPs
VIN
VIN
CIN
CBOOT
RT7247A
SW
Chip Enable
VOUT
R1
EN
SS
CSS
CC
GND
DS7247A-02
December 2012
COUT
FB
RC
R2
COMP
CP
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1
RT7247A
Ordering Information
Pin Configurations
RT7247A
(TOP VIEW)
Package Type
SP : SOP-8 (Exposed Pad-Option 2)
Lead Plating System
G : Green (Halogen Free and Pb Free)
H : UVP Hiccup
L : UVP Latch-Off
N : UVP Disabled
BOOT
VIN
SW
GND
GND
EN
COMP
FB
9
4
SS
Note :
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
Pin Name
Pin Function
Bootstrap for High Side Gate Driver. Connect a 0.1F or greater ceramic
capacitor from BOOT to SW pins.
Input Supply Voltage, 4.5V to 18V. Must bypass with a suitable large ceramic
capacitor.
BOOT
VIN
SW
GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
FB
Feedback Input. It is used to regulate the output of the converter to a set value
via an external resistive voltage divider.
COMP
EN
SS
4,
9 (Exposed Pad)
Enable Input. A logic high enables the converter; a logic low forces the IC into
shutdown mode reducing the supply current to less than 3A. Attach this pin
to VIN with a 100k pull-up resistor for automatic startup.
Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor
from SS to GND to set the soft-start period. A 0.1F capacitor sets the
soft-start period to 13.5ms.
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DS7247A-02
December 2012
RT7247A
Function Block Diagram
VIN
Internal
Regulator
Oscillator
Slope Comp
Shutdown V V
A
CC
Comparator
1.2V
Foldback
Control
+
-
0.4V
Lockout
Comparator
-
5k
EN
V
RSENSE A
BOOT
UV
Comparator
1.8V
Current Sense
Amplifier
+
+
Current
Comparator
VCC
150m
SW
130m
GND
6A
0.8V
SS
+
+EA
-
FB
COMP
Operation
Shutdown Comparator
UV Comparator
Internal Regulator
Provide internal power for logic control and switch gate
drivers.
Lockout Comparator
Oscillator
The oscillator provides internal clock and controls the
converter's switching frequency.
Foldback Control
Dynamically adjust the internal clock. It provides a slower
frequency as a lower FB voltage.
DS7247A-02
December 2012
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3
RT7247A
Absolute Maximum Ratings
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(Note 1)
Supply Input Voltage, VIN -----------------------------------------------------------------------------------------Switch Voltage, SW -----------------------------------------------------------------------------------------------<10ns -----------------------------------------------------------------------------------------------------------------VBOOT VSW ---------------------------------------------------------------------------------------------------------Other Pins Voltage ------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25C
0.3V to 20V
0.3V to (VIN + 0.3V)
5V to 25V
0.3V to 6V
0.3V to 20V
1.333W
75C/W
15C/W
260C
150C
65C to 150C
2kV
(Note 4)
Electrical Characteristics
(VIN = 12V, TA = 25C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VEN = 0V
--
0.5
Supply Current
--
0.8
1.2
mA
0.788
0.8
0.812
--
940
--
A/V
RDS(ON)1
--
150
--
RDS(ON)2
--
130
--
--
10
--
--
VREF
GEA
IC = 10A
Reference Voltage
Error Amplifier
Transconductance
High Side Switch
On-Resistance
Low Side Switch
On-Resistance
High Side Switch Leakage
Current
Upper Switch Current Limit
COMP to Current Sense
Transconductance
Oscillation Frequency
GCS
--
3.7
--
A/V
fOSC1
300
340
380
kHz
fOSC2
VFB = 0V
--
100
--
kHz
DMAX
VFB = 0.7V
--
93
--
Minimum On-Time
tON
--
100
--
ns
DS7247A-02
December 2012
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4
RT7247A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Logic-High
VIH
--
18
Logic-Low
Input Under Voltage Lockout
Threshold
Input Under Voltage Lockout
Hysteresis
Soft-Start Current
VIL
--
--
0.4
3.8
4.2
4.5
--
320
--
mV
ISS
VSS = 0V
--
--
Soft-Start Period
tSS
CSS = 0.1F
--
13.5
--
ms
Thermal Shutdown
TSD
--
150
--
EN Input Voltage
VUVLO
VIN Rising
VUVLO
Note 1. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
DS7247A-02
December 2012
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5
RT7247A
Typical Application Circuit
VIN
4.5V to 18V
2
CIN
10F x 2
BOOT
VIN
RT7247A
SW 3
Chip Enable
4, 9 (Exposed Pad)
GND
CBOOT
L
0.1F 10H
R1
75k
7 EN
8 SS
CSS
0.1F
FB 5
COMP
CC
3.3nF
RC
13k
VOUT
3.3V
COUT
22F x 2
R2
24k
CP
Open
R1 (k)
R2 (k)
RC (k)
CC (nF)
L (H)
COUT (F)
27
27
3.3
22
22 x 2
62
11.8
20
3.3
15
22 x 2
3.3
75
24
13
3.3
10
22 x 2
2.5
25.5
12
9.1
3.3
6.8
22 x 2
1.5
10.5
12
4.7
3.3
3.6
22 x 2
1.2
12
24
3.6
3.3
3.6
22 x 2
12
3.3
3.6
22 x 2
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DS7247A-02
December 2012
RT7247A
Typical Operating Characteristics
Efficiency vs. Output Current
100
3.33
90
3.32
VIN = 4.5V
VIN = 12V
VIN = 17V
70
60
Efficiency (%)
80
50
40
30
20
3.31
3.30
3.29
3.28
10
VOUT = 3.3V
3.27
0
0.25
0.5
0.75
1.25
1.5
1.75
10
12
14
16
18
0.85
3.305
0.83
0.84
0.82
0.81
0.80
VIN = 4.5V
VIN = 12V
VIN = 17V
0.79
0.78
0.77
3.300
3.295
VIN = 4.5V
VIN = 12V
VIN = 17V
3.290
3.285
0.76
VOUT = 3.3V
0.75
3.280
-50
-25
25
50
75
100
125
0.25
0.5
Temperature (C)
1.25
1.5
1.75
380
0.75
370
360
350
340
330
320
310
370
360
350
340
VIN = 4.5V
VIN = 12V
VIN = 17V
330
320
310
300
300
3
12
15
DS7247A-02
December 2012
18
-50
-25
25
50
75
100
125
Temperature (C)
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RT7247A
Load Transient Response
5.5
VOUT
(100mV/Div)
5.0
4.5
4.0
VIN = 12V
VIN = 17V
3.5
3.0
IOUT
(1A/Div)
2.5
VOUT = 3.3V
2.0
-50
-25
25
50
75
100
Time (100s/Div)
125
Temperature (C)
VOUT
(100mV/Div)
VSW
(5V/Div)
IOUT
(1A/Div)
IL
(1A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 1A to 2A
Time (100s/Div)
Time (2.5s/Div)
VIN
(5V/Div)
VIN
(5V/Div)
VOUT
(2V/Div)
VOUT
(2V/Div)
IL
(2A/Div)
IL
(2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div)
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Time (10ms/Div)
DS7247A-02
December 2012
RT7247A
Power Off from EN
Power On from EN
VEN
(5V/Div)
VEN
(5V/Div)
VOUT
(2V/Div)
VOUT
(2V/Div)
IL
(1A/Div)
IL
(1A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div)
DS7247A-02
December 2012
Time (10ms/Div)
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9
RT7247A
Application Information
Output Voltage Setting
Soft-Start
VOUT
R1
FB
RT7247A
R2
GND
BOOT
RT7247A
100nF
SW
0.8 0.1
13.5ms
6
REN
EN
RT7247A
CEN
GND
VIN
EN
REN
100k
EN
Q1
RT7247A
GND
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DS7247A-02
December 2012
RT7247A
Under Voltage Protection
Clamp Mode
Hiccup Mode
Clamp Mode
VOUT
(2V/Div)
Hiccup Mode
ILX
(1A/Div)
VOUT
(2V/Div)
IOUT = Short
Time (1ms/Div)
ILX
(1A/Div)
IOUT = Short
Time (25ms/Div)
Latch-Off Mode
L
VIN
VOUT
(2V/Div)
ILX
(2A/Div)
IOUT = Short
Time (25s/Div)
DS7247A-02
December 2012
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RT7247A
ripple current stays below the specified maximum, the
inductor value should be chosen according to the following
equation :
VOUT
VOUT
L =
1 VIN(MAX)
f
I
L(MAX)
VOUT IL ESR +
8fCOUT
Series
Dimensions
(mm)
TDK
VLF10045
10 x 9.7 x 4.5
TDK
TAIYO
YUDEN
SLF12565
NR8040
8x8x4
VIN
1
VOUT
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DS7247A-02
December 2012
RT7247A
P D(MAX) = (125C 25C) / (75C/W) = 1.333W
(min.copper area PCB layout)
P D(MAX) = (125C 25C) / (49C/W) = 2.04W
(70mm2copper area PCB layout)
The thermal resistance JA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design has been designed. If possible, it's useful to increase
thermal performance by the PCB layout copper design.
The thermal resistance JA can be decreased by adding
copper area under the exposed pad of SOP-8 (Exposed
Pad) package.
As shown in Figure 8, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 8.a), JA is 75C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 8.b) reduces the JA to 64C/W. Even further,
increasing the copper area of pad to 70mm2 (Figure 8.e)
reduces the JA to 49C/W.
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance JA. The Figure 9 of derating curves allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation allowed.
2.2
Four-Layer PCB
2.0
1.8
Copper Area
70mm2
50mm2
30mm2
10mm2
Min.Layout
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
DS7247A-02
December 2012
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RT7247A
Layout Consideration
VIN
GND
SW GND
VIN
CBOOT
BOOT
L
VOUT
REN
CSS
CIN
VIN
SW
GND
GND
CC
SS
EN
COMP
FB
RC
CP
R1
R2
COUT
VOUT
GND
Component Supplier
Part No.
Capacitance (F)
Case Size
C IN
MURATA
GRM31CR61E106K
10
1206
C IN
TDK
C3225X5R1E106K
10
1206
C IN
TAIYO YUDEN
TMK316BJ106ML
10
1206
COUT
MURATA
GRM31CR60J476M
47
1206
COUT
TDK
C3225X5R0J476M
47
1210
COUT
MURATA
GRM32ER71C226M
22
1210
COUT
TDK
C3225X5R1C22M
22
1210
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DS7247A-02
December 2012
RT7247A
Outline Dimension
H
M
EXPOSED THERMAL PAD
(Bottom of Package)
Y
J
C
I
D
Dimensions In Millimeters
Symbol
Dimensions In Inches
Min
Max
Min
Max
4.801
5.004
0.189
0.197
3.810
4.000
0.150
0.157
1.346
1.753
0.053
0.069
0.330
0.510
0.013
0.020
1.194
1.346
0.047
0.053
0.170
0.254
0.007
0.010
0.000
0.152
0.000
0.006
5.791
6.200
0.228
0.244
0.406
1.270
0.016
0.050
2.000
2.300
0.079
0.091
2.000
2.300
0.079
0.091
2.100
2.500
0.083
0.098
3.000
3.500
0.118
0.138
Option 1
Option 2
DS7247A-02
December 2012
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