by
Abraham Yoo
Abstract
In this thesis, next generation low-voltage integrated power semiconductor devices are
proposed and analyzed in terms of device structure and layout optimization techniques.
Both approaches strive to minimize the power consumption of the output stage in DC-DC
converters.
In the first part of this thesis, we present a low-voltage CMOS power transistor layout
technique, implemented in a 0.25m, 5 metal layer standard CMOS process. The hybrid
waffle (HW) layout was designed to provide an effective trade-off between the width of
diagonal source/drain metal and the active device area, allowing more effective
optimization between switching and conduction losses. In comparison with conventional
layout schemes, the HW layout exhibited a 30% reduction in overall on-resistance with
3.6 times smaller total gate charge for CMOS devices with a current rating of 1A.
Integrated DC-DC buck converters using HW output stages were found to have higher
efficiencies at switching frequencies beyond multi-MHz.
ii
iii
Acknowledgements
First of all, I would like to thank Prof. Wai Tung Ng for his supervision,
encouragement, and invaluable counsel throughout my Ph.D. program. Without whose
presence my development as both a student and an individual would not have progressed
as rapidly. I wish to further acknowledge Prof. Johnny Sin (Hong Kong University of
Science and Technology) and Yasuhiko Onishi (Visiting Scientist from Fuji Electric
Corp.) who have contributed to my knowledge in the field, which better enabled me to
carry out and finish my research project on time.
I would like to express appreciation to all the members in the Smart Power Integration
& Semiconductor Devices Research Group for their fruitful discussions over the course
of this research, particularly M. Chang, O. Trescases, H. Wang, E. Xu, G. Wei, and Q.
Fung. I would also like to express my appreciation to all the staff in Nanoelectronic
Fabrication Facility (NFF) at HKUST who provided me with various IC fabrication
support.
Financial support from the University of Toronto Open Fellowship, the Natural
Sciences and Engineering Research Council of Canada, and the Auto21 Network of
Centres of Excellence of Canada are gratefully acknowledged.
Lastly, I would like to extend my appreciation to my wife, Mia Yoo for her patience,
consideration and support during the past four years. She has been wonderful and a true
partner. Also, special thanks to my mother and parents-in-law for their constant support
and encouragement throughout the studies.
iv
Table of Contents
Table of Contents .............................................................................................................. v
List of Tables .................................................................................................................. viii
List of Figures ................................................................................................................... ix
List of Glossary .............................................................................................................. xiv
List of Symbols ............................................................................................................... xvi
Chapter 1 Introduction ..................................................................................................... 1
1.1 Technology and Market Trends in Power Semiconductors ...................................... 1
1.2 Advantages of Power MOSFET Devices ................................................................. 3
1.3 Application Fields for Current and Future Power MOSFETs .................................. 4
1.4 Thesis Objectives and Organization ......................................................................... 6
Chapter 2 Power MOSFETs a Brief Overview ........................................................... 7
2.1 Fundamentals of MOS Device .................................................................................. 7
2.2 Types of Power MOSFETs ..................................................................................... 11
2.2.1 Traditional Vertical Power MOSFETs ............................................................ 12
2.2.2 Traditional Lateral Power MOSFETs .............................................................. 14
2.3 CMOS-based Power MOSFETs ............................................................................. 18
2.3.1 Monolithic Integration: Standard CMOS Process ........................................... 18
2.3.2 CMOS Layout Techniques for Power Integrated Circuits ............................... 20
2.4 Super-Junction (SJ) Power MOSFETs ................................................................... 25
2.4.1 Device Concept and Characteristics ................................................................ 25
2.4.2 Current Status and Challenges of SJ Power MOSFETs .................................. 27
Chapter 3 Analytical Layout Modeling of Power MOSFET ...................................... 30
3.1 Analysis of Basic MOS Finger Structure................................................................ 30
3.2 Modeling of Conventional Multi-Finger (MF) Layout ........................................... 33
vi
vii
List of Tables
Table 3.1 Data for different N N matrix of RW layout structures .................................. 36
Table 3.2 Data for different N N matrix of HW layout structures .................................. 38
Table 3.3 Parameter Summary of Trench-Gate Power MOSFETs................................... 42
Table 3.4 Parameter Summary of Lateral-Diffusion Power MOSFETs ........................... 42
Table 3.5 Efficiency Simulation Conditions: Conventional Power MOSFETs ............... 43
Table 3.6 Parameter Summary of CMOS-based Power MOSFETs ................................. 44
Table 3.7 Efficiency Simulation Conditions: CMOS-based Power MOSFETs ............... 44
Table 3.8 Simulation Data Summary of MF, RW, and HW Layout Structures ............... 52
Table 4.1 Target Specification .......................................................................................... 54
Table 4.2 Summary of 5V power MOSFETs with Hybrid Waffle Layout Structure ....... 55
Table 4.3 Package Description of the Integrated HW Output Stage ................................ 67
Table 4.4 Summary of on-resistance measurements......................................................... 71
Table 4.5 Data comparison between simulated and measured on-resistances.................. 75
Table 4.6 Summary of Gate-Drive Power Calculated from Measurements ..................... 76
Table 5.1: Parameters considered for both process and device simulations ..................... 86
Table 6.1 Parameters and specifications of the SOI wafer used in the fabrication ........ 111
Table 6.2 Summary of SJ-FINFET process parameters ................................................. 126
Table 6.3 Summary of SJ-FINFET layout design rules .................................................. 128
Table 6.4 SJ-FINFET Mask Information ........................................................................ 129
viii
List of Figures
Fig. 1.1 Evolution of power semiconductors. ..................................................................... 2
Fig. 1.2 Annual estimate and forecast of worldwide power semiconductor market........... 3
Fig. 1.3 Power device technologies and applications with respect to their voltages and
current ratings. ....................................................................................................... 5
Fig. 2.1 Basic Structure of a MOS transistor (n-type MOSFET) ....................................... 9
Fig. 2.2 An equivalent circuit for n-type MOSFET showing the parasitic capacitances and
resistances. ............................................................................................................. 9
Fig. 2.3 Types of Power Semiconductor Devices ............................................................. 11
Fig. 2.4 Structure of V-MOSFET. .................................................................................... 12
Fig. 2.5 Structure of DMOSFET....................................................................................... 13
Fig. 2.6 Structure of UMOSFET....................................................................................... 14
Fig. 2.7 Basic Structure of LDMOSFET .......................................................................... 15
Fig. 2.8 A RESURF LDMOSFET structure at full depletion ........................................... 17
Fig. 2.9 Functional elements of smart power technology ................................................. 18
Fig. 2.10 A conventional multi-finger (MF) layout structure ........................................... 21
Fig. 2.11 A modified version of MF layout structure with wider metal layers ................ 22
Fig. 2.12 A conventional Regular Waffle (RW) layout structure ..................................... 22
Fig. 2.13 Cross-section of a SJ-DMOSFET...................................................................... 26
Fig. 2.14 Ron,sp versus BV for different power device technologies [62-70]. ................... 29
Fig. 3.1 A basic MOS finger layout with simple interconnect resistive components. ...... 30
Fig. 3.2 (a) Two different MOS finger layouts with min. and max. metal-1 widths, ....... 31
Fig. 3.3 (a) Ron and (b) Ron,sp vs. Wtotal for different numbers of MOS fingers. ............... 32
Fig. 3.4 Conventional MF layout structure with parasitic resistors. ................................. 33
Fig. 3.5 A MF NMOS layout (10 MOS fingers) structure with minimum design rules. .. 35
Fig. 3.6 Corresponding schematic resistance model of the MF NMOS layout. ............... 35
Fig. 3.7 Schematic of (a) 4 4 regular waffle layout and (b) the corresponding resistance
model. .................................................................................................................. 37
Fig. 3.8 Hybrid waffle structure: (a) a layout and (b) a corresponding resistance model. 39
Fig. 3.9 Simulated Ron and Qg data for different Lfinger values of HW layouts. ................ 40
ix
Fig. 3.10 FOM-1 & FOM-2 versus different Lfinger of HW layout structures. .................. 41
Fig. 3.11 FOM vs. Efficiency for conventional power MOSFETs. .................................. 43
Fig. 3.12 Efficiency vs. Conventional FOM for CMOS-based Power MOSFETs. .......... 45
Fig. 3.13 Cross-sectional views of Trench-gate, LDMOS, and CMOS power MOSFETs.
............................................................................................................................ 45
Fig. 3.14 Efficiency vs. New FOM for CMOS-based Power MOSFETs. ........................ 48
Fig. 3.15 Gate charge characteristics of (a) MF and (b) HW layout structures ................ 49
Fig. 3.16 RON and QG plots as a function of MF, RF and HW layout active areas. .......... 50
Fig. 3.17 Comparison of power conversion efficiencies for both MF and HW layout
structures as a function of switching frequency and for different load currents:51
Fig. 4.1 Power MOSFET Output Stage: (a) Layout and (b) Schematic ........................... 55
Fig. 4.2 HW_NMOS unit-cell: (a) Active, (b) M1, (c) M2, (d) M3, (e) M4, and (f) M5. 56
Fig. 4.3 HW_NMOS unit-cell: (a) Layout and (b) Schematic (w/o parasitics) ................ 57
Fig. 4.4 Gate Segmentations of NMOS array: (a) layout and (b) schematic. ................... 58
Fig. 4.5 Layout comparison between segments: (a) Gate_N<6> and (b) Gate_N<0>. .... 58
Fig. 4.6 HW_PMOS unit-cell: (a) Active, (b) M1, (c) M2, (d) M3, (e) M4, and (f) M5 . 59
Fig. 4.7 Gate Segmentations of PMOS array: (a) layout and (b) schematic. .................... 60
Fig. 4.8 Layout comparison between segments: (a) Gate_P<0> and (b) Gate_P<6>. ..... 60
Fig. 4.9 Power Connection Routing Layouts: (a) M1-M3 and (b) M4-M5 layers. .......... 61
Fig. 4.10 Metal stress relief pattern on a routing metal wire. ........................................... 61
Fig. 4.11 2kV HBM and 400 MM ESD protection circuit, (a) layout (b) schematic. ...... 62
Fig. 4.12 ESD Protection Circuit Under Input Pad: (a) layout and (b) schematic. ........... 63
Fig. 4.13 Power Clamp, esd_nclamp5v_ 500p4U, (a) layout and (b) schematic. ............ 64
Fig. 4.14 p-type high resistance poly-resistor, rphripoly, (a) layout and (b) schematic. .. 65
Fig. 4.15 Seal and guard ring layout. ................................................................................ 65
Fig. 4.16 A micrograph of an integrated output stage using Hybrid Waffle layout in
TSMC 0.25m standard CMOS technology...................................................... 66
Fig. 4.17 A micrograph of source/drain metal runners (M3-M5). .................................... 67
Fig. 4.18 A micrograph of the packaged HW chip. .......................................................... 68
Fig. 4.19 a) System Overview and b) X-ray Image of QFN-12 package. ........................ 68
Fig. 4.20 Test PCB: (a) layout (silkscreen-view) and (b) photograph. ............................. 69
Fig. 4.21 Test circuits for on-resistance measurements: (a) NMOS and (b) PMOS ........ 70
Fig. 4.22 Measured on-resistance vs. # of segments at different voltage ratings. ............ 73
Fig. 4.23 Comparison between simulated and measured on-resistances: ......................... 74
Fig. 4.24 Total dynamic and gate-drive power measurements. ........................................ 76
Fig. 4.25 Measured power conversion efficiency of HW output stage with a test
conditions: fs = 6.25MHz, Vin = 2.7V, Vout = 1.8V, L = 2.2 H, and C = 100nF.
............................................................................................................................ 77
Fig. 4.26 10MHz switching characteristic at Iout = 158mA. ............................................. 78
Fig. 4.27 Measured power conversion efficiency of HW segmented output stage at
10MHz switching frequency: Vin = 3.6V, Vout = 1.8V, L = 1H, and C = 56nF.
............................................................................................................................ 78
Fig. 5.1 Basic idea of SJ-FINFET structure: (a) a fin-gate and (b) with a SJ-drift region 81
Fig. 5.2 (a) Overview of the proposed lateral SJ-FINFET structure and (b) Schematic
cross-sections along the cut-lines: A-A and B-B .............................................. 83
Fig. 5.3 Ideal device structure of the proposed SJ-FINFET. ............................................ 85
Fig. 5.4 P-body formation of the SJ-FINFET: (a) a trench formation by reactive ion
etching process, (b) after 45 tilted B+ ion implantation and thermal annealing
process, (c) a doping concentration profile along X-cut line at X=2, and (d) a
doping concentration profile along Y-cut at Y=-3. ............................................. 88
Fig. 5.5 P-pillar formation of the SJ-FINFET structure: (a)-(d) are the cross-sections
along the B-B cut line after 12 tilted B+ ion implantation (left) and thermal
diffusion (right) steps and (e)-(h) are the corresponding doping profiles for
different B+ ion implantation doses. .................................................................... 90
Fig. 5.6 N+ source/drain contact formation of the SJ-FINFET: (a) after 45 tilted dualimplant of n-type dopant species (i.e. arsenic and phosphorus) and thermal
diffusion steps, and (b) a doping concentration profile along Y-cut line at Y=-3.
............................................................................................................................. 91
Fig. 5.7 Unit-cell of the SJ-FINFET: a) w/ and b) w/o any oxide materials .................... 93
Fig. 5.8 Contour plots of the electrostatic potential distribution in off-state for a proposed
SJ-FINFET with p-pillar impurity concentration of 9.25 x 1016 cm3 under charge
balance: a) w/ and b) w/o any oxide materials ................................................... 96
xi
Fig. 5.9 Contour plots of the electric field distribution in off-state for a proposed SJFINFET with p-pillar impurity concentration of 9.25 x 1016 cm3 under charge
balance: a) w/ and b) w/o refined mesh structure. .............................................. 97
Fig. 5.10 The relationship between BV and charge imbalance for the proposed SJFINFET with Ldrift of 3.0 m and 6.0 m, Wn = Wp = 0.3 m and trench depths
(Wside) of 2.0 m and 3.0 m. ............................................................................ 98
Fig. 5.11 I-V characteristics of the proposed SJ-FINFETs during off-state for various drift
region lengths. .................................................................................................... 98
Fig. 5.12 Transfer characteristics of the SJ-FINFET with Ldrift = 3.5 m. ....................... 99
Fig. 5.13 On-state simulations: (a) electron current density distribution and (b) output
characteristics of the SJ-FINFET with Ldrift =4.5 m and device area = 1 mm2.
.......................................................................................................................... 101
Fig. 5.14 I-V characteristics of the proposed SJ-FINFETs during on-state for various drift
region lengths. .................................................................................................. 102
Fig. 5.15 The trade-off relationship between BV and Ron,sp of the SJ-FINFET for different
drift region lengths. .......................................................................................... 102
Fig. 5.16 Specific on-resistance profile along C-C cut line during on-state for
conventional SJ SOI-LDMOS and the proposed SJ-FINFETs ........................ 104
Fig. 5.17 Mobility profile along C-C cut line during on-state for conventional SJ SOILDMOS and the proposed SJ-FINFET with Wside = 3 m. ............................. 105
Fig. 5.18 Comparison of the electric field distribution (along the C-C cut line) for the SJFINFETs with two different values of NA at ND= 7.4 1016 cm3and Wside = 2
m. ................................................................................................................... 106
Fig. 5.19 Electric field distribution comparison between the conventional SJ-LDMOS and
SJ-FINFETs at NA = 9.25 1016 cm3 and ND = 7.4 1016 cm3. ................... 107
Fig. 5.20 Performance comparison between SJ simulation results with different trench
gate depths and previously published data....................................................... 108
Fig. 6.1 Standard CMOS process flow with additional steps for the lateral SJ-FINFET
implementation. ................................................................................................. 112
Fig. 6.2 Six sequential processing steps required for the deep trench isolation region. . 113
Fig. 6.3 Process Flow of the SJ-FINFET (Part 1 of 5) ................................................... 121
xii
Fig. 6.4 Layout design rules for the proposed SJ-FINFET device on a SOI platform. .. 127
Fig. 6.5 A full test chip layout of both SJ-FINFET and SJ-LDMOS device. ................. 131
Fig. 6.6 Some of the process structures: (a) critical dimensions and (b)-(c) alignment
marks. ................................................................................................................ 131
Fig. 6.7 Micrograph of the fabricated test integrated chip (Optical: 200). .................. 132
Fig. 6.8 Top-view of SJ-FINFET device: (a) a layout and (b) a corresponding fabricated
structures. .......................................................................................................... 133
Fig. 6.9 SEM images of fabricated SJ-FINFET: (a) a transistor array and (b) a crosssection after Al and oxide etchings. .................................................................. 133
Fig. 6.10 Ids - Vgs transfer characteristic of the fabricated SJ-FINFET at Vgs = 0.1 V. .. 134
Fig. 6.11Output I-V characteristics of the fabricated (a) SJ-LDMOSFET and (b) SJFINFET devices, Ldrift = 3.5 m and Wtotal = 200 m. .................................... 135
Fig. 6.12 The specific on-resistance of the fabricated SJ-FINFETs for different n/p pillar
width ratios and SJ-drift trench (DTI) widths. ................................................. 136
Fig. 6.13 The relationship between BV and P-pillar dose for the fabricated SJ-FINFET
devices with Ldrift of 3.5 m and 6 m, Wn = Wp = 0.3 m and Wside of 2.7 m.
.......................................................................................................................... 137
Fig. 6.14 On-resistance data comparison as a function of the gate width (W) of the
fabricated SJ-FINFET and SJ-LDMOSFETS, Ldrift = 3.5 m. ........................ 138
Fig. 6.15 Ron,sp data comparison between SJ-FINFET and SJ-LDMOS for different Ldrift.
.......................................................................................................................... 139
Fig. 6.16 Micrographs of the SJ-FINFETs with different drift lengths: (a) Ldrift = 3.5 m,
(b) Ldrift = 6.0 m, (c) ) Ldrift = 10.0 m and (d) ) Ldrift = 12.0 m for Wtotal = 200
m. ................................................................................................................... 139
Fig. 6.17 Performance comparison between the fabricated SJ-devices and previously
published data. Data from [102], [104], [114] are for conventional
LDMOSFETs. Data from [103], [111-113] are for conventional SJLDMOSFETs. .................................................................................................. 140
xiii
List of Glossary
ASIC: Application Specific Integrated Circuits
ASSP: Application-Specific Standard Products
BJT: Bipolar Junction Transistor
BV: Breakdown Voltage
BOX: Buried Oxide Layer (SOI Wafer)
CAGR: Cumulative Average Growth Rate
CMOS: Complementary Metal Oxide Semiconductor
CMP: Chemical Mechanical Polishing
DMOS: Double Diffused MOS
DTI: Deep Trench Isolation
ESD: Electro-Static Discharge
FET: Field Effect Transistor
FOM: Figure of Merit
FINFET: Fin-Field Effect Transistor
GTO: Gate Turn-off Thyristor
HW: Hybrid-Waffle (Layout Style)
HS: High-Side (Output Switch)
HBM: Human Body Model (ESD)
IGBT: Insulated Gate Bipolar Transistor
ICP-RIE: Induced Coupled Plasma RIE
LDMOSFET: Lateral Double-Diffused MOSFET
LS: Low-Side (Output Switch)
xiv
xv
List of Symbols
Cgd: Gate to Drain Capacitance, or Miller Capacitance
Cgs: Gate to Source Capacitance
Ciss: Input Capacitance
Coss: Output Capacitance
Crss: Reverse Transfer Capacitance
xvi
on : Turn-On Delay
xvii
Chapter 1 Introduction
Over the last decade, there has been a growing research interest in the area of highefficient power integrated circuits (PICs) for various electronic applications. Especially
portable electronics products, such as cell phones, laptops, MP3 players, PDAs, digital
cameras, and other compact battery powered products have gained tremendous popularity
in the market place during the last few years. Power management ICs play a critical role
in these systems to offer a long battery operating time and many power-saving features at
the same time. The most important and largest device block in power management IC is
the output power stage, which can switch or regulate large amounts of power using many
parallel-connected power transistors. MOS power transistors have several advantages
over their bipolar counterparts, including a majority carrier device, simpler drive
requirements, and lower forward voltages. These advantages make MOS transistors
extremely useful power devices [1-4]. In this chapter, power device technology, market
trends, advantages/disadvantages, their current and future applications, and the objectives
of this thesis will be addressed.
1950
1st Wave
[6]
(Uncontrollable
Latching
Devices)
2nd
1970
1980
Triac
RC
Thyristor
Thyristor
2000
2010
Wave
(Controllable
Non-Latching
Devices)
1990
GTO
JFET / SIT
Bipolar Tr. Module
Bipolar
Transistor
GCT
High
Bipolar Tr. Module
[7]
LIGBT
Sub-
CMOS
LDMOSFET
(EDMOS)
3rd Wave
(MOS-Gate
Controlled
Devices &
Power ICs)
Power
MOSFET
SOILDMOSFET
[8]
V-shape gate
MOSFET
RESURF
LDMOSFET
[9]
[11]
[10]
VDMOSFET
Superjunction
VDMOSFET
Trench
VDMOSFET
[12]
IGBT
[15]
FS-IGTBT
Trench [14]
IGBT
[13]
NPT-IGBT
during the period from 2006 to 2011 [16]. The power semiconductor market is expected
to increase at a cumulative average growth rate (CAGR) of 8% per year to $15.5 billion
in 2011. Among several different power device technologies, the switching regulator,
power management ASIC/ASSP (Application-Specific Integrated Circuits or Standard
Products), and low voltage power MOSFET applications are currently contributing more
than half of total market revenue. Especially, the switching regulator and low voltage
power MOSFETs are used in almost all portable electronics and automotive components.
In recent years, with the rising output of whole systems, these two products are
developing relatively faster than the others as demonstrated in this figure.
$16B
LV
LV
LV
SWR
LV
SWR
LV
SWR
LV
SWR
SWR
SWR
Fig. 1.2 Annual estimate and forecast of worldwide power semiconductor market.
of about 500 kHz [3]. On the other hand, MOS transistors are majority carrier devices.
They do not exhibit any saturation delay, thus they can switch at speed in excess of multi
MHz [3]. Another advantage of power MOSFETs are their simple drive circuitry. The
average current through the gate drive of a typical one-amp power MOSFET is only a
few milliamps. Bipolar transistors generally require much higher drive currents due to a
low current gain ().
Power MOSFETs can also conduct large currents at very low drain-to-source
voltages. The behavior of a MOS transistor under these conditions can be derived from
the Shichman-Hodges theory for the linear region [17]. The simplified theory reveals a
linear relationship between the drain-to-source voltage and the drain current. The
transistor behaves as if it is a resistor whose value is known as the on-resistance. The onresistance can be reduced to arbitrarily small values by increasing the W/L ratio.
However, in practice, considerations such as die size, cost, metallization resistance, and
bond-wire resistance place practical limitation upon the on-resistance. In general, the
limitations are more severe in low voltage power MOSFETs (<100V) because they
require more precise circuit topologies and interconnections. Hence, there are many ongoing research projects to overcome those limitations at device design/fabrication, circuit
design, wafer, and package levels.
fuel cell vehicles. Low voltage power MOSFETs (<100V) are widely used in engine
control, vehicle dynamic control, vehicle safety, and body electronics subsystems in both
100
Thyristor
IGBT
10
Battery
control
Automation
Electronics
1
0.1
Triac
Power
Supply
Motor
Control
DC/DC converter
Lamp
Factory
Ballast Automation
Smart PIC
(BCD)
Linear IC
Bipolar
Digital IC
CMOS
HVDC
AD/DC
converter
Motor
Control
0.01
0.001
1000
Telecom
Circuits
GTO
Display
Driver
HVIC
DMOST/IGBT
10
100
1000
10000
The basic structure of MOS transistor (i.e. n-type MOSFET) is shown in Fig. 2.1,
where n+ represents heavily doped n-type silicon with low resistivity. The difference
between the source and drain is that the source n+ is shorted to the p-substrate by the
source metal. This is important for fixing the potential of the p-substrate for normal
device operation. For power device applications, the MOSFET is necessary to be off
when the voltage on the gate is zero. The turn-on of the MOSFET relies on the formation
of a conductive channel on the surface of the semiconductor, when a positive (or
negative) voltage is applied on the gate of the n-type (or p-type) MOSFET. For the n-type
MOSFET, as Vg increases, electrons gather at the interface between the oxide and silicon,
and a charged layer is formed to provide a "channel" for the current. When this
phenomenon occurs, the value of Vg is called the threshold voltage (Vth). In
semiconductor physics, the Vth is defined as the applied gate voltage required to make the
surface of the silicon strongly inverted (i.e. as n-type in terms of carrier concentration as
the p-type substrate. The threshold voltage can be written as [32]:
Qdep Qss
m s
Cox
kT N
fp ln a
q
ni
Vth 2 fp
where
Qdep 4q si fp Na
Cox
ox
Tox
(Eq.2.1)
(Eq.2.2)
(Eq.2.3)
(Eq.2.4)
The resistance from drain to source of the MOSFET is determined by the property of
the charged layer in the channel, and can be expressed as [32]:
Rch
Lg Tox
Wg ch ox (Vgs Vth )
(Eq.2.5)
where nch is the carrier mobility in the channel. The definition of Lg (gate length) and
Wg
Gate
Source
Lg
Oxide
P+
Drain
N+
N+
P-substrate or P-well
Rg
Cgd
Drain
Source
Rs
Rd
Cds
Fig. 2.2 An equivalent circuit for n-type MOSFET showing the parasitic capacitances and
resistances.
However, the nonlinearity of the parasitic capacitances and the incomplete data on
their variation over the full range of relevant voltages, make a gate circuit by
conventional methods exceedingly difficult. To overcome this problem, it has become
standard practice to specify the total gate charge, Qg that has to be supplied in order to
establish a particular drain current under given test conditions. Data sheets from most
manufacturers normally divide the Qg into that required to charge the gate-to-source
capacitance, Qgs, and that required to supply the gate-to-drain capacitance, Qgd. The merit
of the gate charge parameter is that it is relatively insensitive to the drain current and the
precise circuit conditions used, and it is quite independent of temperature [1]. It allows a
very simple design methodology for obtaining the desired switching time, and it enables
the total charge and the total energy required to be easily estimated. The resulting average
current and power needed from the gate circuit can be also obtained throughout a
multiplication of the operating frequency.
10
3-terminal devices
2-terminal devices
PiN diode Schottky diode
Power MOSFET
JFET
LDMOS
BJT
Thyristor
Vertical
Lateral
CMOS
IGBT
RESURF
UMOS
V-MOS
DMOS
Cool MOS
11
Some well known examples of vertical power MOSFETs include V-MOS (V-shaped
MOS), DMOS (Double-diffusion MOS), UMOS (U-shaped MOS), and Cool MOS
(Vertical Super-junction MOS from Infineon Technologies). The common lateral power
devices include LDMOS (Lateral Double-diffused MOS), RESURF (Reduced SURface
Field) LDMOS and CMOS power transistors. In the following sections, both traditional
vertical and lateral power MOSFETs are briefly discussed in terms of their intrinsic
structures and associated operating principles.
The name, V-MOSFET [33] is derived from the V-shaped groove along which
current flows, as shown in Fig. 2.4. Although the V-MOSFET was the first
commercialized structure of the power MOSFET, it was replaced by the Double-diffusion
MOSFET (DMOSFET) because of the drawback of high electrical field concentrated at
the tip of the V-groove. The diffusion refers to the manufacturing process: the P-well is
obtained by a diffusion process (i.e., actually a double diffusion process to get the P-body
and N+ regions, hence the name double-diffused).
Source
Source
Gate
N+
P-body
N+
P-body
Oxide
N-drift region
N+
Drain
Fig. 2.4 Structure of V-MOSFET.
12
DMOSFET
In Fig. 2.5, the cross-sectional vertical structure of the DMOSFET [33] is illustrated.
When Vg is higher than the threshold voltage and Vds is positive, the electron current of
the DMOSFET travels horizontally through the channel and then vertically down to the
drain. A more direct and shorter current path can be achieved if the channel is orientated
vertically instead of along the silicon surface. This idea is realized later by the structure
of the UMOSFET.
Gate
Source
Oxide
N+
Source
N+
P-body
P-body
N-drift region
N+
Drain
Fig. 2.5 Structure of DMOSFET.
UMOSFET
Similar to V-MOSFET, the UMOSFET is named from the U-shaped groove formed
in the gate region, as shown Fig. 2.6. In comparison with the DMOSFET structure, the
UMOSFET has no JFET effect, which is caused by the depletion of the region between
wells in the DMOSFET. The UMOSFET has higher channel density to significantly
reduce the on-resistance and also it has no sharp oxide tip (as in the V-MOSFET). This is
because that the corners of the gate oxide located in the n-drift region can be rounded by
isotropic etching. In order to prevent the catastrophic destruction of the gate oxide due to
the high electrical field at the corner of the trench, the p-body is usually designed to be
13
relatively deep. Also, the doping concentration at the bottom of the p-body is high
enough to ensure that the breakdown voltage occurs first at the junction of the p-body and
the n-drift region. As a result, the voltage can be clamped to save the gate oxide [34].
Source
N+
P-body
Oxide
Source
Gate
N+
Source
Gate
N+
P-body
N+
P-body
N-drift region
N+
Drain
Fig. 2.6 Structure of UMOSFET.
The lateral double diffused MOSFET is the predominant power device in the
implementation of PICs because of many attractive electrical characteristics such as high
input impedance, low on-resistance, high breakdown voltage and fast switching speed. A
typical LDMOSFET structure is as illustrated in Fig. 2.7. In this structure, the current
flows laterally on the surface from the source to the drain electrode and the channel
region is implemented using double implantation of the p-well and the n+ source regions
through the same opening window. One of the main advantages in the LDMOSFET is
that it can be easily integrated into a standard CMOS process. In the on-state, when a
positive voltage, higher than the threshold voltage is applied to the gate, a conductive
channel forms at the surface of the p-well and electrons flow from the n+ source through
the highly conductive channel and the n-drift layer to the n+ drain electrode. In the off-
14
state, the depletion region associated with the p-well and the n-drift region, mostly
extends through the drift region and determines the breakdown voltage of the structure.
The drift region length and resistivity should be optimized to achieve a higher BV. In
order to enhance the trade-off relationship between BV and Ron,sp, the drift region length
should be increased while its doping concentration is decreased. In the LDMOSFET, the
trade-off relationship is defined by the equation [35].
(Eq.2.6)
This equation provides that the relationship between BV and Ron,sp. It is quadratic in
nature. Hence, a higher BV can result in a significant increase in the on-resistance of the
device. Therefore, the silicon area efficiency is low and the specific on-resistance is
relatively high for those applications that require a high current handling capabilities. In
vertical power MOSFETs, the n-drift region is located inside the silicon. Hence, a current
path can be elongated without sacrificing the silicon area.
Wg
Gate
Source
Lg
Oxide
P+
Drain
N+
N-drift region
N+
P-well
P-substrate
15
In 1979, Appels and Vaes suggested the RESURF concept [36], which allows
significant improvement in the voltage blocking capability of lateral device. The cross
section of a RESURF LDMOSFET is as shown in Fig. 2.8. There are two different diodes
shown with the associated junctions such as a lateral junction at the n-drift/p-well
boundary and a vertical junction at the n-drift/p-substrate boundary. At an optimum
thickness and concentration of the n-drift layer, the depletion layer from both horizontal
and vertical n/p junctions allows the electric field at the surface to be lower than the
critical electric field. A higher breakdown occurs at the junction between the p-substrate
and n-drift layer when the electric field reaches the critical value, Ec.
Under the conditions, the thickness of the epitaxial layer, te must equal to the
depletion width, Wd in that layer as defined by the following equation [36].
Wd t e
2 s ( BV )
q( N e N s
(Eq.2.7)
where s denotes the dielectric constant of silicon, q is the electronic charge, and N e and
Ns are the doping concentration in the epitaxial layer and the substrate respectively. The
corresponding parallel plane breakdown voltage is then given by [36].
BV s
EC2
2 q (Ne N s )
(Eq.2.8)
where Ec is the critical electric field in silicon. The charge density, Ne te in the epitaxial
layer is given by [36].
Ne te s
EC
q
(Eq.2.9)
16
Ne te 1 21012 cm2
(Eq.2.10)
A well designed silicon RESURF device, satisfying the above condition, can withstand
approximately 15 V/m of drift region length.
The RESURF structure allows the optimized performance at high voltages in the offstate, because the n-drift layer is fully depleted of charge carriers and the surface field is
reduced to a value of less than the critical electric field. The surface electric field profile
is uniform and has a flat shape at the surface. In the past decades, the RESURF
technology has been successfully commercialized for many lateral power semiconductor
devices such as diodes and LDMOS transistors for 20 1200V [37]. Although the
maximum blocking voltage of the RESURF LDMOSFET is greater than the conventional
LDMOSFET, this increase is limited to a few hundred volts because the lightly doped
epitaxial drift layer causes an increase in the on-resistance of the device.
E
Es < Ec
X
Gate
N+
P-well
N+
P+
te
N-drift region
Ec
P-substrate
17
IGBT
LDMOS
VDMOS
SJ-MOS
Bi-CMOS
CMOS
HV Level Shifter
Gate Drive Circuit
Sensing &
Protection
Interface
Analog Circuits
Over Temperature
Over Current
Under Voltage
Over Voltage
Logic Circuits
CMOS LSI
Previous smart power devices have always used design rules and technologies which
are less efficient than that used for CMOS devices. In the early 80s, the first smart power
devices were fabricated with 2.5 or 4m design rules while CMOS used 1m design
rules. When CMOS devices used submicron IC design rules, smart power devices were
fabricated with 1 or 2m design rules [5]. This difference was essentially linked (i) to the
more complex fabrication that must be taken into account: isolation, edge terminations
for power devices and combination of different kinds of devices, and (ii) to the rapid
development of CMOS devices driven by larger market forces. Recently, the design rules
for smart power devices went down to 0.35-0.13m, which offers a greater possibility of
integrated CMOS-based power ICs. This strong drive towards integration leads to a
single chip system for low voltage power applications. Some manufacturers prefer a
mixed technology (e.g. Bi-CMOS); however, overall design rules do not help to reduce
the device area, because most of the chip size is determined by the on-chip power devices.
Since low voltage power MOSFETs implemented in a deep submicron CMOS process
exhibit much shorter switching delays than those in conventional power MOSFETs, this
allows the CMOS devices to operate in the MHz range for high-efficient mobile
applications. Nevertheless, one of the drawbacks is that more advanced CMOS
technology is accompanied with larger parasitic interconnect resistances and capacitances.
Without any processing and device structural changes, performance improvement can be
only gained by introducing a new layout structure. In the next section, several different
layout techniques for CMOS power device applications will be discussed in detail.
19
The multi-finger (MF) CMOS layout structure has been widely used in almost all
smart PICs. In general, MOS transistor with large device widths are needed to achieve
low channel resistance, and to maximize the operating frequency, the minimum gate or
channel length is used. To reduce the distributed gate resistance, a common layout
practice is to decompose it into many parallel transistors of smaller widths. This
conventional layout technique is known as a multi-finger distribution, as shown Fig. 2.10.
20
Gate
However, Ron does not continue to decrease as the number of parallel fingers is
increased. In fact, at some point, the interconnect resistance begins to dominate, causing
Ron to be saturated. Further increase in active area leads to higher total gate capacitance
without any Ron reduction. To minimize Ron, many different layout techniques have been
proposed and commercialized [44]. One of modified versions of MF layout [3] is
demonstrated in Fig. 2.11. Although the wider metal layers minimize the overall Ron in
this type of layout structure, there is a trade-off relationship between a number of
source/drain contacts and a width of metal layer. In addition, this layout structure has no
change in device active area; therefore the gate resistance and capacitance remain the
same as those of the conventional MF layout structure.
21
Gate
Source
Drain
Gate Poly
M-1
Contact
Metal-1
Via-1
Metal-2
Fig. 2.11 A modified version of MF layout structure with wider metal layers
Regular Waffle (RF) Layout
Source: M1 || Mtop
Gate
Source
Drain
Gate Poly
Contact
Metal-1
Drain: M1 || Mtop
Fig. 2.12 A conventional Regular Waffle (RW) layout structure
22
The RW layout uses a mesh of horizontal and vertical poly gate stripes to divide the
source/drain implant into an array of squares. Each square contains a single contact. By
alternately connecting these contacts to the source and drain metallization, one can
arrange four drains around each source and four sources around each drain [44]. The
drain and source metallization consists of a series of diagonal stripes of metal-1 and
upper parallel metal layers as shown in this figure.
An analysis of the W/L ratios achieved for a given device area shows that the waffle
layout structure provides an increase in packing density equal to [3]:
2S gate
(W / L) RW
(W / L) MF Lgate S gate
(Eq.2.11)
The RW layout offers a better packing density than the MF layout as long as the
spacing between the gates, Sgate exceeds the gate length, Lgate . Almost all power
MOSFET layout structures meet this requirement. For example, the layout rules specify a
minimum drawn gate length of 2m, a minimum contact width of 1m, and a minimum
spacing poly-to-contact of 1.5m. Using these rules, Eq.2.11 indicates that the waffle
transistor provides approximately 33% higher transconductance than the conventional
multi-finger transistor. By allowing the source/drain area to be shared by more polysilicon gates, the waffle layout minimizes the active area, leading to smaller junction
capacitance. A small parasitic capacitance has not only a beneficial effect on the speed
requirement, but also on the power consumption of the chip, which is one of the key
issues in integrated design nowadays. In addition, the characteristic (i.e. compactness) of
the waffle layout leads to the reduction of thermal noise because the gate resistance is
also decreased.
23
However, the waffle-type transistor has three crucial deficiencies. First, due to the
restriction of minimum CMOS design rules (e.g. minimum metal width and spacing) of
the first metallization level, the source/drain diffusion area should be larger than the
minimum dimension to accommodate the metal lines connecting the source/drain regions
through the contacts. The metallization invariably contributes a significant portion of the
Ron of the transistor, and in more recent CMOS process technology nodes, it often
becomes the dominant factor. If one assumes that the metallization contributes about half
the total Ron, then the improvement gained by using the waffle layout drops by half, or
from 33% to 16% for the previous example.
The situation is actually even worse, because the waffle layout is difficult to properly
route the metal layers. The metal-1 layer stripes must repeatedly cross the gate poly and
this introduces a significant step-induced metal thinning [44]. Second, the waffle
transistor contains a large number of bends in its channels. These bends produce sharp
corners in the source/drain regions that avalanche at lower voltages than the remaining
parts of the transistors. Such a localized avalanche limits the amount of energy in which
the waffle transistor can dissipate. This limitation becomes more apparent in high voltage
power applications. Third, the waffle layout structure makes no provision for backgate
contacts (e.g. p+ substrate contact or n+ contact for n-well). Unless the transistor is used
in combination with a heavily doped substrate or a buried layer to provide a substrate or
well contact, it is quite susceptible to de-biasing and latch-up issues. In Chapter 3, a new
waffle-type layout structure, named hybrid-waffle will be introduced. This new layout
strategy will provide a breakthrough to overcome those disadvantages of the conventional
waffle layout, described in this section.
24
25
Gate
Source
N+
P-body
Ld
W
tepi
N-drift
pillar
P-drift pillar
N+
Drain
BV EC Ld
N D WP N si E C
2
q
(Eq.2.12)
(Eq.2.13)
where the critical electric field, Ec is also increased by the increased doping concentration
of the pillar.
26
Because the current flows only through the n-pillar, the specific on-resistance can be
expressed as [51]:
R on,sp
Ld
W BV
PN 2
q n ND 2n si EC
(Eq.2.14)
This equation clearly shows the linear relationship between the BV and the specific onresistance of SJ-DMOSFETs instead of the power relationship for the case of
conventional power MOSFETs. To achieve the best performance in the SJ structure,
precisely charge balanced p- /n- pillars must be formed at exactly the same doping level
to have equal amount of positive and negative charges. By carefully choosing the suitable
pillar width, doping concentration and drift region depth, the SJ device can substantially
outperform over the conventional power MOSFETs, especially in the medium to high
voltage ranges.
27
28
the SEG process using chlorine source gases for filling the high aspect ratio trenches
without voids. Boron implantation was also used to reduce the leakage current and
improve the avalanche characteristics. It is noted that the SEG process step is currently
not compatible with a standard CMOS process technology. High off-state leakage current
and soft breakdown effects were observed for devices fabricated using this technique.
100
LDMOS
LDMOS-SOI
LDMOS-SJ
VDMOS
VDMOS-SJ
Si-limit
10
Low Voltage
0.1
0.01
10
100
1000
29
Source
Gate
Source
Rc
Drain
Rg
Rm1
Gate Poly
Metal-1
Contact
Drain
Fig. 3.1 A basic MOS finger layout with simple interconnect resistive components.
Several different circuit simulations have been performed by using this simple
resistance model for a better understanding of the effects of parasitic interconnect
resistances in CMOS layout structures. First, the contribution of parasitic interconnect
resistances, Rparasitic in a finger MOS layout with two different metal-1 widths has been
simulated by using TSMCs 0.25m CMOS HSPICE model (see Fig. 3.2). As the finger
length (or gate channel width) increases, both channel resistance and on-resistance
decrease initially. However, after a certain value of the finger length, the on-resistance
starts to increase gradually. This indicates that the interconnect resistance starts to
30
dominate the total on-resistance. The difference between intrinsic channel resistance and
total on-resistance corresponds to the parasitic interconnect resistance. For longer finger
lengths, this difference is even more pronounced.
(a)
Vs.
D
(b)
1000
Ron @ min. M-1 w idth
100
Ron ()
Rparasitic
Ron
10
Rchannel
Rparasitic
1
0
100
200
300
400
500
600
700
800
900
Fig. 3.2 (a) Two different MOS finger layouts with min. and max. metal-1 widths,
(b) Simulation results of Rchannel, Ron, and Rparasitic for (a).
In addition, the on-resistance models for different numbers of multi-finger layouts
have been studied and the simulation results are given in Fig. 3.3. By increasing the
numbers of MOS layout fingers, both smaller values of Ron and Ron,sp have been observed.
Theoretically, the on-resistance for the same device width is constant; however, this
different observation can be understood that higher number of MOS fingers for the
similar device size leads to the smaller parasitic interconnection resistance. This explains
31
why many layout designers do not always use the maximum finger length allowed in the
design rule. It is also interesting to note that a smaller technology node of standard
CMOS process provides the smaller on-resistance characteristics for the same device size.
Advanced CMOS technologies have more metal layers and this allows a greater reduction
in parasitic interconnect resistance.
1000
(a)
Ref [71]
[48] (0.8um)
1 finger (TSMC 0.25um)
3 fingers (TSMC 0.25um)
10 fingers (TSMC 0.25um)
1 finger
Ron ()
100
10
20 fingers
1
0
200
400
600
800
1000
1200
1400
1600
1800
2000
(b)
[71] (0.8um)
Ref[48]
35
Ron,sp (mmm2)
30
10 fingers
1 finger 3 fingers
20 fingers
10
5
0
0
200
400
600
800
1000
1200
1400
1600
1800
2000
Fig. 3.3 (a) Ron and (b) Ron,sp vs. Wtotal for different numbers of MOS fingers.
32
Source: M1
Gate
Source
Drain
Gate Poly
Contact
Metal-1
Source: M1
Gate: Poly
Drain: M1
Si-Sub
JDRAIN
JSOURCE
33
TSMCs 0.25m standard CMOS process provides two different types of transistors;
(a) 2.5V logic thin gate oxide MOSFETs and (b) 5V high-voltage I/O thick gate oxide
MOSFETs. Two important differences between transistors (a) and (b) are the breakdown
voltage (BV) and the minimum channel length, Lgate of the MOSFET. Since our target
specifications require an actual 7V-BV, the 5V thick gate oxide MOSFET was only
option for the final DC-DC converter output stage design. It is noted that the minimum
drawn channel length of the thick gate oxide transistor is 0.5m, which is the twice as
long as the minimum channel length of the 2.5V logic transistor in TSMCs 0.25m
standard CMOS process. By carefully examining the given minimum design rules of the
thick gate oxide transistors, a MF layout structure with 10 gate fingers was first
constructed and then a corresponding model with various resistive components was
developed as demonstrated in Fig. 3.5 and Fig. 3.6, respectively.
The calculation methods for these resistors are quite straight forward since there are
only two different directions of current flowing; lateral and vertical. For the vertical
direction, the corresponding resistive component can be estimated by contact/via
resistances. By adding more number of contacts (or vias) in parallel, the vertical
resistance between top and bottom layers can be simplified as: Rvertical = (Rcontact for a
contact) / (# of contacts). For the lateral direction, the corresponding resistance is mainly
from a metal layer. Since the sheet resistance of each metal layer is provided from the
foundry technology file, the lateral resistance on each metal layer can be simplified as:
Rlateral = Rsheet (Lmetal/Wmetal). Based on these two simple calculation methods, each
interconnect resistor denoted in Fig. 3.6 was extracted for the model. More detailed
information on all these calculations can be found in Appendix-I.
34
Source
Gate
Source
Drain
Spoly
S
Sad
Gate Poly
Metal-1
Metal-2
Lg
SM1
Scp
Sc
Scd
Contact
Wc
W
c
Via-1
Lex
N+ S/D
WM1
Wv1
WM2
Drain
Fig. 3.5 A MF NMOS layout (10 MOS fingers) structure with minimum design rules.
Cadence Schematic
RM2-M5_out
(gate)
RV1
RM1_gate
Rc
Rc
Rm1
RG_out
RM1
RM2-M5_out
(Source)
RV1
RG
RM1c_out
RM2
Rg
RM1
RV1
RM1c
RM1c
RM2-M5_out
(Drain)
RM1c_out
RM2
RM1c
RM1c
RM1
RM1
35
W
(m)
0.74
0.74
0.74
0.74
0.74
0.74
0.50
0.50
0.50
0.50
0.50
0.50
133
562
3626
14652
58904
132756
0.0002
0.0006
0.0039
0.0155
0.0618
0.1388
1.24
1.24
1.24
1.24
1.24
1.24
10
20
50
100
200
300
10
20
500
100
200
300
Notes
Unit-cell Pitch = W + 2(L/2) = W + L = W + 0.5m = 1.24m
Wtotal = W (Total # of MOS Fingers) = W 2[(# of Unit-cells in x-/y-axis)2 (# of Unit-cells in y-axis)]
Die Size = [(Unit-cell Pitch) (# of Unit-cell in x-/y-axis) + 0.5]2 (0.001)2
36
(a)
Scp
W
Wc,v1-v4
Unit-cell
Sc-c
WM1-M5
Rroute
(b)
Source
4Rc
Rout
4Rv1-4
Rroute
Drain
Rout
Rroute
RM1 || M5
Fig. 3.7 Schematic of (a) 4 4 regular waffle layout and (b) the corresponding resistance
model.
37
W
(m)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
900
2100
3800
6000
8700
11900
15600
19800
24500
29700
35400
0.0049
0.0108
0.0191
0.0297
0.0426
0.0578
0.0754
0.0953
0.1175
0.1421
0.1689
6.82
6.82
6.82
6.82
6.82
6.82
6.82
6.82
6.82
6.82
6.82
10
15
20
25
30
35
40
45
50
55
60
10
15
20
25
30
35
40
45
50
55
60
Notes
Unit-cell Pitch = W + 2(0.22) + 2(0.14) + 2(0.3) + 0.5 = 6.82m
Wtotal = W (Total # of MOS Fingers) = W 2[(# of Unit-cells in x-/y-axis)2 (# of Unit-cells in y-axis)]
Die Size = [(Unit-cell Pitch) (# of Unit-cell in x-/y-axis) + 0.5 + 2(0.22) + 2(0.3) + 2(0.14)]2 (0.001)2
38
(a)
Ld
Lex
SC
Lg
LM3
WM3
SM3
W
(b)
Rc
Rroute
Rx1
S
Rout
RM1-CtV
Rroute
RM3 || M5
Fig. 3.8 Hybrid waffle structure: (a) a layout and (b) a corresponding resistance model.
39
2400
0.24
Ron: PMOS
Qg: PMOS
2000
0.2
1600
0.16
1200
0.12
800
0.08
400
0.04
QG (nC)
RON (m)
Ron: NMOS
Qg: NMOS
0
0
10
20
30
40
50
60
70
80
Lfinger (m)
Fig. 3.9 Simulated Ron and Qg data for different Lfinger values of HW layouts.
40
80
24
FOM-1: PMOS
FOM-2: PMOS
70
21
60
18
50
15
40
12
30
20
10
0
0
10
20
30
40
50
60
70
FOM-2 (nCmmm2)
FOM-1 (nCm)
FOM-1: NMOS
FOM-2: NMOS
80
Lfinger (m)
Fig. 3.10 FOM-1 & FOM-2 versus different Lfinger of HW layout structures.
In Fig. 3.10, two different FOMs: FOM-1= Ron x Qg, FOM-2= Ron,sp x Qg, (Ron,sp =
Ron Area) are represented. Both NMOS and PMOS have the minimum FOM value
when Lfinger is close to 5 ~ 12 m. Although a small FOM value of the power MOSFET
generally leads to higher power efficiency, however it is suspected that this may not be a
good performance indicator for a low voltage CMOS technology since low voltage
CMOS processes have a much smaller total gate charge, Qg value. Hence, the optimum
Lfinger is more accurately verified from the power efficiency versus Lfinger plot for a
constant load current. The efficiency simulation results of both SPICE and MATLAB
give an optimal Lfinger of approximately 5 m. It is noted that all DC-DC converter
efficiency simulation and gate drive/controller design works for the final output stage
were done by Marian Chang [74], a MASc student whom I worked together for the same
research project from ON-Semiconductor Corp.
41
Si5920DC
Si1450DH
Si8424DB
SiA414DJ
Si1050X
Si8404DB
8
5
0.032
7.3
3
0.8
4
234
[75]
8
5
0.047
4.24
3.6
0.8
4
199
[76]
8
5
0.031
20
88
0.6
12.2
620
[77]
8
5
0.011
19
20
0.8
12
209
[78]
8
5
0.086
7.1
3.7
0.8
1.34
611
[79]
8
5
0.031
20
88
0.6
12.2
620
[80]
MGSF1N02LT1
MMBF0201NLT1
NTA4153N
NTK3134N
20
12
0.115
3
5
0.8
1
345
[81]
20
12
1
1.4
5
0.85
0.3
1400
[82]
20
6
0.127
1.82
3
0.67
0.6
230
[83]
20
6
0.2
1.16
3
0.75
0.89
232
[84]
42
95
Trench MOS
LDMOS
Efficiency (%)
90
@ fs = 1 MHz
85
@ fs = 800 kHz
80
75
70
0
300
600
900
1200
1500
FOM (nCm)
Fig. 3.11 FOM vs. Efficiency for conventional power MOSFETs.
43
A similar analysis of efficiency vs. conventional FOM was performed for CMOSbased power MOSFETs with different total gate widths implemented in Cadence
Virtuoso. Both Ron and Qg were extracted through HSPICE simulation and the detailed
simulation conditions are summarized in Appendix-II. The extracted values for different
NMOSFETs are listed in Table 3.6. For a comparison with efficiency, the conventional
FOM was first calculated for each NMOSFET. The efficiency simulation of these
converters was performed with test conditions summarized in Table 3.7. The simulation
results of power conversion efficiency are plotted in Fig. 3.12 with respect to the
conventional FOM.
#1
8.7
#2
11.9
#3
15.6
#4
19.8
#5
24.5
#6
29.7
165
0.086
149
0.106
147
0.129
14.16
15.82
18.92
7
5.5
330
0.038
245
0.052
195
0.068
1
0.6
0.4
12.44
12.63
13.18
Simulator values
3.3V
3.3V
0.8V
0.4 A
5 MHz, 10MHz, and 15MHz
In contrast to the simulated result in Fig. 3.11, the conventional FOM was found to be
clearly not a good performance indicator for CMOS-based power MOSFETs. The lower
FOM value no longer guarantees a higher efficiency or better design performance. This
observation can be understood through the difference in device structure. As illustrated in
Fig. 3.13, standard CMOS inherently has a much smaller overlap area between its polysilicon gate electrode and the source/drain diffusion area than the conventional power
MOSFETs. Therefore, CMOS-based power MOSFETs have a smaller Qg, and a different
44
power loss distribution from that of conventional power MOSFETs. Due to the difference
in power loss distribution, Ron and Qg no longer has comparative contribution to the
overall power loss. A new FOM was therefore required to characterize the performance
of CMOS-based power MOSFETs.
95
Standard CMOS @ 5 MHz
Standard CMOS @ 10 MHz
Standard CMOS @ 15 MHz
Efficiency (%)
90
85
80
75
70
10
13
16
19
22
25
FOM (nCm)
Fig. 3.12 Efficiency vs. Conventional FOM for CMOS-based Power MOSFETs.
G
n+
Cgs
p+
Cgs
G
Cgd
G
Cgd
p-sub
n+
n-
p+
nCgs
n+
Cgd
p-sub
n+
D
Fig. 3.13 Cross-sectional views of Trench-gate, LDMOS, and CMOS power MOSFETs.
45
From the literature review in [85], Colino and Schultz proposed a new FOM method
using different weighting factors for each FOM element which depends on a specific
topology and circuit conditions. However, they have not specified on how these
weighting factors can be chosen. In this section, a systematic approach is developed by
analyzing the major loss mechanisms in a synchronous buck converter to determine these
weighting factors.
For different DC-DC converter topologies, various power loss equations can be used
to determine the weighting factors of the new FOM. Although the weights of the
conduction loss and gate-drive loss for CMOS-based power MOSFETs are different from
those for conventional power MOSFETs, they are still two the major power loss
contributing factors [86]. Hence, Ron and Qg are also two important key parameters to be
considered for characterization. The new FOM equation can be defined as:
FOMNew A RON B Qg
(Eq.3.1)
where A and B are the weighting factors. To determine the values of these weighting
factors, the equation for conduction and gate-drive loss are stated [2]:
Pcond is proportional to the square of output load current. By assuming that the HS and
LS switches have similar Ron as they are generally designed to be for CMOS power
MOSFETs, the constant A in Eq.3.1 is the square of the typical output load current. The
assumption of similar Ron for both the HS and LS switches is quite reasonable when the
duty cycle is not always much above or much below 50%. To further illustrate the design
46
decision, one can consider an application where Vout varies from 1.8 to 3.3V when Vin is
held at 5.5V. In this case, the duty cycle varies from 36% to 66%, thus the conduction
time for both the HS and LS switches would be comparable over the operating range.
This indicates that their on-resistances should also be designed to have comparable values.
When choosing an appropriate power MOSFET for a specific application, the designers
are usually aware of the operating switching frequency (fs) and the supply voltage level
(Vin). Hence, these two parameters can be used to calculate the weighting factor of Qg. In
order to account for the total Qg from both the HS and LS switches when only the Qg of
the LS switch is known, it is necessary to note that Qg of a PMOS is about three times
larger than that of an NMOS. Since the effective mass of a hole is much larger than that
of an electron, this results in a lower mobility for hole. By considering this fact, the
PMOS switch should be approximately three times larger than the NMOS to achieve
similar Ron. Therefore, the total Qg would be approximately four times of Qg (LS). This can
be reflected by defining the constant B in Eq.3.2.
B 4 f S Vin
(Eq.3.2)
Nevertheless, if Qg for the PMOS is known, it can be included as the total Qg, and the
constant B will not require a scaling factor of 4. Simultaneously, SPICE simulation for
Qg extraction may not produce an accurate value of Qg when the size of PMOS is too
large. When only Qg of NMOS is extracted, the new FOM equation can be defined as:
(Eq.3.3)
To confirm the validity of the proposed FOM, the efficiency (as plotted in Fig. 3.12)
vs. the new FOM for the CMOS-based power MOSFETs is re-plotted in Fig. 3.14. In
contrast to the traditional FOM, the new FOM data trend represents the corresponding
power conversion efficiency more accurately [87]. This can be explained by the fact that
the new FOM reflects the conduction and switching power losses more effectively as it
has a unit in watt. Therefore, this new FOM developed for low voltage CMOS transistors
is a more accurate indicator of the overall device performance.
47
90
Std CMOS @ 5 MHz
88
Efficiency (%)
86
84
82
80
78
76
74
0.03
0.04
0.05
0.06
0.07
FOMNEW (W)
Fig. 3.14 Efficiency vs. New FOM for CMOS-based Power MOSFETs.
48
value, the Miller capacitance is fully discharged, the gate voltage will continue to rise
(point C). Since the time to discharge this parasitic capacitance is mainly depending on
the magnitude of Cgd, it is required to minimize the Qgd. However, the change in Ids
affects Qgs rather than Qgd. Nevertheless the total gate charge of HW structure was
approximately 3.6 times smaller than that for the MF structure at Vg = 3.3V. This is due
to the fact that the total W for the MF structure is more than 3 times wider than the HW
structure for the same chip area, thus smaller Qgd.
3.5
(a)
Vds
0.8
Vg
2.1
0.6
MF
I ds
1.4
0.4
@ Vg = 3.3V
0.7
Current (A)
Voltage (V)
2.8
0.2
0
0
40
80
120
160
200
240
(b)
Vds
0.8
HW
Voltage (V)
Vg
2.1
0.6
I ds
1.4
0.4
Current (A)
2.8
@ Vg = 3.3V
A
0.7
0.2
0
0
20
40
60
80
Fig. 3.15 Gate charge characteristics of (a) MF and (b) HW layout structures
: @ Ids=800mA, : @ Ids=400mA, : @ Ids=80mA.
49
Fig. 3.16 illustrates the Ron and Qg trends for the MF, RW and HW layout structures
as a function of power MOSFET active area. Unfortunately, both Ron and Qg plots for
RW layout structure were incomplete for the full range of device size. Since the larger
RW device contains too many transistor cells and resistive components, the simulation
was terminated after 40-50 hours of operation. It is interesting to note that Ron trends for
MF and HW structures cross over at Area = 0.066 mm2. This indicates that with a large
enough device area, the HW structure can minimize and achieve smaller overall Ron
although the W/L ratio of HW structure is smaller than that of the MFs and RWs. Since
small values of both Ron and Qg for a power MOSFET are always preferred to minimize
the overall power loss, HW structure is expected to have higher power conversion
efficiency than the other two layout strategies.
0.6
0.54
QG (MF)
0.5
0.45
RON (HW)
0.36
QG (RW)
0.3
0.27
RON (RW)
RON (MF)
0.2
0.1
0
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
QG(nC)
RON (Ohm)
0.4
0.18
QG (HW)
0.1
0.09
0.00
0.11 0.12 0.13
Area (mm2)
Fig. 3.16 RON and QG plots as a function of MF, RF and HW layout active areas.
For verification purpose, the power conversion efficiency was simulated as a function
of its operating switching frequency as shown in Fig. 3.17. As expected, the MF structure
provided a better power conversion efficiency at low switching operations where
conduction loss dominates. However, as the frequency increased to several MHz, there
50
was a cross-over point between MF and HW plots. This indicates that the HW structure is
a better layout scheme for power MOSFETs operating in the multi-MHz range. Also, the
HW structure provides higher efficiency at light load current because the switching and
gate drive losses (which are directly proportional to Qg) dominate over conduction loss.
100
(a)
Iload = 800mA
HW
MF
Efficiency (%)
80
60
40
(b)
10
Frequency
(MHz)
I
= 400mA
load
100
HW
MF
Efficiency (%)
80
60
40
10
100
100
(c)
8
Iload = 80mA
HW
MF
Efficiency (%)
80
60
40
10
Frequency (MHz)
100
Fig. 3.17 Comparison of power conversion efficiencies for both MF and HW layout
structures as a function of switching frequency and for different load currents:
(a) 800mA, (b) 400mA, and (c) 80mA.
51
Table 3.8 Simulation Data Summary of MF, RW, and HW Layout Structures
NMOS @ Vin=3.3V, Vdd=3.3V, Id=400mA
MultiFingers
(MF)
Regular
Waffle
(RW)
Hybrid
Waffle
(HW)
L
(m)
Wtotal
(m)
Area
(mm2)
Ton
(ps)
Toff
(ps)
RON
(m)
QG
(nC)
FOM
(nCm)
0.50
20172
0.0295
15.5
214.9
352
0.099
34.80
0.50
36388
0.0523
25.7
472.8
237
0.190
44.96
0.50
54582
0.0788
38.4
914.2
206
0.306
63.00
0.50
71354
0.0985
68.9
1452.2
199
0.393
78.16
0.50
86520
0.1175
118.1 2370.3
194
0.504
97.71
0.50
27981
0.0295
18.6
305.2
332
0.137
45.48
0.50
49835
0.0523
37.1
882.7
231
0.260
60.06
0.50
58904
0.0618
N/A
N/A
219
0.324
70.96
0.50
6000
0.0297
9.8
108.5
493
0.030
14.78
0.50
8700
0.0426
17.8
168.5
330
0.044
14.50
0.50
11900
0.0578
30.2
261.4
245
0.061
15.01
0.50
15600
0.0754
41.1
325.6
195
0.083
16.12
0.50
19800
0.0953
53.6
437.9
165
0.109
17.97
0.50
24500
0.1175
68.4
554.2
149
0.141
20.99
52
3.5 Summary
This chapter presented the simulation-based research on a low-voltage CMOS power
transistor layout technique, implemented in a 0.25m standard CMOS technology that is
suitable for high speed switching power devices. The proposed hybrid waffle (HW)
layout technique organizes MOSFET fingers in a square grid arrangement. It was
designed to provide an effective trade-off between the width of diagonal source/drain
metal and the active device area, allowing more effective optimization between switching
and conduction losses. In comparison with conventional multi-finger (MF) layout
geometries, the HW layout structure for the power MOSFET was found to exhibit
approximately 30% reduction in overall on-resistance with 3.6 times smaller total gate
charge for CMOS devices with a current rating of 1A. Moreover, it was found that the
conventional FOM was no longer a suitable indicator of overall device performance,
especially for the low voltage CMOS power transistors. Therefore, a new FOM was
proposed to model specifically the power loss distribution for the CMOS output-stages.
By adding two different weighting factors for both conduction and switching losses, the
new FOM could reflect the overall device performance more accurately. Lastly, the
integrated output-stage using the HW structure could achieve higher simulated power
conversion efficiencies at switching frequencies beyond multi-MHz. This performance
gain was obtained without additional processing step or changes in a device structure, and
will be very attractive for next generation low voltage integrated power converters.
53
2.5 to 5.5
800
1.2
Typical: 10
Max: 12
210
120
-0.3
6
6
-40 to 85
-55 to 150
-40 to 125
2.0
400
54
VDD
VDD
GND
PMOS
SW
PMOS
NMOS
NMOS
SW
GND
(b)
(a)
Fig. 4.1 Power MOSFET Output Stage: (a) Layout and (b) Schematic
Table 4.2 Summary of 5V power MOSFETs with Hybrid Waffle Layout Structure
W
(m)
L
(m)
NMOS
5.0
0.5
PMOS
4.2
0.5
Size
(mm2)
234 x 438
= 0.1024
501 x 435
= 0.2183
WTotal
(m)
Total # of
finger TRs
RON (m)
@ Ids=400mA
(Simulated)
QG (nC)
@ VG=3.3V
(Simulated)
21270
4443
148.0
0.113
49547
12100
214.6
0.303
Since the maximum allowable chip size was given as 1.68 mm2, several different
layout floor plans have been proposed and reviewed. In order to achieve the Ron target
specifications (see Table 4.1), a larger die size was required based on the simulation
results of the HW schematic models. However, the on-resistance close to the target
specification was possible to obtain throughout the optimization of Wtotal ratio between
55
NMOS and PMOS. Instead of using the optimal finger length of 5m, the PMOS was
constructed with a finger length of 4.2m. Although the size of PMOS was only twice
times larger than NMOS, this provided about 40% higher Wtotal than that of NMOS array.
Also, all ESD protection diodes were embedded underneath the I/O pads to save more
space in the given die size. In the following sub-sections, more detailed design
information on each power MOSFETs, power connection routings, ESD protection
diodes, power clamps, I/O pads, seal and guard rings will be briefly discussed.
Gate:M2
Gate:M2
PTAP
M1
M2
(b)
(c)
L = 0.5M
(a)
M3 || M4
M3
M3
M3 || M4
M3 || M4
M3
(d)
M3 || M5
M3 || M5
M3 || M5
(e)
(f)
Fig. 4.2 HW_NMOS unit-cell: (a) Active, (b) M1, (c) M2, (d) M3, (e) M4, and (f) M5.
56
The wider metal layers (e.g. M3 to M5 in parallel) were also implemented without
any design rule violations (i.e. DRC-clean layout). This is especially crucial for large
devices where the metal resistance is comparable to the channel resistance as previously
discussed in the section 3.1. Fig. 4.3 presents the corresponding schematic model of the
HW_NMOS unit-cell without any parasitic components.
Drain
Drain
Source
Source
Source
Drain
Drain
(a)
(b)
Fig. 4.3 HW_NMOS unit-cell: (a) Layout and (b) Schematic (w/o parasitics)
In Fig. 4.4, the full NMOS array is sub-divided into seven segments for power
efficiency optimization. This also provides an opportunity to analyze the influence of
parasitic components on the overall device performance since the size of the power
MOSFET (W/L ratio) can be changed. Also, a metal-2 layer is designed exclusively to
connect the entire poly-gate electrodes. This helps to avoid any cross-links with other
metal layers and further reduces the distributed gate resistance for a faster switching
operation. It is interesting to note that each NMOS segment contains a total 644
transistors in parallel but the last segment (i.e., Gate_N<6>) contains only 579 transistors.
This can be explained by the asymmetry of poly-gate distribution as illustrated in Fig. 4.5.
For instance, each segment contains five vertical sub-gate columns; however, the first
sub-column of Gate_N<6> segment in Fig. 4.5(a) has a different poly-gate distribution
from the others. Although the last segment contains 10% less transistors, there is only 1%
57
difference in the total number of transistors when all segments are being used, thus the
effect is assumed to be negligible.
M2
SW
Gate_N<6>
NM6<0:579>
Gate_N<5>
NM5<0:644>
Gate_N<4>
Gate_N<0>
Gate_N<1>
Gate_N<2>
Gate_N<3>
Gate_N<4>
Gate_N<5>
Gate_N<6>
NM4<0:644>
Gate_N<3>
NM3<0:644>
Gate_N<2>
NM2<0:644>
Gate_N<1>
NM1<0:644>
Gate_N<0>
NM0<0:644>
(a)
GND
(b)
Fig. 4.4 Gate Segmentations of NMOS array: (a) layout and (b) schematic.
Gate_N<6>
Gate_N<5>
Gate_N<0>
Gate_N<1>
More transistors
(a)
(b)
Fig. 4.5 Layout comparison between segments: (a) Gate_N<6> and (b) Gate_N<0>.
58
Gate:M2
Gate:M2
NTAP
M1
M2
N-Well
L= 0.5M
(a)
(b)
M3
(c)
M3 || M5
M3 || M4
M3 || M4
M3
M3 || M4
M3
(d)
M3 || M5
(e)
M3 || M5
(f)
Fig. 4.6 HW_PMOS unit-cell: (a) Active, (b) M1, (c) M2, (d) M3, (e) M4, and (f) M5
As illustrated in Fig. 4.7, the full PMOS array is also divided into seven segments to
analyze the overall device performance for different size of power MOSFETs. Again, a
metal-2 layer is used exclusively to connect the entire poly-gate electrodes. This further
reduces the distributed gate resistance and allows a faster switching operation. Each
59
PMOS segment contains a total 1739 transistors in parallel except that the last segment
(i.e. Gate_N<6>) contains only 1666 transistors. This asymmetry of poly-gate
distribution is illustrated in Fig. 4.8. Although the last segment contains 4% less
transistors, there is only 0.5% difference in the total number of transistors when all
segments are being used, thus the effect is negligible.
VDD
M2
PM0<0:1739>
Gate_P<0>
PM1<0:1739>
Gate_P<1>
Gate_P<6>
Gate_P<5>
Gate_P<4>
Gate_P<3>
Gate_P<2>
Gate_P<1>
Gate_P<0>
PM2<0:1739>
Gate_P<2>
PM3<0:1739>
Gate_P<3>
PM4<0:1739>
Gate_P<4>
PM5<0:1739>
Gate_P<5>
PM6<0:1666>
Gate_P<6>
(a)
(b)
Fig. 4.7 Gate Segmentations of PMOS array: (a) layout and (b) schematic.
Gate_N<0>
Gate_P<6>
More transistors
(a)
(b)
Fig. 4.8 Layout comparison between segments: (a) Gate_P<0> and (b) Gate_P<6>.
60
Gate-Driver (M1-M3)
PMOS
SW (M1-M3)
GND
(M4-M5)
NMOS
GND (M1-M5)
VDD (M1~M5)
GND (M1-M3)
VDD (M1-M3)
NMOS
PMOS
VDD (M4~M5)
SW (M1-M5)
(a)
(b)
Fig. 4.9 Power Connection Routing Layouts: (a) M1-M3 and (b) M4-M5 layers.
Metal-2/4 Vertical Slots
(i)
(ii)
(iv)
(iii)
(a)
VDD
VDD
In: SP
Out: EN
In: EN
Out: SP
GND
GND
VDD
pad_io_100x100
Out: DPWM_N
In: DPWM_N
Out: DPWM_P
In: DPWM_P
VDD
GND
GND
VDD
VDD
pad_o_100x100
Out: PT
In: CLK
GND
VDD
GND
resistor_172k
esd_nclamp5v_500p4U
GND
(b)
Fig. 4.11 2kV HBM and 400 MM ESD protection circuit, (a) layout (b) schematic.
62
GND
M2
VDD GND
M1/M3/M4
VDD
GND
M2
No Resistor
(c)
Resistor
(a)
VDD
pad_io_100100
VDD
pad_o_100100
Output
Output
GND
GND
(b)
VDD
OUTPUT PAD: M5
100m x 100m
INPUT PAD: M5
100m x 100m
Input
VDD GND
M1/M3/M4
(d)
Fig. 4.12 ESD Protection Circuit Under Input Pad: (a) layout and (b) schematic.
ESD Protection Circuit Under Output Pad: (c) layout and (d) schematic.
63
In order to satisfy 2kV HBM and 400 MM ESD requirements, eight power clamps
(i.e., esd_nclamp5v_500p4U) are added between VDD and GND. Power clamps are
designed as a MOS-based structure to introduce a RC delay to the input node and they
have a total width of 4000 m (8 500 m), as shown in Fig. 4.13. An extra resistor is
required for this protection circuit. Poly-resistor with R = 172 k is connected between
vsup and rvsup terminals. To minimize the die size, the p-type high resistance polyresistor (i.e. rphripoly) is used in a snake pattern, as illustrated in Fig. 4.14. Also, many
PTAPs (i.e., p+ substrate contacts) are added on the substrate to prevent the possible
latch-up event.
rvsup
GND
rvsup
vsup
Ctotal = 1.875 pF
vsup: M1/M3/M4
rvsup: M1
gnd: M5
GND
GND
vsup
vsup
(a)
vsup
Wtotal = 500 m
vsup
(b)
Fig. 4.13 Power Clamp, esd_nclamp5v_ 500p4U, (a) layout and (b) schematic.
64
vsup
p-type polysilicon
rvsup
GND
vsup
rvsup
(b)
(a)
Fig. 4.14 p-type high resistance poly-resistor, rphripoly, (a) layout and (b) schematic.
Seal and Guard Rings
For physical stress damage and additional latch-up preventions, seal and guard rings
are employed, respectively. For instance, the seal ring is essentially a huge substrate
contact around the outside of each chip. It is basically a chunk of metal. All metal layers
in the process are stacked on top of each other, in order to keep any cracks that occur at
the edge of the die from working their way into the circuitry inside. Also, to prevent the
latch-up, a guard ring is used to surround the die (i.e., p+ in p-well and n+ in n-well).
Both seal and guard rings used in the output stage are shown in Fig. 4.15.
Seal Ring
Guard Ring
1442 m
ESD Protection
CLK
PDRV
EN
NDRV
PT
S/P
PMOS Gate-Driver
NMOS Gate-Driver
PMOS
GND
NMOS
1060 m
Logic Controller
VDD
GND
VDD
SW
SW
Fig. 4.16 A micrograph of an integrated output stage using Hybrid Waffle layout in
TSMC 0.25m standard CMOS technology.
66
Source
(VDD)
Drain
(SW)
67
S/P
VIN
VIN
S/P
PDRV
PDRV
SW
CLK
SW
CLK
EN
EN
GND
GND
PT
PT
NDRV
NDRV
(a)
(b)
68
Lf
(Vin Vout) D
2 iL f S
(Eq.4.1)
Cf
iL
8 vC f S
(Eq.4.2)
To control the output stage, an Altera Cyclone III FPGA development kit is used. The
controller code programmed into Cyclone III is scripted by Marian Chang. The
programmable electronic load, HP6051A, is connected to the output of the L-C filter as a
load for the output stage with current ranging from 10 to 800 mA. Standard lab
equipments are employed for power supply, and measurements of voltage and current.
Output
Filter
LDOs
ADC
Output Stage
Connectors to FPGA
Transceivers
(a)
(b)
Fig. 4.20 Test PCB: (a) layout (silkscreen-view) and (b) photograph.
69
R ON(LS)
Vsw
Vsw
(Eq.4.3)
R ON(HS)
I ds
Vsw /R ext
(Eq.4.4)
For PMOS,
From these two equations, several Ron measurements for different number of each
PMOS and NMOS segments are calculated and the data are summarized in Table 4.4.
VSUP
VIN
Off
On
REXT
VSW
On
VGND
(a)
+ VX
-
VSW
Off
REXT
VGND
(b)
Fig. 4.21 Test circuits for on-resistance measurements: (a) NMOS and (b) PMOS
70
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
NMOS: QFN-12
PMOS: QFN-12
# of Segment = 1
# of Segment = 1
2.5
19.25
0.098
1.999
0.111
0
1.134
4.85
3.3
19.25
0.099
1.998
0.086
0
0.870
4.38
5.0
19.25
0.100
1.998
0.066
0
0.662
3.91
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
# of Segment = 2
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
2.5
19.25
0.101
1.998
0.060
0
0.601
2.57
3.3
19.25
0.101
1.998
0.048
0
0.476
2.40
2.5
19.25
0.102
1.998
0.043
0
0.424
1.82
3.3
19.25
0.102
1.998
0.034
0
0.336
1.69
5.0
19.25
0.102
1.998
0.038
0
0.374
2.21
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
2.5
19.25
0.102
1.998
0.035
0
0.344
1.47
3.3
19.25
0.102
1.998
0.029
0
0.282
1.42
5.0
19.25
0.226
4.614
4.348
0
1.178
4.51
2.5
19.25
0.129
2.611
2.483
0
0.992
2.76
3.3
19.25
0.155
3.108
2.977
0
0.847
2.74
5.0
19.25
0.231
4.601
4.445
0
0.676
2.59
# of Segment = 3
5.0
19.25
0.102
1.998
0.028
0
0.275
1.62
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
# of Segment = 4
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
3.3
19.25
0.152
3.164
2.920
0
1.609
5.21
# of Segment = 2
# of Segment = 3
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
2.5
19.25
0.126
2.667
2.427
0
1.904
5.29
2.5
19.25
0.133
2.641
2.551
0
0.679
1.89
3.3
19.25
0.158
3.138
3.047
0
0.575
1.86
5.0
19.25
0.230
4.530
4.428
0
0.443
1.70
# of Segment = 4
5.0
19.25
0.103
1.998
0.024
0
0.230
1.36
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
2.5
19.25
0.133
2.630
2.558
0
0.542
1.51
3.3
19.25
0.159
3.124
3.054
0
0.441
1.43
5.0
19.25
0.235
4.615
4.531
0
0.357
1.37
71
# of Segment = 5
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
2.5
19.25
0.102
1.998
0.031
0
0.299
1.28
3.3
19.25
0.102
1.998
0.026
0
0.249
1.25
# of Segment = 5
5.0
19.25
0.103
1.998
0.021
0
0.207
1.23
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
# of Segment = 6
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
2.5
19.25
0.102
1.998
0.027
0
0.264
1.13
3.3
19.25
0.103
1.998
0.023
0
0.223
1.12
2.5
19.25
0.103
1.999
0.024
0
0.234
1.00
3.3
19.25
0.103
1.999
0.020
0
0.199
1.00
3.3
19.25
0.161
3.170
3.107
0
0.390
1.26
5.0
19.25
0.235
4.603
4.530
0
0.310
1.19
# of Segment = 6
5.0
19.25
0.103
1.998
0.019
0
0.188
1.11
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
# of Segment = 7
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
2.5
19.25
0.131
2.576
2.515
0
0.467
1.30
2.5
19.25
0.128
2.521
2.468
0
0.415
1.15
3.3
19.25
0.162
3.167
3.111
0
0.347
1.12
5.0
19.25
0.228
4.461
4.397
0
0.280
1.07
# of Segment = 7
5.0
19.25
0.103
1.999
0.017
0
0.169
1.00
VIN (V)
REXT ()
IDS (A)
VX (V)
VSW (V)
VGND (V)
RON ()
Ratio
2.5
19.25
0.128
2.518
2.472
0
0.360
1.00
3.3
19.25
0.162
3.168
3.118
0
0.309
1.00
5.0
19.25
0.234
4.558
4.497
0
0.261
1.00
The Ron measurements for three different voltage ratings are plotted in Fig. 4.22. The
overall on-resistance for each NMOS and PMOS is found to be decreased as the number
of segments in the output stage is increased. Since the higher number of segments refers
to the higher number of HW unit cells or the larger power MOSFET area, these results
confirm the functionality of the on-chip segmentation control logics.
72
2
NMOS, VDD = 5.0V
1.8
1.6
RON ()
1.4
1.2
1
0.8
0.6
0.4
0.2
0
1
# of Segments
Table 4.5 summarized both the simulated and measured on-resistance data. The
difference between the simulations and measurements is found to be less than 10%.
Without the package resistance consideration, the difference will be slightly higher. It is
noted that all simulated on-resistance data shown in Table 4.5 includes the 20m
additional source/drain package resistance to the HW schematic models.
73
2.4
(a)
2.2
1.8
RON ()
1.6
1.4
1.2
>90% Accuracy
1
0.8
0.6
0.4
0.2
0
1
# of Segments
2
NMOS, VDD = 3.3V (Measurement)
(b)
1.8
1.6
RON ()
1.4
1.2
>93% Accuracy
1
0.8
0.6
0.4
0.2
0
1
# of Segments
1.4
(c)
1.2
RON ()
1
0.8
>92% Accuracy
0.6
0.4
0.2
0
1
# of Segments
# of Segments
Meas.
(V)
Sim.
(V)
Error
(%)
Meas.
(V)
Sim.
(V)
Error
(%)
Meas.
(V)
Sim.
(V)
Error
(%)
1
2
3
4
5
6
7
1.134
0.601
0.424
0.344
0.299
0.264
0.234
1.048
0.559
0.401
0.321
0.273
0.239
0.216
7.6
7.0
5.6
6.5
8.8
9.4
7.7
0.870
0.476
0.336
0.282
0.249
0.223
0.199
0.829
0.458
0.335
0.273
0.234
0.207
0.188
4.8
3.9
0.4
3.2
6.3
7.2
5.6
0.662
0.374
0.275
0.230
0.207
0.188
0.169
0.655
0.375
0.281
0.232
0.201
0.179
0.164
1.0
0.2
2.2
1.0
2.9
4.8
3.1
PMOS
# of Segments
Meas.
(V)
Sim.
(V)
Error
(%)
Meas.
(V)
Sim.
(V)
Error
(%)
Meas.
(V)
Sim.
(V)
Error
(%)
1
2
3
4
5
6
7
1.904
0.992
0.679
0.542
0.487
0.415
0.360
1.909
0.984
0.688
0.541
0.449
0.386
0.338
0.3
0.8
1.3
0.2
3.8
6.9
6.1
1.609
0.847
0.575
0.441
0.390
0.347
0.309
1.545
0.812
0.576
0.449
0.379
0.331
0.288
4.0
4.1
0.2
1.7
3.0
4.5
6.7
1.178
0.676
0.443
0.357
0.310
0.280
0.261
1.161
0.678
0.455
0.367
0.311
0.271
0.239
1.4
0.4
2.6
2.8
0.2
3.4
8.4
The total input gate charge measurement is also desirable to analyze the trade-off
relationship between Ron and Qg in a segmented output stage. However, Qg was not able
to be measured directly because there was no test point at the gate terminals of the power
MOSFETs. Therefore, the gate-drive loss, Pgate which is proportional to Qg, was
measured instead as part of the total dynamic power consumption, Pdyn. As shown in Fig.
4.24, the total Pdyn was measured during switching includes the gate-drive loss, diode
conduction and reverse recovery loss, switching loss, shoot-through loss, and power
consumed by the protection circuits and level-shifters in the switching mode [91-92].
Since the measurements are taken by setting the load current to zero, the diode and
switching losses which are proportional to the load current are approximately zero.
Moreover, the gate-drive loss should be theoretically zero when no segment is enabled.
75
25
Power (mW)
20
15
10
5
Pdyn_total
Pgate_total
0
0
# of Segments
Fig. 4.24 Total dynamic and gate-drive power measurements.
1
1.89
1.32
0.57
1.0
2
4.08
2.85
1.23
2.2
3
5.83
4.08
1.75
3.1
4
8.45
5.91
2.54
4.5
5
9.81
6.86
2.95
5.2
6
12.19
8.53
3.66
6.5
7
13.38
9.36
4.02
7.1
76
90%
Efficiency (%)
80%
70%
60%
50%
40%
10
100
1000
Fig. 4.25 Measured power conversion efficiency of HW output stage with a test
conditions: fs = 6.25MHz, Vin = 2.7V, Vout = 1.8V, L = 2.2 H, and C = 100nF.
At 10MHz switching frequency, the waveforms at the output node (Vout) and the
switching node (Vx) were measured at Iout = 158 mA, as shown in Fig. 4.26. All segments
in the output stage were enabled. The fast turn-on and turn-off times indicates the
converter is capable of switching at 10MHz with minimal ripples. All efficiency data of
selected segments were plotted together in Fig. 4.27. The maximum efficiency was found
as 82%. This result confirms that the CMOS power transistors using the HW layout
structure have a performance advantage at light-load conditions with segmented output
stage. The improvement was obtained with no processing or device structural changes.
77
Efficiency (%)
80%
70%
60%
50%
40%
1 SEG
4 SEG
30%
6 SEG
7 SEG
20%
10
100
1000
78
4.5 Summary
This chapter covers the HW layout technique for the design of CMOS power
transistors in a low voltage DC-DC buck converter. A prototype IC that contains
integrated gate drivers, protection circuits and CMOS output power transistors was
implemented in a standard 0.25m CMOS process. The experimental measurements of
the on-resistance and gate-drive loss confirmed the advantages of the HW structure in a
VLSI based process, making the MOSFET a suitable candidate for on-chip, high
frequency switch mode DC-DC converters. The performance improvement was obtained
with no processing or device structural changes. The measured overall on-resistances for
both the n- and p-type power MOSFETs were in good agreement with the earlier
simulation results. Also, the segmentation of the power MOSFET array enhanced the
converter efficiency at the light-load conditions. The maximum measured efficiencies of
the converter switching at 6.25 MHz and 10MHz were 85% and 82%, respectively.
79
80
The basic idea of the SJ-FINFET structure was originated from two existing
technologies: (a) superjunction principle [11] and (b) one of multi-gate transistor
architectures so called FINFET (Fin-Field Effect Transistor) [96]. By combining these
technologies, the SJ-FINFET device was first introduced as shown in Fig. 5.1.
(a)
(b)
Fig. 5.1 Basic idea of SJ-FINFET structure: (a) a fin-gate and (b) with a SJ-drift region
81
However, one of issues within this initial structure is that it needs to fill the trench with
an epitaxial layer, whose growth technique is generally not compatible with modern
CMOS processes. Also, it has a relatively poor crystalline quality due to a higher
dislocation density. To solve this problem, several attempts have been reported by using a
doped poly-Si as an alternative [97] but the inter-diffusion is another issue because a
dopant (e.g. boron) from the as-deposited poly-Si can easily diffuse into the n-pillar or
segregate at the interface during a high temperature thermal processing step.
The overview of the proposed lateral SJ-FINFET is illustrated in Fig. 5.2(a). The
proposed device structure has an embedded trench gate on the side wall and a channel on
the top surface. It is designed to increase the total channel width (i.e. Wtop + Wside) and
provide a more effective conduction path to the drift region. The cross-sections of the
proposed device structure are also demonstrated in Fig. 5.2. It can be seen that the crosssectional area of n-drift (Sn) is larger than that of p-drift (Sp) within the SJ unit-cell. This
asymmetric SJ drift structure are analyzed for different voltage rating in order to examine
its effect on the on-resistance and the sensitivity of the BV due to charge imbalance. To
achieve fully depleted SJ-drift region where Sn is larger than Sp, the doping concentration
of the p-drift layer (NA) should be greater than the n-drift doping concentration (ND). For
trench depths of 2 and 3 m, NA is calculated to be about 23% and 16% greater than ND,
respectively. This indicates that the increase in NA is less pronounced for a deeper trench
82
structure since the difference between Sn and Sp becomes smaller for a deeper trench
structure. Also, the difference between ND and NA can be even smaller as the bottom ndrift layer is not directly connected to the channel. Hence, a full charge balanced
characteristic is mainly required near the sidewall of the drift trench region.
(a)
(b)
Cross-section: A-A
Cross-section: B-B
Wtop
2 or 3
Wside
n-drift
2 or 3
p-drift
Poly-Si
Wtop
DTI
0.3 0.3
Wside
0.6
TGox
0.03
p-body
0.6
(Sp) (Sn)
0.3
0.3
BOX
BOX
SJ unit-cell SJ unit-cell
SJ unit-cell SJ unit-cell
Fig. 5.2 (a) Overview of the proposed lateral SJ-FINFET structure and (b) Schematic
cross-sections along the cut-lines: A-A and B-B
83
Lgate
(c)
Lch
Ldrift
n
+
n+
n-drift
Tepi
n+
p-body
p+
BOX
p-substrate
Lgate
(d)
Ldrift
n
+ Wside
n+
p-drift
WP
WN
p+ p-
Tepi
n+
n-drift
BOX
p-substrate
Lgate
(e)
Ldrift
n
n+
+ Wside
p+ p-
DTI
WP
WN
Tepi
n+
p-drift
n-drift
BOX
p-substrate
Fig 5.2 Schematic cross-sections along (c) n-drift region, (d) p-drift region, and (e) drifttrench region
84
The initial n-drift doping concentration for d = 0.3 m was calculated by [11].
N D 1.411012 7 / 6 d 7 / 6 (cm3 )
(Eq.5.1)
85
Table 5.1: Parameters considered for both process and device simulations
Parameter
Value
0.6
7.4 1016
0.3
5.0 1017
1.0 1020
p+ contact, Np+(cm-3)
5.0 1019
35
0.6
1.0
0.5
2.0
86
87
it was possible to obtain the target lateral diffusion length and its peak doping
concentration. The optimized doping profiles along both X-cut and Y-cut lines from Fig.
5.4(b) are clearly demonstrated in Fig. 5.4(c) and (d), respectively.
Trench Etch
Boron
8e17 cm-3
p-type
Distance (microns)
Phosphorus
n-type
N-epi.
Distance (microns)
Distance (microns)
(a)
(c)
Boron Implant
@ Y = -3
8e17 cm-3
X-cut (X=2)
p-type
Distance (microns)
Y-cut (Y=-3)
Boron
n-type
Phosphorus
P-body
N-epi
Distance (microns)
Distance (microns)
(b)
(d)
Fig. 5.4 P-body formation of the SJ-FINFET: (a) a trench formation by reactive ion
etching process, (b) after 45 tilted B+ ion implantation and thermal annealing process,
(c) a doping concentration profile along X-cut line at X=2, and (d) a doping concentration
profile along Y-cut at Y=-3.
88
The process simulations of the SJ-drift formation were carried out for the crosssections along the line B-B cut line, as shown in Fig. 5.2(a), to determine the optimized
process parameters. The simulated structure for the cross-section through B-B is also
given in Fig. 5.5(a)-(d). Similar to the P-body formation, a deep trench structure is
created by anisotropic dry-etching, but the silicon nitride (Si3N4) hard-mask layer was
considered instead of using the photoresist. Since the width of the drift trench limits the
device performance, a narrow deep trench structure is always preferred in the SJ-drift
region. However, this causes an issue as the sidewall doping process becomes more
difficult due to the shadowing effect [98]. To minimize this effect in a practical
implantation situation, a thin Si3N4 hard-mask layer with a thickness of 2000 was
grown on a sacrificial oxide rather than using a relatively thick photoresist itself.
Together with the trench etch and tilted ion implantation processes, the SJ-drift
structure can be integrated on the SOI platform. By considering the aspect ratio of the
trench structure, the P-pillar formation was simulated by a 12 tilted B+ ion implantation
with maximum energy of 45 KeV and dose of 4 1013 cm-2. After removing the Si3N4
hard-mask, it was followed by a 250-min annealing for drive-in, as shown in Fig. 5.5(e).
The doping profiles of the SJ-drift region with different implant doses were also extracted
as illustrated in Fig. 5.5(f)-(h) because the condition of exact charge balance is important
in obtaining the stable high breakdown voltage during a blocking mode. Since the width
of the alternating n/p pillars was chosen as 0.3 m and the corresponding optimal doping
concentration (ND) was calculated as 7.4 1016 cm3, as described in the section 5.1, the
doping profile of the P-pillar region in Fig. 5.5(g) demonstrates a best match. It has a
fairly uniform doping concentration with some considerably low distortion at the
junctions due to lateral diffusion and at the surface due to charge segregation into the
field oxide. It is noted that these simulation results are validated with the fabricated
devices later in Chapter 6.
89
After annealing
Boron Impt.
After annealing
After annealing
(c)
Distance (microns)
Y-cut (Y=-3)
(d)
Distance (microns)
Y-cut (Y=-3)
Distance (microns)
Distance (microns)
Y-cut (Y=-3)
Distance (microns)
Distance (microns)
Distance (microns)
P-pillar
Boron Impt.
(b)
(a)
Si3N4
Distance (microns)
Boron Impt.
After annealing
Y-cut (Y=-3)
Boron Impt.
N-epi
Distance (microns)
Distance (microns)
Distance (microns)
Distance (microns)
Distance (microns)
Distance (microns)
Distance (microns)
@ Y = -3
Boron
5.5e16 cm-3
n-type
p-type
Distance (microns)
8e16 cm-3
n-type
Boron
p-type
Phosphorus
Phosphorus
Distance (microns)
Distance (microns)
(f)
(e)
1e17 cm-3
@ Y = -3
log (doping conc.)
@ Y = -3
Boron
p-type
n-type
1.3e17 cm-3
Boron
p-type
n-type
Phosphorus
Phosphorus
Distance (microns)
(g)
Distance (microns)
(h)
Fig. 5.5 P-pillar formation of the SJ-FINFET structure: (a)-(d) are the cross-sections
along the B-B cut line after 12 tilted B+ ion implantation (left) and thermal diffusion
(right) steps and (e)-(h) are the corresponding doping profiles for different B+ ion
implantation doses.
90
@ Y = -3
Distance (microns)
Y-cut (Y=-3)
N+
P-body
Boron
N-epi
N+
Arsenic
P-body
N-epi.
Distance (microns)
(a)
Distance (microns)
(b)
Fig. 5.6 N+ source/drain contact formation of the SJ-FINFET: (a) after 45 tilted dualimplant of n-type dopant species (i.e. arsenic and phosphorus) and thermal diffusion steps,
and (b) a doping concentration profile along Y-cut line at Y=-3.
91
92
reliable simulation of breakdown at the drain junction, the mesh was also more
concentrated inside the junction depletion region for a better resolution of avalanche
multiplications. In addition, the boundary between the n- and p-pillars was re-fined many
times to obtain more accurate full charge-balance condition between them.
Drain
SJ-drift
Gate
DTI
Source
p-body
BOX
p-sub
(a)
Drain
channel
Source
p-drift
n-drift
p-body
p-sub
(b)
Fig. 5.7 Unit-cell of the SJ-FINFET: a) w/ and b) w/o any oxide materials
93
The simulated SJ-FINFET device had several different drift region lengths with a
trench gate depth (i.e. Wside) of 2 m. The widths of the alternating n/p pillar were W n =
Wp = 0.3 m and because in actual device operation each pillar is depleted by two
neighboring pillars, only one half of the SJ-FINFET structure was considered in the
simulations. In the device simulations, the optimal doping concentrations of the pillars
were initially calculated as ND= 7.4 1016 cm3 and NA = 9.25 1016 cm3 from the Eq.
5.1 and subsequently optimized by simulations.
The off-state equi-potential and electric field contour plots of the SJ-FINFET with
Ldrift = 3.5 m at the breakdown point are shown in Fig. 5.8 and Fig. 5.9, respectively. As
avalanche breakdown begins, free electrons are accelerated by the electric field to very
high speeds. If their velocity is high enough, when they strike an atom, they knock an
electron free from it (i.e. ionization). Both the original electron and the newly freed one
are then accelerated by the electric field and strike other atoms. As this process continues,
the number of free electrons moving through the material increases exponentially, thus
avalanche breakdown can result in the flow of very large current. Fig. 5.9 demonstrates a
relatively uniform electric field distribution over the entire drift region. This indicates
that the pillars are depleted mutually and charge compensation is in effect. A breakdown
voltage of 65V was achieved for this SJ-FINFET on SOI corresponding to an average
lateral electric field of 18.5V/m.
The operating principle of the SJ device is based on charge compensation. The charge
imbalance between n-drift and p-drift layers directly affects the value of BV. Thus, it is
important to evaluate the effect of charge imbalance in order to achieve the maximum BV.
Fig. 5.10 presents the relationship between BV and charge imbalance. It can be seen that
the variation of Ldrift has no effect on the charge imbalance but the increase of trench
depth from 2 m to 3 m gives a 5% positive shift of the charge imbalance (%) for the
optimal BV. This can be explained by the fact that the areas of n-/p- pillars (i.e. Sn and Sp
from Fig. 5.2(b)) are always constant at a fixed trench depth whether Ldrift increases or
94
not. However, the ratio between Sn and Sp becomes smaller for a deeper trench structure.
Therefore, the difference between ND and NA would also be smaller as the trench depth is
increased. In this figure, the BV of SJ-FINFET is highly sensitive to the charge
imbalance in the pillars. If charge imbalance between the pillars exists, the gradient of the
electric field in the drift region is proportional to the pillars doping concentrations for a
specific charge imbalance (%) with the resultant p-p-n+ (for NA > ND) or p-n-n+ (for ND >
NA) diode having effectively highly doped drift region. Such high sensitivity imposes
stringent requirements for a precisely controlled fabrication process.
The BV simulations of the SJ-FINFET were also carried out for several different drift
lengths while the optimum charge balanced conditions were maintained in all cases. In
this analysis, Ldrift was varied from 3 m to 12 m and all other parameters were kept the
same. In Fig. 5.11, the BV is found to increase linearly with a slope of about 18 V/m
while Ldrift is increased from 3 m to 6 m. As the drift length becomes greater than 6
m, the slope begins to reduce; eventually reaching about 15 V/m at Ldrift = 12 m.
Since the avalanche failure mechanism occurs near the gate edge on the drain side, this
result suggests that a further optimization of field plate is necessary for drift lengths
greater than 6 m.
95
Drain
2V/div
Field oxide
Gate
Source
DTI
BOX
p-sub
(a)
2V/div
Drain
Gate
SJ-drift
Source
p-body
BOX
p-sub
(b)
Fig. 5.8 Contour plots of the electrostatic potential distribution in off-state for a proposed
SJ-FINFET with p-pillar impurity concentration of 9.25 x 1016 cm3 under charge
balance: a) w/ and b) w/o any oxide materials
96
Drain
n
p
Gate
Source
n
p
p-body
BOX
BOX
p-sub
(a)
Drain
n
p
Gate
Source
n
p
p-body
BOX
p-sub
(b)
Fig. 5.9 Contour plots of the electric field distribution in off-state for a proposed SJFINFET with p-pillar impurity concentration of 9.25 x 1016 cm3 under charge balance:
a) w/ and b) w/o refined mesh structure.
97
120
Wside / Ldrift = 2m / 6m
Wside / Ldrift = 3m / 6m
BV (V)
100
80
Wside / Ldrift = 2m / 3m
60
Wside / Ldrift = 3m / 3m
40
-30
-25
-20
-15
-10
-5
1E-04
1E-05
Ld=3.0m
Id (A/cm 2 )
Ld=3.5m
1E-06
Ld=4.0m
Ld=4.5m
Ld=5.0m
1E-07
Ld=6.0m
Ld=8.0m
1E-08
Ld=12.0m
1E-09
0
50
100
150
200
Vds (V)
Fig. 5.11 I-V characteristics of the proposed SJ-FINFETs during off-state for various drift
region lengths.
98
The simulated transfer characteristic of the SJ-FINFET with Ldrift = 3.5 m was
obtained in the on-state and are shown in Fig. 5.12 for Vds = 5V. The threshold voltage of
the device was approximated by the extrapolated intercept of the linear portion of the
Ids(Vgs) curve with the Vgs axis. The threshold voltage was estimated to be 1.75V. Given
that the devices have same gate length, gate oxide thickness and channel doping
concentration, it is expected for their threshold voltages to be identical. A higher
threshold voltage can be possible but it will require an extra mask and a dedicated
channel implantation process inside the p-body region.
0.9
0.8
Ids (A)
0.7
0.6
0.5
0.4
0.3
0.2
Vth ~ 1.75 V
0.1
0
0
0.5
1.5
2.5
Vgate (V)
99
dissipation. In a linear region, the device acts as a resistor with almost a constant onresistance, Ron defined by Vds / Ids. To extract the specific on-resistance (Ron,sp), the area
factor which implies how many unit-cells can be substituted into the final device, should
be defined in the device input file. The simulated Ron,sp of the device was 0.498 mcm2
at VG = 10V. Since the BV is independent of the SJ depth, the greater pillar height is
preferred for a higher electron current density, however the shadowing effect from the
tilted ion implantation (as addressed in the section 5.2) should be minimized along with
other process limitations such as etching selectivity, trench profile (i.e. aspect ratio),
minimum processing rule, high dislocation density in the n-epi, etc.
In Fig. 5.14, the I-V characteristics of the SJ-FINFETs with Wside = 2 m were
simulated in the on-state for different Ldrift while the optimum charge balanced conditions
(ND= 7.4 x 1016 cm3 and NA = 9.25 x 1016 cm3) were maintained in all cases. In this
analysis, Ldrift was varied from 3 m to 12 m and all other parameters were kept the
same. Note that the specific on-resistance for each Ldrift can be calculated from the plot.
As the drift length of the SJ-FINFET increases, the drain-to-source current is found to be
decreased. Since the drift resistance is proportional to the drift length, it is obvious that a
smaller amount of current flows through a longer current path.
Lastly, Fig. 5.15 plots BV and Ron,sp as a function of Ldrift for two different trench gate
depths (i.e. Wside = 2 m or 3m). This confirms that a low Ron,sp can be achieved by
using high aspect ratio trench. This fact can be utilized to overcome the problem of BV
sensitivity to the charge imbalance. A recommended solution is that first one should
determine a required increase of the drift region length to offset the degradation in BV
and finally to negate the resulting increase in Ron,sp by adopting a higher aspect ratio
pillars.
100
VG = 10 V, VDS = 0.1 V
(a)
2.2
2
VG = 10 V
1.8
Ids (A)
1.6
1.4
VG = 5 V
1.2
1
0.8
0.6
0.4
VG = 3 V
0.2
0
0
0.02
0.04
0.06
0.08
0.1
Vds (V)
(b)
Fig. 5.13 On-state simulations: (a) electron current density distribution and (b) output
characteristics of the SJ-FINFET with Ldrift =4.5 m and device area = 1 mm2.
101
400
Ld=3.0m
Id (A/cm2 )
300
Ld=3.5m
Ld=4.0m
Ld=4.5m
200
Ld=5.0m
Ld=6.0m
100
Ld=8.0m
Ld=12.0m
0.02
0.04
0.06
0.08
0.1
Vds (V)
Fig. 5.14 I-V characteristics of the proposed SJ-FINFETs during on-state for various drift
region lengths.
200
2.5
160
2.0
120
1.5
80
1.0
BV @ Wside=2m
BV @ Wside=3m
40
R on,sp (mcm2 )
BV (V)
@ VG = 10 V
0.5
Ron,sp @ Wside=2m
Ron,sp @ Wside=3m
0.0
2
10
12
Ldrift (m)
Fig. 5.15 The trade-off relationship between BV and Ron,sp of the SJ-FINFET for different
drift region lengths.
102
103
Gate
Rsource
Rn-drift
Rch
Rdrain
0.6
Ron,sp (mcm2 )
0.5
Conventional
SJ SOI-LDMOS
0.4
n-drift
source
drain
channel
0.3
Wside = 2m
0.2
Wside= 3m
0.1
SJ-FINFET
0
0
Ldrift (m)
Fig. 5.16 Specific on-resistance profile along C-C cut line during on-state for
conventional SJ SOI-LDMOS and the proposed SJ-FINFETs
Moreover, Fig. 5.17 demonstrates the corresponding carrier mobility (i.e. electron)
characteristics along the same cross-section. Since the electron mobility is well-known
as the ratio of carrier velocity in the field direction (i.e. drift velocity) to the magnitude of
the electric field, a high electric field near the gate edge (i.e. Y = 2m) makes both
devices to have a relatively decreased mobility. However, the SJ-FINFET employs the
triple gate concept not only to enhance the electron mobility in the channel but also to
relax both vertical and lateral electric field near the gate edge. Therefore, the decrease in
the electron mobility is much less than the conventional SJ-LDMOS structure, as
104
illustrated in the simulated result. It is also observed that the mobility is saturated as a
consequence of the velocity saturation of electrons in the n-drift region.
Gate
Rsource
Rn-drift
Rch
Rdrain
1200
Mobility (cm2/Vs)
Conventional SJ-LDMOS
SJ-FiNFET w/ Wside = 3m
1000
800
600
400
200
0
0
Y-distance (m)
Fig. 5.17 Mobility profile along C-C cut line during on-state for conventional SJ SOILDMOS and the proposed SJ-FINFET with Wside = 3 m.
Fig. 5.18 presents the electric field distribution of the SJ-FINFETs with two different
values of NA. The cross-section along the C-C cut line from Fig. 5.2(a) was also used to
obtain the electric field distribution shown in this plot. At the gate edge, a high electric
field can be observed with a low NA of 9.25 1016 cm3 and if the NA is increased to 9.87
105
1016 cm3, a high electric field is moved toward the drain edge. The optimum electric
field strength distribution is obtained with the NA of 9.25 1016 cm3. This proves that
the optimum charge balanced condition of the SJ-FINFET can be obtained with NA lower
than ND. As previously discussed in the Section 5.3.2, the optimal doping concentration
of the p-pillar should be greater than that of n-pillar doping because of the smaller area of
p-drift region within the SJ-FINFET structure. This also indicates that the simulated
result is in a good agreement with the theoretical calculation from Eq. 5.1. It is important
to note that relaxing the electric field at the gate edge can achieve a higher breakdown
voltage. The avalanche breakdown occurs at the junction between the p-body and n-drift
layer when the electric field reaches the critical value, Ec of approximately 5105 V/cm.
5E+05
4E+05
3E+05
2E+05
1E+05
0E+00
0
Y-distance (m)
Fig. 5.18 Comparison of the electric field distribution (along the C-C cut line) for the SJFINFETs with two different values of NA at ND= 7.4 1016 cm3and Wside = 2 m.
Since the optimal doping concentrations of the SJ-FINFET with Wside = 2 m was
determined, the SJ-FINFET with Wside = 3 m also needed to be investigated in
comparison to a conventional SJ-LDMOS structure. In Fig. 5.19, all simulations were
106
carried out in the same doping of the SJ-drift region; ND = 7.4 1016 cm3 were and NA =
9.25 1016 cm3. The peak E-field comparison at the gate edge of the n-drift region
demonstrates that the SJ-FINFETs have approximately 10% lower values than the
conventional SJ-LDMOS structure. Since Ec is a function of the doping of n/p pillars
hence a fixed value for those devices, this simulation result indicates that the higher
breakdown voltage can be expected in the SJ-FINFETs. It is also interesting to note that
that the SJ-FINFET with the deeper trench gate (i.e. Wside = 3 m) shows a relatively less
uniform electric field distribution in the n-drift region than that of the other SJ-FINFET.
This can be explained by the fact that the optimal doping concentration (NA) of the ppillar is also a function of its height. The U-shaped geometry of the p-pillar was used in
the SJ-FINFETs, therefore the ratio between Sn and Sp (i.e. cross-sectional areas of n-/ppillars, as described in the section 5.1) becomes smaller for a deeper trench structure. As
a result, the difference between ND and NA should be smaller as the trench depth is
increased. By considering this fact, the optimal NA for the SJ-FINFET with Wside = 3um
is re-calculated as 8.7 1016 cm3.
6E+05
Conventional SJ-LDMOS
SJ-FINFET with Wside = 2m
5E+05
4E+05
3E+05
2E+05
1E+05
0E+00
0
Y-distance (m)
Fig. 5.19 Electric field distribution comparison between the conventional SJ-LDMOS and
SJ-FINFETs at NA = 9.25 1016 cm3 and ND = 7.4 1016 cm3.
107
[104]
[104]
[105]
Simulated conventional
lateral SJ-LDMOS
BV1.9-2.0
[105]
[105]
[102]
[104]
Simulated SJ-FINFET
(: 2m and : 3m)
[103]
[102]
[101]
[101]
0.1
10
Si-limit: BV2.5
90V
165V
100
Breakdown voltage (V)
Fig. 5.20 Performance comparison between SJ-FINFETs and previously published data.
108
5.5 Summary
In this chapter, a novel device structure suitable for practical implementation of
lateral superjunction FINFET (SJ-FINFET) on SOI platform was proposed and studied
for next generation of sub-200V rating power applications. The SJ-FINFET structure
with heavily doped alternating U-shaped n/p pillars was developed to minimize both
channel and drift resistances, and to mitigate electron current crowding near the top of ndrift region. The feasibility of the design concept was validated by a two dimensional
process simulator, TSUPREM-4TM for three important process modules such as a) P-body
formation, b) SJ-drift formation, and c) N+ source/drain contact formation. In comparison
with the conventional planar gate SJ-LDMOS device, the SJ-FINFET device was also
investigated for different trench gate depths and drift lengths. Three dimensional
numerical simulations with ISE-DESSISTM have been performed to analyze the influence
of device parameters on the charge imbalance and the trade-off relationship between BV
and Ron,sp. To summarize, the SJ-FINFET structure exhibits low Ron,sp with voltage
ratings below 200V. With the optimized charge balanced SJ-drift region, the SJ-FINFETs
were found to be able to overcome the Si-limit with the breakdown voltages of 165 V and
90 V, respectively. This is a positive indication that the SJ-FINFET can become a
competitive power device for sub-200V applications [106]. In the next chapter, the
detailed fabrication process of the SJ-FINFET would be presented followed by the
experimental measurement results of both SJ-FINFET and SJ-LDMOS devices. The
issues related to the optimization of the SJ structure and process integration would be also
discussed.
109
110
layer were 3.5m, 500m, and 2m, respectively. The detailed specifications of the SOI
wafer are described in Table 6.1.
Table 6.1 Parameters and specifications of the SOI wafer used in the fabrication
Parameters
Specifications
SOI Wafer: Silicon Fusion Bonding (SFB)
Diameter
100 0.2 mm
Crystal Orientation
(100) 0.5 degree
Flat
Standard: <100>
Overall Thickness
505.5 25 m
Thickness Variation
< 2 m
Surface/Backside
Polished / Lapped
Device Layer (Epi.)
Type / Dopant
N-type / Phosphorus
Thickness
3.5 0.5 m
Resistivity
0.1 0.2 cm
Buried Oxide Layer (BOX)
Type of Oxide
Thermal Oxide
Thickness
2.0 0.1 m
Handle Wafer (Substrate)
Type / Dopant
P-type / Boron
Thickness
500 25 m
Resistivity
60 70 cm
The SJ-FINFET fabrication was compatible with a standard 0.5m CMOS flow. To
realize the SJ-FINFET, new optional process modules were developed that can be added
to the baseline CMOS technology. Fig. 6.1 represents a condensed flow chart for the SJFINFET process. For example, two different deep trench etches are necessary prior to the
formation of the gate electrode. The sidewall doping of the trenches can be performed by
a tilted ion implantation. With additional thermal diffusion steps, the doped trench
regions are activated as the P-body and P-drift (i.e. SJ-drift) regions, respectively. Gate
lithography and etch, gate oxidation, in-situ (n-doped) amorphous silicon deposition,
poly-crystallization, poly-silicon etch and doping annealing are then carried out to form
the gate electrode. When a positive potential higher than the threshold voltage is applied
111
to the gate electrode, an inversion layer is created along the sidewall of the trench and
underneath the top surface in the p-body region. The created channel allows electron
current to flow laterally from the source to the drain electrode. The formations of deep
trench source/drain are also necessary in order to achieve more uniformly distributed
electron current flow in the n-drift region. Similar to the P-body region, the sidewall
doping of each trench can be created by a tilted ion implantation. After a thick
passivation oxide layer is deposited, the contact lithography and oxide etching are
required to open the contact windows followed by a metallization process. Some of
process design considerations are described in greater detail in the following pages.
Additional Steps
SOI-substrate
Active & Isolation
P-body Trench Formation
P-well or N-well I/I
SJ-drift Formation
Gate Lithography
Trench Gate Formation
Gate Oxidation
S/D Trench Formations
Source & Drain I/I
Passivation & Contacts
Metallization
Fig. 6.1 Standard CMOS process flow with additional steps for the lateral SJ-FINFET
implementation.
112
Resist
Nitride
Pad
Oxide
Silicon
Resist
Liner
Oxide
Nitride
Silicon
Isolat.
Oxide
Isolat.
Oxide
Isolat.
Oxide
(e) CMP
Fig. 6.2 Six sequential processing steps required for the deep trench isolation region.
113
114
threshold voltage rolls off as the channel length is reduced. The short channel effect
(SCE) complicates device operation and degrade device performance. As a result, this
effect needs to be minimized so that a short channel device can preserve the electrical
characteristics of a long channel device.
The minimum channel length, Lmin in which a long channel sub-threshold behavior
can be preserved can be calculated from the empirical relation [108].
(Eq.6.1)
Dopant redistribution is one of the major concerns for the thermal budget in process
integration. In addition, the thermal budget induces a stress from various interfaces
between the substrate and other deposited layers. Since the SJ-FINFET fabrication
requires a deep trench isolation region filled with LTO and the silicon nitride layer as a
hard mask, the wafer warpage should be considered as another process design issue. To
minimize the degree of the wafer warpage, several methods had to be considered. First,
the low stress silicon-rich nitride was used as the hard-masking layer, instead of the
stoichiometric silicon nitride because it induces a less tensile stress. The thickness of the
deposited nitride layer was further reduced to obtain even less tensile stress. Another
method was that the thermal SiO2 liner (compressive stress) was grown inside the trench
prior to the LTO gap-filling and densification processes (tensile stress). This results that a
high tensile stress induced by LTO could be reduced. Also, all stress layers deposited at
the backside of the wafer were not completely removed for the stress neutralization
purpose. Lastly, the thermal budget was limited to 900 C after all high dose
implantations.
115
116
where a p-body trench would be formed by means of photolithography. The oxide film
was then etched by RIE using photoresist as a mask. In this RIE step, the etching had to
be carefully performed so as to prevent photoresist from burning-out. After the initial RIE
step, the n-epi silicon device layer was etched by ICP-RIE (Induced Coupled Plasma
RIE) to form a p-body trench structure followed by photoresist acid strip and RCA
cleaning steps (e.g. sulfuric clean + HF dip). This trench structure was required to form a
p-body region on the sidewall of the trench by 45 B+ tilted ion implantation. The
implant dose and energy were 2.21014/cm2 and 180keV, respectively. To prevent the
out-diffusion of boron during annealing, a 250 oxide liner was grown inside the trench
prior to the thermal diffusion step. Not only the liner helps to prevent the out-diffusion of
boron but also it minimizes the stress which induces a dislocation in the silicon layer. The
p-body annealing process was then carried at 850C for first 10 minutes and at 950C for
additional 30 minutes. By considering all thermal process steps greater than 850 C, the
specific annealing condition for the p-body region was extracted based on the process
simulation. After the initial p-body annealing step, the trench was gap-filled with a 3 m
thick of LTO at 425C in a CVD furnace (e.g. deposition rate: 115 /min, gas flow rate:
O2 = 50 sccm, SiH4 = 40 sccm). This was then followed by the thermal densification at
900C for 30 minutes. For the next processing step, the LTO deposited on the top surface
was completely removed by using a combination method of CMP and RIE with a high
selectivity of oxide and silicon (i.e. LTO: Si > 100).
MASK #3 SJ-drift
As illustrated in Fig. 6.3(f) to (h), a thin 250 sacrificial oxide was thermally grown
and then a 4000 thick low stress nitride was deposited on the top of the oxide by
LPCVD. The nitride layer was added as a hard-masking layer for the SJ-drift formation.
This was due to the fact that a deep and narrow trench structure (i.e. a high aspect ratio)
was required in the drift region and the sidewall of the trench had to be doped by a low
angle tilted implantation. To achieve a more uniform p-pillar junction profile, a thick
photoresist had to be replaced by a relatively thin and stable nitride layer. Not only it
helped to reduce the shadowing effect but also the nitride was able to protect the other
117
silicon active area from the high energy implantation. After Mask #3 was used to define
the drift trench pattern, the nitride layer was etched and stopped by an end-point detection
method. This was then followed by ICP-RIE to create the drift trench structure with a
depth of 2.6 m and a width of 0.6 m. After the trench formation, the sidewall doping of
the trench was carried out by a 12 B+ tilted implantation with energy of 45 keV and four
different doses of 21013/cm2, 41013/cm2, 61013/cm2, and 11014/cm2 for each different
SOI wafer. To obtain the optimal charge balanced condition in the SJ-drift region, it was
necessary for each SOI wafer to have a different charge imbalance (%) condition. Since
the p-drift region should be connected to the p-body and eventually to p+ body contact to
form a SJ-diode structure, a 45 B+ tilted implantation with energy of 80 keV and dose of
3.51013/cm2 was also carried out with 90 and 270 rotations of the SOI wafer, as shown
in Fig. 6.3(g). Similar to the earlier p-body trench structure, the drift trench was also
filled with LTO followed by densification and CMP planarization steps. After that, the
nitride hard mask was completely removed by H3PO4.
MASK #4 Trench Gate
As illustrated in Fig. 6.3(i) to (j), a thin 250 pad oxide was first grown and a high
resolution photoresist was spin-coated and soft-baked on the top of the oxide. After the
photoresist was patterned with Mask #4, another high aspect ratio trench was formed by
ICP-RIE. This was then followed by the pad oxide removal and gate oxidation steps. A
high quality 35nm thin oxide was grown as a gate oxide at 950C in dry O2. The quality
of the gate oxide is very crucial in determining the performance of the device. To
enhance the quality of the oxide, a small amount of NH3 was introduced into the thermal
growth cycle to reduce the amount of the mobile ionic charge in the oxide. After the gate
oxide growth, the substrate was immediately deposited by in-situ n-doped amorphous
silicon at 570C. In a conventional CMOS process, a polysilicon gate is doped
simultaneously with a source/drain implant step. However, the SJ-FINFET requires a
corrugated 3D trench MOS gate and this makes the polysilicon gate difficult to be doped
by an implantation technique. Hence, a polysilicon deposition step had to be replaced by
an n-doped amorphous silicon deposition and then re-crystallized into the n-doped
118
polysilicon gate by RTP (1000 C and 30 seconds). To avoid the wafer warpage issue, the
poly-silicon deposited at the backside of the SOI wafer was completely removed prior to
the RTP step.
MASK #5 Gate Poly
As illustrated in Fig. 6.3(k), the conventional gate mask (i.e. Mask #5) was used to
define the entire gate electrode. For a better step coverage, the polysilicon was etched by
ICP-RIE and stopped at the oxide interface by end-point-detection. For comparison
purpose, the planar gate SJ-LDMOS devices were also fabricated on the same wafer
without the previous trench gate mask (i.e. Mask #4).
MASK #6 N+ source / drain
As shown in Fig. 6.3(l) to (o), the formations of deep trench source/drain were
necessary to achieve more uniformly distributed electron current flow in the n-drift
region. Mask #2 was re-used to ensure that a high energy n+ source implantation do not
block the p-body tail underneath the n+ source region. Mask #6 was then used to define
the n+ drain region. The sidewall doping of each trench was carried out by a 45 titled
dual-implant of n-type dopant species such as arsenic and phosphorus. Since the two
implants were identically masked, the greater diffusivity of the phosphorus meant that it
would diffuse laterally in advance of the arsenic during annealing of the implant.
Therefore, the arsenic provides a low contact resistance while the phosphorus provides a
more gentle junction curvature.
MASK #7 P+ contact
As demonstrated in Fig. 6.3(p) to (r), the photoresist was patterned using the Mask #7.
This was followed by dry etching process using plasma, thereby forming a 3m depth of
trench structure as shown in Fig. 6.3(q). This trench structure was required for p+ contact
implant. Boron implantation with energy of 180keV and dose of 51014/cm2 was
implemented and then a 4m thick LTO passivation layer was deposited, densified, and
119
planarized. The passivation oxide should be thick enough to reduce the parasitic
capacitance between the metal pad and the substrate.
MASK #8 Contact openings
Mask #8 was used to open the contact windows for the gate and source/drain contacts,
as shown in Fig. 6.3(s). To open the contact windows, a 3m thick LTO filled in the
trenches was initially removed by RIE and then the oxide residues were completely
removed by a chemical etching to ensure a good electrical contact between the metal
wiring layer and the silicon.
MASK #9 Metallization
A 1 m of aluminum (Al-1wt% Si) layer was sputtered on the SOI wafer, at a
sputtering rate of 182 /sec. Mask #8 was used for metal patterning as illustrated in Fig.
6.3(t). Aluminum was dry etched at an etching rate of 1500 /min and the photoresist
was then removed by an O2 plasma ashing. In the final step, the wafer was annealed in a
forming gas (5% hydrogen, 95% nitrogen) for 30 minutes at 400 C to reduce the contact
resistance and the interface trapped charge in the gate oxide.
Process Specifications
More detailed information such as the process step number, processing condition, and
equipment are summarized in Appendix-V. The process was characterized at various
stages. The typical process and electrical parameters obtained from the fabrication test
structure are listed in Table 6.2. The layer thickness and step height were measured using
the NanoSpec 4000 and the Alpha-Step 200 surface profiler. The sheet resistance of the
poly gate was measured using a 4-pint probe. The contact resistance was obtained from
the measurement of the 6-terminal Kelvin structure [110].
120
(a)
Mask #1
Active definition
n-type SOI wafer (Phosphorus)
Resistivity = 0.1 0.2 cm
electron conc. ~ 7.4 1016 / cm3
(b)
Pad Oxide: Dry 300, 950C
(c)
Mask #2
P-body definition
Oxide etch: RIE, 10% over-etch
Deep-Si etch: RIE (depth = 2.7 m)
Inspection
(d)
B, 2.2e14 cm-2, 180 keV, 45
hole conc. ~ 5 1017 / cm3
(e)
Photoresist removal: ash / acid strip
P-body diffusion: 950 C / 1050 C
(f)
Trench gap-filling: LTO, 425 C
LTO densification: 900 C
CMP (planarization)
Sacrificial oxidation: 250
Nitride deposition: 4000 , 780 C
(g)
Mask #3
P-pillar definition
Hard mask etching: RIE
Si etching: ICP-RIE (depth = 2.6 m)
Boron, dose: 2,4,6, and 8e13 cm-2
energy: 45 keV, titled angle: 12
rotation: 0 and 180
Boron, dose: 3.5e13 cm-2
energy: 80 keV, titled angle: 45
rotation: 90 and 270
(h)
Trench gap-filling: LTO, 425 C
LTO densification: 900 C
CMP (planarization)
LTO etch: dry and wet
Nitride strip: H3PO4, 165 C
Oxide removal: HF:H20 (1:50)
(i)
Mask #4
Trench gate definition
High resolution photoresist
Sacrificial oxidation: 250
Si-etch: ICP-RIE (2.7 m)
Oxide removal: HF:H20 (1:50)
(j)
Gate oxide growth: Dry, 350
N2 annealing at 900 C
Amorphous-Si deposition: In-situ
Transformation to Poly-Si: 1000 C
Inspection: Rsh 25 / sq.
Backside etch: Poly-Si
(k)
Mask #5
Gate poly definition
Descum: O2 Asher
Poly-Si etch: ICP, End-point-detect
Photoresist: ash / acid strip
HF dip, rinse, and spin dry
Inspection: SEM
(l)
Mask #2
N+ source definition
Sacrificial oxide: Dry, 950 C
Photoresist: coat / develop / bake
Descum: O2 Asher
Oxide etch: 10% over-etch
LTO etch: Dry, 2.2 m
LTO etch: Wet, 0.3 m
(m)
(n)
Mask #6
N+ drain definition
Si-etch: RIE (2.7 m)
P , dose: 5e14 cm-2
energy: 180 keV, titled angle: 45
As , dose: 9e14 cm-2
energy: 200 keV, titled angle: 45
rotation: 90 and 270
(o)
Photoresist removal
Field oxide growth: 4 m
LTO densification: 900 C
S/D Activation: 1000 C
CMP (planarization)
(p)
Mask #7
P+ contact definition
Photoresist: coat / develop / bake
LTO etch: 3 m
Sulfuric clean / HF dip
(q)
B , dose: 5e14 cm-2
energy: 180 keV, titled angle: 7
rotation: 90 and 270
(r)
Trench gap-filling: LTO, 4 m
LTO densification: 900 C
P+ annealing: 950 C
CMP (planarization)
(s)
Mask #8
Contact hole definition
Photoresist: coat / develop / bake
LTO etch: 3 m, 10% over-etch
Sulfuric clean / HF dip
Inspection: NanoSpec / Alpha-Step
(t)
Mask #9
Metallization definition
Al sputter: Al :1% Si, 1 m
Photoresist: coat / develop / bake
Al etch: Dry, 1m
Photoresist Ash: O2 asher
Inspection: optical microscope
Forming gas annealing: 400 C
Values
0.1 0.2 cm
3.5 m
2.0 m
Substrate thickness
500 m
350
0.6 m
1.2 m
2.7 m
5000
24.6 /
5.0 m
2.7 m
0.3 m
1.2 m
0.5 m
0.6 m
2.6 m
1.1 m
4000
1.0 m
1.2 m
DTI thickness
3.5 m
0.03 m
126
1.1
1.2
5.4
4.1
2.1
2.2
2.3
2.4
4.2
7.2
3.1
6.2
3.2
7.1
5.1
7.3
6.1, 8.1
3.3
4.3
3.4
8.2
5.2
5.3
3.5
9.2
9.3
ACTIVE
PWELL
DRIFT
FIN
POLY
9.1
NIMP
PIMP
CONT
METAL
Fig. 6.4 Layout design rules for the proposed SJ-FINFET device on a SOI platform.
127
Defining design rules involves the consideration of factors such as the lateral
diffusion, minimum device area and maximum misalignment of the equipment. Mask
alignment error can be defined as the mask alignment tolerance (0.03 m for ASML
Stepper 5000) multiplied by the square root of the number of alignment steps. In this
design, a minimum line width of 0.5 m and an alignment tolerance of 0.1 m were used.
The layout design rules for the low voltage SJ-FINFET devices are illustrated in Fig. 6.4
and summarized in Table 6.3.
Table 6.3 Summary of SJ-FINFET layout design rules
Mask
ACTIVE
PWELL
DRIFT
FIN
POLY
NIMP
PIMP
CONT
METAL
Layout
Rule No.
Description
1.1
1.2
2.1
2.2
2.3
2.4
3.1
3.2
3.3
3.4
3.5
4.1
4.2
4.3
5.1
5.2
5.3
5.4
6.1
6.2
7.1
7.2
7.3
8.1
8.2
9.1
9.2
9.3
Minimum width
Minimum clearance to contact opening
Minimum width
Minimum clearance to trench gate
Minimum clearance to gate poly
Minimum clearance to drift edge
Minimum width of drift trench
Minimum p-pillar diffusion length
Minimum spacing between p-pillars
Minimum spacing between drift trenches
Minimum length of drift trench
Minimum width
Minimum spacing between trench gates
Minimum overlap between FIN and DRFIT
Minimum width
Minimum overlap between FIN and POLY
Minimum overlap between POLY and drift edge
Minimum extension of poly to active
Minimum width
Minimum clearance to drift edge
Minimum width
Minimum overlap between PWELL and PIMP
Minimum clearance to trench gate
Minimum width
Minimum overlap between PIMP and CONT
Minimum width
Minimum spacing between metal lines
Minimum overlap between CONT and METAL
Dimension
(m)
12.2
0.3
3.6
0.6
0.5
1.4
0.5
0.25
0.6
1.2
3.0
0.9
0.6
0.1
1.4
0.1
0.2
0.5
3.6
0.6
3.6
0.6
1.5
3.6
0.6
5.0
5.0
0.5
128
Instead of a conventional contact aligner which loads the mask directly in contact
with the substrate and exposes the photoresist, a 5 i-line (=365nm) stepper was used as
a photolithography tool for a better resolution and tolerance. This corresponds to the fact
that the feature size on the mask will be five times larger than the drawn layout size. The
SJ-FINFET fabrication requires a total of nine masking layers and the mask information
is as summarized in Table 6.4.
Description
Polarity (layer #)
1. ACTIVE
Clear (3)
2. PWELL
Dark (237)
3. DRIFT
Dark (63)
4. FIN
Dark (4)
5. POLY
Clear (13)
6. NIMP
Dark (8)
7. PIMP
Dark (7)
8. CONT
Contact openings
Dark (15)
9. METAL
Al-Metallization
Clear (16)
The entire test chip layout is as illustrated in Fig. 6.5. The total area of the layout is
100,000 m 100,000 m (or 500,000 m 500,000 m for the mask). The test chip
contains various process and device test structures of different sizes. It consists of six
groups of test elements (A-F):
(A) This group includes a large inter-digitated (i.e. multi-finger) SJ-FINFET structure
with a total gate width of 111,600 m.
129
(B) This group includes a large inter-digitated SJ-LDMOS structure with a total gate
width of 111,600 m for a comparison purpose.
(C) This group includes various single and multi-finger SJ-FINFET and SJ-LDMOS
structures for different gate width (10, 20, 40, 80, 100, and 200 m) and SJdiodes with different drift lengths (3.5, 4.5, 6, 8, 10, and 12m). Each device has
connected to the test pads with size of 100 m 100 m for DC measurement.
(D) This group includes several multi-finger SJ-FINFET (W = 200 m) structures for
different n/p width ratios (0.67, 1.00, 1.33, and 1.67) and SJ-drift trench widths
(0.6, 0.8, 1.0, and 1.2). They are also subdivided into different drift length for a
comparison purpose.
(E) This group includes several multi-finger SJ-FINFET (W = 200 m) structures for
different source/drain trench width (3.6 - 5m), gate length (1-1.8m with a 0.1
m increment), and field plate length (0.1-0.9 with a 0.1 m increment). Also, it
contains the test structures for contact resistance, sheet resistance (a Kelvin cross
with 6 terminals), and open/short circuit (i.e. leakage current) measurements of
the various layers.
(F) Lastly, this group includes various process test structures required for film
thickness, step height and coverage (i.e. monitoring etching) measurements. The
alignment marks and critical dimension (e.g. SEM inspection) structures are also
included as illustrated in Fig. 6.6.
130
(C)
(B)
(A)
(D)
(F)
(E)
Fig. 6.5 A full test chip layout of both SJ-FINFET and SJ-LDMOS device.
(a)
(b)
(c)
Fig. 6.6 Some of the process structures: (a) critical dimensions and (b)-(c) alignment
marks.
131
100 m
Fig. 6.7 Micrograph of the fabricated test integrated chip (Optical: 200).
132
Drain
Drain
Gate
Gate
P-pillar Trench
Source
(a)
P-pillar Trench
Source
(b)
Fig. 6.8 Top-view of SJ-FINFET device: (a) a layout and (b) a corresponding fabricated
structures.
P-pillar Trench
Poly-Si: Trench Gate
Source
Trench
Ldrift
Drain
Trench
(b)
Fig. 6.9 SEM images of fabricated SJ-FINFET: (a) a transistor array and (b) a crosssection after Al and oxide etchings.
The threshold voltage was extracted by extrapolating the linear region on the Ids-Vgs
plot. Fig. 6.10 presents the transfer characteristic of the fabricated SJ-FINFET device
with Ldrift = 3.5 m and W = 200 m at Vgs = 0.1 V. The measured threshold voltage of
the SJ-FINFET was approximately 180 mV, which is in good agreement with the
previous device simulation result of the SJ-FINFET (see Fig. 5.12). Also, the drain to
source current Ids was found to be saturated for larger gate to source voltages. This
indicates that at high vertical field strengths (i.e. Vgs/tox), the electrons scatter more often
133
in the channel and this electron mobility degradation effect leads to less current than one
expected at high Vgs.
6E-03
Ids (A)
4E-03
3E-03
2E-03
1E-03
VTH ~ 1.75 V
0E+00
0
10
11
12
13
14
15
Vgate (V)
Fig. 6.10 Ids - Vgs transfer characteristic of the fabricated SJ-FINFET at Vgs = 0.1 V.
134
Vds increases. This phenomenon can be understood by taking account of the self-heating
effect. Since the majority of electron current is concentrated near the top surface of ndrift region in the SJ-LDMOSFET, this may lead to the increase in the internal
temperature of the device. On the other hand, the SJ-FINFET employs the triple gate
structure not only to reduce the channel resistance but also to relax the electron current
crowding near the gate edge.
0.10
(a)
0.09
0.08
Vg= 10 V
0.07
Ids (A)
0.06
Vg= 8 V
0.05
Vg= 6 V
0.04
0.03
Vg= 4 V
0.02
0.01
Vg= 2 V
0.00
0
0.5
1.5
2.5
3.5
4.5
Vds (V)
0.10
(b)
0.09
Vg= 10 V
0.08
0.07
Vg= 8 V
Ids (A)
0.06
0.05
Vg= 6 V
0.04
0.03
Vg= 4 V
0.02
Vg= 2 V
0.01
0.00
0
0.5
1.5
2.5
3.5
4.5
Vds (V)
Fig. 6.11Output I-V characteristics of the fabricated (a) SJ-LDMOSFET and (b) SJFINFET devices, Ldrift = 3.5 m and Wtotal = 200 m.
135
Ldrift = 3.5m @ VG = 10 V
1.4
@ DTI=0.8um
@ DTI=1.0um
@ DTI=1.2um
Ron,sp (mcm2)
1.2
1
0.8
0.6
0.4
0.2
0
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Fig. 6.12 The specific on-resistance of the fabricated SJ-FINFETs for different n/p pillar
width ratios and SJ-drift trench (DTI) widths.
136
100
Wside / Ldrift = 2.7m / 6.0m
80
BV (V)
60
40
20
B, 8e13 cm-2, 45keV,
12
3.0E+13
5.0E+13
7.0E+13
9.0E+13
1.1E+14
Fig. 6.13 The relationship between BV and P-pillar dose for the fabricated SJ-FINFET
devices with Ldrift of 3.5 m and 6 m, Wn = Wp = 0.3 m and Wside of 2.7 m.
137
SJ-FINFET @ Vg=8V
SJ-FINFET @ Vg=10V
SJ-LDMOS @ Vg=8V
SJ-LDMOS @ Vg=10V
600
Ron ()
500
400
300
200
100
0
0
25
50
75
100
125
150
175
200
W (m)
Fig. 6.14 On-resistance data comparison as a function of the gate width (W) of the
fabricated SJ-FINFET and SJ-LDMOSFETS, Ldrift = 3.5 m.
The specific on-resistance is plotted as a function of Ldrift in Fig. 6.15. The fabricated
SJ-FINFET images with different Ldrift are shown in Fig. 6.16. The specific onresistances of the fabricated SJ-FINFET devices are 25-33% lower than that of the
fabricated SJ-LDMOSFETs. The Ron,sp is found to increase linearly with a slope of about
1 mcm2/m. However, as the drift length becomes greater than 6 m, the slope begins
to increase significantly. These results suggest that a further optimization of field plate
(F.P) is necessary for drift lengths greater than 6 m.
138
36
2.2
33
2.0
30
1.8
27
1.6
24
1.4
21
1.2
18
1.0
15
0.8
12
0.6
SJ-FINFET @ Vg=10V
0.4
Improvement (%)
Ron,sp (mcm2)
2.4
SJ-LDMOS @ Vg=10V
0.2
Improvement @ Vg=10V
0.0
10
11
12
Ldrift (m)
Fig. 6.15 Ron,sp data comparison between SJ-FINFET and SJ-LDMOS for different Ldrift.
Ldrift = 3.5 m
Ldrift = 6.0 m
(a)
Ldrift = 10.0 m
G
(b)
Ldrift = 12.0 m
G
(c)
S
(d)
Fig. 6.16 Micrographs of the SJ-FINFETs with different drift lengths: (a) Ldrift = 3.5 m,
(b) Ldrift = 6.0 m, (c) ) Ldrift = 10.0 m and (d) ) Ldrift = 12.0 m for Wtotal = 200 m.
139
1.4
Other published data
[114]
Simulated SJ-FINFET
1.2
Fabricated SJ-FINFET
Ron,sp (mcm2 )
Fabricated SJ-LDMOS
[113]
[104]
[102]
Fabricated
SJ-LDMOS
0.8
0.6
Fabricated
SJ-FINFET
[102]
0.4
[111]
Si[104]
Limi [112]
t
[103]
Simulated
SJ-FINFET
0.2
Si-Limit
0
0
20
40
60
80
100
120
140
BV (V)
Fig. 6.17 Performance comparison between the fabricated SJ-devices and previously
published data. Data from [102], [104], [114] are for conventional LDMOSFETs. Data
from [103], [111]-[113] are for conventional SJ-LDMOSFETs.
140
6.5 Summary
A novel lateral SJ-FINFET device, which employs a corrugated 3-D trench gate
structure with heavily doped alternating U-shaped n/p pillars was fabricated and
measured for next generation of sub-100V applications. The SJ-FINFET fabrication
required a total of nine masking layers and the process steps were compatible with a
standard 0.5m CMOS flow. To realize the SJ-FINFET, new optional process modules
were developed that can be added to the baseline CMOS technology. The inclusion of
these modules had no significant impact on the overall processing cost. The performance
advantage of the SJ-FINFET over the conventional planar gate SJ-LDMOSFET was
verified experimentally. The measured BV-Ron,sp trade-off relationships was comparable
with other published LDMOS transistors and it also demonstrated a good agreement in
the data trend between the simulation and measurement. For the similar BV ratings, the
specific on-resistances of the fabricated SJ-FINFET devices were 29-33% lower than that
of the fabricated SJ-LDMOSFETs. It is noted that there are no dynamic test results. This
was due to the fact that the test structures are too small to be able to extract the gate
charge. Nevertheless, the current work represents the first experimental confirmation that
the super-junction concept is advantageous for sub-100V applications. We believe that a
fabrication process with finer photolithography (i.e. better than the 0.5m used in this
work) and better control of the doping concentrations in the n+/p+ pillars will produce
even more encouraging performance.
141
Chapter 7
Conclusions
In this thesis, the development and experimental verification of the next generation
low-voltage power MOSFETs have been described. In the first part of the thesis, the
feasibility of monolithic integration of a high speed, high efficiency buck converter was
investigated in terms of the layout optimization. In particular, the unit-cell structure of the
hybrid waffle (HW) layout, implemented in a 0.25m, 5 metal layer standard CMOS
process was optimized for minimum specific on-resistance with enhanced switching
characteristics. Analytical layout models containing parasitic resistors and capacitors
were proposed. This allowed more accurate power loss calculations for the final output
stage design. The HW layout technique organized MOSFET fingers in a square grid
arrangement. It was designed to provide an effective trade-off between the width of
diagonal source/drain metal and the active device area, allowing more effective
optimization between switching and conduction losses. In comparison with conventional
layout schemes, the HW layout was found to exhibit a 30% reduction in overall onresistance with 3.6 times smaller total gate charge for CMOS devices with a current
rating of 1A. The performance improvement was obtained with no processing or device
structural changes. The measured overall on-resistances for both the n- and p-type HW
power MOSFETs were in good agreement with the simulation results. Also, the
maximum measured efficiencies of the converter switching at 6.25 MHz and 10MHz
were 85% and 82%, respectively.
The focus of the second part of this thesis was to explore the suitability of the superjunction (SJ) concept in low voltage power MOSFETs. Conventional SJ devices do not
have significant advantages over LDMOS devices in sub-100V rating applications. This
is due to the fact that the channel resistance becomes comparable to the drift region
resistance. A lateral super-junction FINFET (SJ-FINFET) with a corrugated 3-D trench
gate was presented to resolve this issue. Using highly doped alternating ultra thin n/p
pillars (the FINs) as the SJ drift region, the proposed devices could provide a new degree
of freedom in the trade-off between on-resistance and breakdown voltage. Threedimensional numerical simulations using ISE-DESSISTM was performed to analyze the
142
effect of various device parameters. Several prototype devices were fabricated in a 0.5m
CMOS process with nine masking layers. In comparison with conventional planar gate
SJ-LDMOSFETs, the fabricated SJ-FINFETs demonstrated approximately 30%
improvement in Ron,sp. This is a positive indication that the SJ-FINFET can become a
competitive power device for sub-100V applications. Further process and parasitic
optimizations with a deeper trench gate structure and finer lithography resolution will
lead to a better performance and may overcome the ideal Si limit of BV and Ron,sp.
Future work may take advantage of new developments in interconnects and contact
processes by incorporating Cu interconnects to reduce de-biasing effects and make use of
borderless contacts to increase the packing density. Consideration can be also given to
reduce the gate resistance using special silicide materials and new layout techniques to
further reduce the chip area for a given current carrying capability. Other future work
may consider modifying the existing process flow of the SJ-FINFET to achieve better
control of the doping concentrations between the pillars. In addition, the fabrication
process of the SJ-FINFET with finer photolithography should be considered in
combination with the HW layout strategy.
143
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153
154
155
156
Ids
Ids
Vds
Vds
D
Vg
G
Vg
CMOS-based
Power NMOS
CMOS-based
Power PMOS
GND
GND
Vds = Measured
Vds = Measured
157
B.
constant current (Id1) to DUT, the value of Vg1 is first extracted through a parametric Vds
vs. Ids plot to determine the gate voltage at which the current through the MOSFET is
equal to 100/400/800mA. M1 then acts as a current load to M2 from which we extract the
Qg. It is also noted that M1 and M2 are the same CMOS-based power MOSFET devices.
Vdd
Bias Conditions for NMOS (PMOS)
Id1
M1
Vg1
Vdd = 3.3V(-3.3V)
Vds
Vg2
Ig
DUT
Id2
Ig = 1.1mA (-2.2mA)
Period = 100ns
M2
Therefore, Qg = Ig x time @ Vg2 = 3.3V (-3.3V)
GND
158
C.
Fig. C(a), which was modified from Fig. 13 of [92], by plotting the Vds and Vgs
waveforms. The pre-driver shown in Fig. C(a) was constructed with the gate-driver
design by Marian Chang. The resistance, R, is chosen such that the sum of R and R on
(extracted in part A) will force a current of 400mA to pass DUT when it is turned on Fig.
C(b) also shows how the delays are defined [92].
(a)
Vds
Vdd GND
Pre-driver
Vdd
Vgs
Ids
DUT
Vg
GND
Bias Conditions for NMOS (PMOS)
(b)
-
Period = 100ns
Fig. C. Turn-on and turn-off delay extraction circuit from Cadence schematic.
159
Process
Alignment Mark
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.10
0.11
0.12
0.13
0.14
0.15
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
Sulfuric clean
HF dip
DI rinse / Spin dry
Photoresist coating
Pre-bake
Photoresist exposure
Soft-bake
Photoresist develop
Hard-bake
Descum
Inspection
Silicon plasma etch
Photoresist O2 ashing
Photoresist acid strip
Inspection
Equipment
Requirements
120C, 10min
1min
4 cycles
Program 1-4-7, P/R=1075
90C, 1min
Energy: 350 (i-line)
110C, 1min
Program 1-7
120C, 10min
2min
Check the mask pattern
Etch = 120nm
20min
120C, 10min, P/R inspect
Depth measurement
120C, 10min
1min
4 cycles
300, 950C
2500 , 780C
Program 1-4-7, P/R=1075
90C, 1min
Energy: 350 (i-line)
110C, 1min
Program 1-7
120C, 10min
2min
End-point detection
Step-thickness
10% over-etch
Step-thickness
S011, Etch = 3.6m, 70 cycles
Step-thickness
20min
120C, 10min, P/R inspect
120C, 10min
1min
4 cycles
500 , 1000C
4.5m, 425C, 115 /min,
O2:50 sccm SiH4: 40 sccm
Active / Isolation
Sulfuric clean
HF dip
DI rinse / Spin dry
Pad oxide growth
Nitride Deposition
Photoresist coating
Pre-bake
Mask #1: Active
Soft-bake
Photoresist develop
Hard-bake
Descum
Nitride Etch
Inspection
Oxide Etch
Inspection
Deep-Si Etch
Inspection
Photoresist Ash
Photoresist acid strip
Sulfuric clean
HF dip
DI rinse / Spin dry
Liner Oxidation
Isolation Oxide Depo.
160
Step
No.
1.26
1.27
1.28
1.29
1.30
1.31
DTI Densification
CMP: Planarization
Post-CMP Cleaning
LTO Dry-etch
LTO Wet-etch
Nitride Removal
D4: Annealing
CMP1: Strasbaugh 6EC
CMP2: USI wafer washer
AME-8110 Etcher: P3
WET-A2: HF:H20 (1:50)
WET-C1: Nitride Strip
1.32
1.33
Process
Equipment
Requirements
900C, 30min
4.0m removal
DI wafer
Etch: 4000
Etch: 1000 , 16min
H3PO4 @ Temp=165C,
Selectivity: Si3N4:LTO > 25
25C, 5min
4 cycles
PBODY: P-Body
2.1
2.2
2.3
2.4
Sulfuric clean
HF dip
DI rinse / Spin dry
Sacrificial Oxidation
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
2.25
Nitride Deposition
Photoresist coating
Pre-bake
Mask #2: PBODY
Soft-bake
Photoresist develop
Hard-bake
Descum
Nitride Etch
Inspection
Oxide Etch
Inspection
Deep-Si Etch
Inspection
Photoresist Ash
Photoresist acid strip
Sulfuric clean
HF dip
DI rinse / Spin dry
Inspection
Tilted Implant: 45deg.
2.26
Nitride Removal
2.27
2.28
2.29
2.30
2.30
P-body diffusion
LTO Gap-Filling
D4: Annealing
B4: CVD Furnace LTO
2.31
2.32
2.33
2.34
LTO Densification
CMP: Planarization
Post-CMP Cleaning
LTO Dry-etch
D4: Annealing
CMP1: Strasbaugh 6EC
CMP2: USI wafer washer
AME-8110 Etcher: P3
120C, 10min
1min
4 cycles
250 , 850C, 10min, 950C,
35min
4000 , 780C
Program 1-4-7, P/R=1075
90C, 1min
Energy: 350 (i-line)
110C, 1min
Program 1-7
120C, 10min
2min
End-point detection
Step-thickness
10% over-etch
Step-thickness
S011, Etch = 2.2um, 36 cycles
Step-thickness
20min
120C, 10min, P/R inspect
120C, 10min
1min
4 cycles
Cross-section by test wafer #1.
Species=Boron,
Energy(keV)=180,
Dose(/cm2)=2.2E14, Tilt=45deg
H3PO4 @ Temp=165C,
Selectivity: Si3N4:LTO > 25
5min, 25C
4 cycles
250A, 850C, 10min, 950C,
35min,
950C, 10min, 1050C, 45min
3.0m, 425C, 115 /min,
O2:50 sccm SiH4: 40 sccm
850C, 10min, 900C, 30min
2.5um LTO removal
DI wafer
Etch: 5000
161
Step
No.
2.35
3
Process
LTO Wet-etch
Equipment
Requirements
SJ-drift
3.1
3.2
3.3
3.4
Sulfuric clean
HF dip
DI rinse / Spin dry
Sacrificial Oxidation
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
Nitride Deposition
Photoresist coating
Pre-bake
Mask #3: IP
Soft-bake
Photoresist develop
Hard-bake
Descum
Nitride Etch
Inspection
Oxide Etch
Inspection
Deep-Si Etch
Inspection
Photoresist Ash
Photoresist acid strip
Sulfuric clean
HF dip
DI rinse / Spin dry
Inspection
Tilted Implant: 2 x L/R
and 2 x T/B
3.25A
3.26
LTO Gap-Filling
3.27
3.28
3.29
3.30
3.31
3.32
LTO Densification
CMP: Planarization
Post-CMP Cleaning
LTO Dry-etch
LTO Wet-etch
Nitride Removal
D4: Annealing
CMP1: Strasbaugh 6EC
CMP2: USI wafer washer
AME-8110 Etcher: P3
WET-A2: HF:H20 (1:50)
WET-C1: Nitride Strip
3.33
3.34
120C, 10min
1min
4 cycles
250, 850C, 5min, 950C,
35min, 850C, 5min
5000 , 780C, 8Hrs
Program 1-4-7, P/R=1075
90C, 1min
Energy: 320 (i-line)
110C, 1min
Program 1-7
120C, 10min
2min
End-point detection
Step-thickness
10% over-etch
Step-thickness
S011, Etch = 2.2m, 36 cycles
Step-thickness
20min
120C, 10min, P/R inspect
120C, 10min
1min
4 cycles
Cross-section by test wafer #2.
Species=Boron,
Energy(keV)=80/45,
Dose(/cm2)=3.5E13/2,4,6,and
8E13, Tilt=45deg / 12deg
200, 850C, 10min, 950C,
20min,
3.0m, 425C, 115 /min,
O2:50 sccm SiH4: 40 sccm
850C, 10min, 900C, 20min
2.5m removal
DI wafer
Etch: 5000
Etch: 1000 , 16min
H3PO4 @ Temp=165C,
Selectivity: Si3N4:LTO > 25
25C, 5min
4 cycles
120C, 10min
1min
4 cycles
Program 1-4-7, P/R=1075
90C, 1min
4
4.1
4.2
4.3
4.4
4.5
Trench Gate
Sulfuric clean
HF dip
DI rinse / Spin dry
Photoresist coating
Pre-bake
162
Step
No.
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
Process
Equipment
Requirements
4.21
4.22
4.23
Amorphous-Si
deposition (In-situ)
Gate Transformation to
Poly-Si
Photoresist coating
Hard-bake
Backside Poly-Si Etch
4.24
4.25
4.26
4.27
4.19
4.20
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
6
Gate Poly
Photoresist coating
Pre-bake
Mask #5: POLY1
Soft-bake
Photoresist develop
Hard-bake
Descum
Poly-Si Etch
Photoresist Ash
Photoresist acid strip
Sulfuric clean
HF dip
DI rinse / Spin dry
Inspection
Inspection
N+ Source
6.1
Sacrificial Oxidation
6.2
6.3
6.4
6.5
6.6
Nitride Deposition
Photoresist coating
Pre-bake
Mask #2: PBODY
Soft-bake
163
Step
No.
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
Photoresist develop
Hard-bake
Descum
Nitride Etch
Inspection
Oxide Etch
Inspection
LTO Etch
Inspection
Photoresist Ash
Photoresist acid strip
Tilted Implant: 45deg.
6.19
6.20
LTO Gap-Filling
6.21
6.22
6.23
6.24
6.25
6.26
6.27
6.28
LTO Densification
CMP: Planarization
Post-CMP Cleaning
LTO Dry-etch
LTO Wet-etch
Sulfuric clean
HF dip
DI rinse / Spin dry
D4: Annealing
CMP1: Strasbaugh 6EC
CMP2: USI wafer washer
AME-8110 Etcher: P3
WET-A2: HF:H20 (1:50)
WET-A1: Standard Clean
WET-A2: HF:H20 (1:50)
DI rinse, Spin dry-1 and -2
Process
Equipment
N+ Drain
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
Photoresist coating
Pre-bake
Mask #6: NIMP
Soft-bake
Photoresist develop
Hard-bake
Descum
Oxide Etch
Inspection
Deep-Si Etch
Inspection
Tilted Implant: -45deg.
7.13
7.14
7.15
7.16
7.17
7.18
Photoresist Ash
Photoresist acid strip
Sulfuric clean
HF dip
DI rinse / Spin dry
Trench Ox. Liner
IPC-4000 O2 Asher
WET-E4: Resist Strip
WET-A1: Standard Clean
WET-A2: HF:H20 (1:50)
DI rinse, Spin dry-1 and -2
D1: Dry Oxidation
7.19
LTO Gap-Filling
7.20
LTO Densification
D4: Annealing
Requirements
Program 17
120C, 10min
2min
End-point detection
Step-thickness
10% over-etch
Step-thickness
Etch = 1.8um
Measure the LTO thickness
20min
120C, 10min, P/R inspect
Species=Phosphorous,
Energy(keV)=180,
Dose(/cm2)=7E14, Tilt=45deg
200, 850C, 10min, 950C,
20min,
3.0m, 425C, 115 /min,
O2:50 sccm SiH4: 40 sccm
850C, 10min, 900C, 20min
2.5m removal
DI wafer
Etch: 4000
Etch: 1000 , 16min
120C, 10min
1min
4 cycles
164
Step
No.
7.21
7.22
7.23
Process
Requirements
1000C, 15min
1.0m removal
DI wafer
Photoresist coating
Pre-bake
Mask #7: PIMP
Soft-bake
Photoresist develop
Hard-bake
Descum
LTO Etch
Photoresist Ash
Photoresist acid strip
Sulfuric clean
HF dip
DI rinse / Spin dry
Inspection
HF dip (optional)
Ion Implant: default
8.16
8.17
LTO Gap-Filling
8.18
8.19
8.20
LTO Densification
CMP: Planarization
Post-CMP Cleaning
D4: Annealing
CMP1: Strasbaugh 6EC
CMP2: USI wafer washer
Thickness = 1m,
Rate = 18.2nm/sec.
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.14A
8.15
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
9.14A
9.14B
10
10.1
S/D Annealing
CMP: Planarization
Post-CMP Cleaning
Equipment
P+ Contact
Contact Openings
Photoresist coating
Pre-bake
Mask #8: CONT
Soft-bake
Photoresist develop
Hard-bake
Descum
LTO Etch
Photoresist Ash
Photoresist acid strip
Sulfuric clean
HF dip
DI rinse / Spin dry
Inspection
HF dip (optional)
Inspection (optional)
Metallization
Al Sputter Deposition
165
Step
No.
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
Electrical Test
Process
Equipment
Requirements
4 cycles
Program 1-4-7, P/R=1075
90C, 1min
Energy: 350 (i-line)
110C, 1min
Program 1-7
120C, 10min
2min
Cross-section by test wafer #5.
Etch = 1m, Rate = 150nm/min
Step and Oxide Thickness
4 cycles
20min
P/R removal inspect
4 cycles
Time=30min, Temp=400C,
N2:H2=20:1
166
List of Publication
Journal and Conference Papers
Patents
A. Yoo, H.S. Kang, and H.J. Shin, Shared Contact Structure Having Corner
Protection Pattern, Semiconductor Devices, and Methods of Fabricating the Same,
US Patent Application No. US11/377,455, March 17, 2006.
167