Digital Electronics Lab Manual

EXPERIMENT NO: 1
VERIFICATION OF TRUTH TABLES OF DIGITAL ICS

AIM
To study and verify the truth tables of various digital ICs
COMPONENTS AND EQUIPMENTS REQUIRED
ICs 7400, 7402, 7404,7432,7408,7486,7411,7410,7420 and digital IC trainer kit.
THEORY
All ICs given are DIP (dual-in-line package) type and belong to TTL family. Pin no: 14 is
the supply pin and to work properly, supply voltage must be between +4.75V and
+5.25V.This is why +5V is the nominal supply voltage specified for all TTL devices. Pin
no: 7 is the common ground for the chip and the other pins are used for inputs and
outputs.
AND gate (IC 7408)
The AND gate performs logical multiplication more commonly known as AND
operation. The AND gate output will be high only if all inputs are high. IC7408 contains
four, two-input AND gates (quad two input AND gates).
OR gate (IC 7432)
OR gates perform logical addition. Output will be high if and only if any of the input
becomes high.7432 is a quad two input OR gate.
NOT gate (IC 7404)
It performs a basic logic function called inversion or complement.IC7404 is a Hexinverter (6-in-1 inverter).
Digital Electronics lab manual

NAND gate(IC 7400)
AND gate followed by NOT gate is a NAND gate. Its output will be low if only all the
inputs are in high state. IC 7400 is a quad two input NAND gate.
NOR gate (IC 7402)
A NOR gate is an OR gate followed by a NOT gate.. Its output is low if any of the inputs
is high.7402 is a quad two neither input NOR gate.
NAND and NOR gates are called universal gates.
XOR gate(IC 7486)
Output will be high if and only if one input is in high state. 7486 is a quad two input
XOR gate.
IC 7411 is three-input AND gates, 7410 is three input NAND gate and
7420 is four-input NAND gate.
PROCEDURE
1. Check all the components and IC packages using multimeter and digital IC tester.
Also assure whether all the connecting wires are having continuity using 5V supply and
LEDs of IC trainer kit itself.
2. Place the ICs properly on the bread board.
3. Connect pin14 to power supply and 7 to ground for each IC.
4. Select good logic input switches to provide inputs for the gates and output lines to
monitor the outputs.
5. Provide the possible combinations (as in truth table) using logic switches. Check the
output in each case. The LED indicator connected to the output terminal should glow
indicating a HIGH level at the output and should not glow indicating a LOW level.
VIET
RESULT
The various digital IC packages are studied and their truth tables are verified.
VIET

1) Quad two input AND gates IC 7408
Pin lay-out
Symbol
Truth Table
A
0
0
1
1
B
0
1
0
1
Y
0
0
0
1
2) Quad two input OR gates IC 7432

Pin lay-out
Symbol
Truth Table
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
1
3) Hex inverter gates -IC7404

Pin lay-out
Symbol
Truth Table
A
0
1
Y
1
0
4) NAND gates- IC 7400
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Pin lay-out
Symbol
Truth Table
5) NOR gates-IC 7402

Pin lay-out
Symbol
Truth Table
A
0
0
1
1
6) XOR gate- IC 7486

Pin lay-out
Symbol
B
0
1
0
1
Y
1
0
0
0
Truth Table
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
0
EXPERIMENT NO: 2
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CHARACTERISTICS OF TTL
AIM
To find the transfer characteristics of TTL gates.
COMPONENTS AND EQUIPMENTS REQUIRED
IC 7400, voltmeter and trainer kit
THEORY
Internal circuit diagram of a basic TTL NAND gate is shown in fig(1). If any of the
input is low level, the output will be in high level.
Transfer Characteristics
If any input of a NAND gate is low, Q2 & Q3 will be turned OFF and Q4 will be
turned ON to give a logic 1 output. Then Vo will be having a value Vcc-( VBE + VD )
where VBE is the base emitter potential of transistor and VD is the diode voltage drop
collector potential of Q2 is Vcc through R1 and base emitter of Q1.
If input voltage Vi is raised generally, current gets diverted from the emitter of Q1
to its collector causing Q2 to conduct. Q2 is then operates in its linear region with a gain
R2/R3. Since Q4 remains ON and acts as an emitter follower, the output decreases at a rate
ot 1.6, when the input of Q2 fall drastically, then output falls with a steep slope.
Logic swing and Transition width
These two quantities are given by the expression
Logic swing
= VOH VOL
Transition width = VIH VIL
Noise Margin
It is an amount of noise voltage that an input can tolerate without causing a false
change in input state. Noise margin at high level are given by the expressions below.
NMH = VOH VIH
NML = VIL VOL
VIET
PROCEDURE
1. Check all the components and IC packages using multimeter and digital IC tester
2. Set up the circuit to measure sourcing current. Ensure that the gate output is in
logic 1. Take the reading from the ammeter.
3. Set up the circuit to measure sinking and sourcing current. Ensure that the gate
output is in logic 0. Take the voltmeter readings. Draw the characteristics with Vi on
X-axis Vo on Y- axis.
4. To display transfer characteristics on CRO, Feed a 5V wave form to the input of the
gate. Fed the signal to the channel A and B.
RESULT
The transfer characteristics of TTL gate were obtained.
VIET
Vcc
+V
R2
R4
Q4
R1
Vi
NPN
Q2
Vo
Q3
R3
INTERNAL CIRCUIT DIAGRAM 1
5V
+ Vi
0-5V
-
+ Vo
0-5V
-
Circuit diagram 1
VIET
Vi
Vo
EXPERIMENT NO: 3
VIET
VERIFICATION OF DE MORGANS THEOREM AND

POSTULATES OF BOOLEAN ALGEBRA
AIM
To verify De Morgans theorem and postulates of Boolean algebra, using Logic
gates.
COMPONENTS REQUIRED
IC Trainer Kit, IC 7400, IC7432, IC 7402, IC 7408, IC 7404.
THEORY
De Morgans theorem
De Morgans theorem states that,
(i) The complement of a sum equals the product of the complements
(A + B) = A. B .eqn(i)
(ii)
The complement of a product equals the sum of the complements.

(A. B) = A + B
.eqn(ii)
Postulates of Boolean algebra
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10

1. Commutative law
A+ B = B + A .eqn(iii)
A. B = B. A .eqn(iv)
2. Associative law
A + (B + C) = (A + B) + C .eqn(v)
A. (B .C) = (A .B) .C
.eqn(vi)
3. Distributive law
A. (B +C) = A. B + A. C .eqn(vii)
A + (B .C) = (A + B). (A + C .eqn(viii)
4. Complimentary law
A + A = 1
A. A = 0
.eqn(ix)
.eqn(x)
PROCEDURE
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11
1) Make sure that the functional units of the IC trainer kit are working properly
2) Test and ensure that all the selected logic gates in the component ICs are good.
3) Construct the truth table for the logic expressions as stated by the eqns ( i through
xiv)
4) Realize the expressions as stated by the equations ( i through xiv) using suitable
logic gates[for
eqns. i through viii realize the LHS and RHS simultaneously from
the same input lines].

5) Try the different possible combinations of the input and verify the output in each
case with the help of the truth table.
RESULT
Studied and verified De Morgans theorem and postulates of Boolean algebra.
REALIZATION OF LOGIC EQNS. AND CORRESPONDING TRUTH TABLES
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12

De Morgans theorem
(A + B) = A. B eqn(i)
A
( A . B) = A + B ..eqn(ii)
(A+B)'
(A.B)'
A'.B'
(A+B)
A.B
0
0
1
1
0
1
0
1
1
1
0
0
1
0
1
0
1
0
0
0
1
0
0
0
A'+B'
0
0
1
1
0
1
0
1
(A.B)
1
1
1
0
(A+B)
1
1
0
0
1
0
1
0
1
1
1
0
Postulates of Boolean algebra

1. Commutative law
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13
A+ B = B + A .eqn(iii)
A
A . B = B. A eqn(iv)
A+B
B+A
B
A
A+B
B+A
0
0
1
1
0
1
0
1
0
1
1
1
0
1
1
1
A.B
B.A
A.B
B.A
0
0
1
1
0
1
0
1
0
0
0
1
0
0
0
1
2. Associative law
A + ( B + C ) = ( A + B ) + C eqn(v)
A
A .( B .C ) = (A .B ) .C ..eqn(vi)
A
C
A+B
C
A.B
A+(B+C)
A+(B+C)
(A+B)+C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
VIET
(A.B).C
B.C
B+C
A.(B.C)
(A+B)+C
A.(B.C)
(A.B).C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
14
3. Distributive law
A. (B +C) = A. B + A. C .eqn(vii)
A
A + ( B .C ) =( A + B ). (A + C) .eqn(viii)
A.(B+C)
A+(B.C)
B+C
B.C
A.B
A+B
(A.B)+(A.C)
A.C
A(B+C)
AB+AC
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
(A+B).(A+C)
A+C
A+(BC)
(A+B)(A+C)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
4. Complementary law
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15

A + A = 1
A. A = 0
0 1
1 0
A
0 1
1 0
AA
0
0
A+A
1
1
5. Identity law
A .1 = A
A+0=A
A
0
A A.1
0 0
1 1
A A+0
0 0
1 1
6.Idempotent law
A+ A= A
A A+A
0 0
1 1
VIET
A. A=A
A A.A
0 0
1 1
16
EXPERIMENT NO: 4
REALISATION OF LOGIC GATES USING UNIVERSAL

GATES (NAND/NOR)
AIM
To realize all the logic gates using universal gates (NAND/NOR)
COMPONENTS REQUIRED
1) IC Trainer Kit
2) IC 7400-NAND: 2 nos
3) IC 7402 NOR: 2nos
THEORY
Logic gates are the fundamental building blocks of digital systems. A gate is a digital
circuit with one or more input and having only one output. The two universal gates are
NAND & NOR which can perform all the three basic logic functions. Basic logic gates are
AND, OR & NOT which can be derived from universal gates .Moreover XOR & XNOR can
also be derived using these gates .Hence they are called as universal gates.
NOR gate: NOR gate is a combination of NOT & OR. Here the output of OR gate is
NOT ed .The Boolean expression for a NOR gate is
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17

Y= (A+B)
NAND gate: NAND gate is a combination of NOT & AND gate. In this case the output
of AND gate is NOT ed .The Boolean expression representing the NAND operation is
Y= (A.B)
PROCEDURE
1. Verify whether all the components and wires are in good condition.
2. Place the ICs on the trainer kit and make sure that the seventh pin is connected to
ground and 14th to Vcc.
3. Set up the ckt and feed the i/p combinations
4. Observe the o/p corresponding to the i/p applied
5. Verify the corresponding truth table for i/p o/p relationship.
6. Repeat the above for all the ckts
RESULT
All the logic gates were realized using the universal gates (NAND/NOR).
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18
LOGIC GATES USING NAND

TRUTHTABLE
a)NOT
1
b)AND
A
B
1
2
1
1
0
1
0
1
c)OR
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19
10
4
d)NOR
1
10
4
12
11
13
e)XOR
4
A
B
12
13
2
9
8
10
VIET
11
20
f)XNOR
4
6
5
A
B
1
2
12
3
13
9
10
VIET
1
11
2
21
LOGIC GATES USING NOR

TRUTH TABLE
CIRCUIT DIAGRAM
a)NOT
A
2
b)OR
A
0
1
1
0
1
1
c)AND
3
8
9
5
6
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10
22

d)NAND
2
3
8
10
13
12
9
6
11
e)XOR
8
10
9
2
2
3
11
13
12
f)XNOR
11
13
12
2
1
8
9
5
VIET
3
10
5
6
23

EXPERIMENT NO: 5
ARITHMETIC LOGIC CIRCUITS-HALF ADDER

& FULL ADDER
AIM
To realize half adder and full adder using
a) XOR and NAND gates
b) NAND gates alone
COMPONENTS REQUIRED
IC 7400 -NAND : 3 nos
IC 7486 XOR :1 no:
THEORY
Half adder is a circuit used for adding 2 bits. The sum and the carry will be present at
the output. There are two inputs to the full adder A & B.The full adder will also
produce a sum and carry at the output.
From the K-mp it is clear that, the equation for sum of half adder is,
S= AB+AB
The expression for carry-out of a half adder is,
C= AB
The expression for the sum of full adder is
The expression for carry-out of a full adder is,
PROCEDURE
1. Obtain and verify the components
2. Set up the circuits using 7486 and 7400 ICs
3. Provide the inputs and verify the outputs.
RESULT
The circuits for half adder and full adder using X-OR and NAND gates were
designed and verified the truth table.
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24
HALF ADDER
TRUTHTABLE
K-MAP
a)FOR SUM
A 0
1
B
CARRY
S=AB'+A'B
=A+B
USING X-OR & NAND

A
B
A
B
0
1
b)FOR CARRY
0
1
0
C=AB
S=A+B
C=A.B
USING NAND ONLY

4
5
1
12
S=A+B
13
9
11
10
C=A.B
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25
FULL ADDER
K-MAP
TRUTH TABLE
a)FOR SUM
A
Cin
Cout
A
B
AB 00
Cin
0
1
01
11
10
b)FOR CARRY
AB 00
Cin
0
01
11
10
3
4
Cin
2
5
3
9
10
USING NAND ONLY

4
A
B
1
2
12
3
9
10
13
11
1
6
5
12
11
13
2
9
Cin
10
Cout
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26

EXPERIMENT NO: 6
ARITHMETIC LOGIC CIRCUITS-HALF SUBTRACTOR & FULL

SUBTRACTOR
AIM
To realize half subtractor and full subtractor using
a) XOR and NAND gates
b) NAND gates alone
COMPONENTS REQUIRED
IC 7400 -NAND : 3 nos
IC 7486 XOR : 1 no:
THEORY
Half subtractor is a circuit used for subtracting 2 bits. The difference and
borrow will be present at the output. There are two inputs to the full subtractor A & B.
The full subtractor will also produce a difference and
borrow at the output.
From the K-map it is clear that, the equation for difference of half subtractor is,
D = AB+AB
The expression for borrow of a half subtractor is,
Bo = AB
The expression for the difference of full subtractor is
The expression for the borrow of full subtractor is
PROCEDURE
1. Obtain and verify the components
2. Set up the circuits using 7486 and 7400 ICs
3. Provide the inputs and verify the outputs.
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27
RESULT
The circuits for half subtractor and full subtractor using X-OR and NAND
gates were designed and verified the truth table.
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28
HALF SUBTRACTOR
K-MAP
A
a)DIFFERENCE
Bo
A
B
0
b)BORROW OUT
A
B
0
1
D=AB'+A'B
Bo=A'B
a)USING X-OR AND NAND

1
A
B
2
4
10
Bo
b)USING NAND ONLY

4
A
B
12
11
13
8
10
1
2
VIET
4
5
8
10
Bo
29
FULL SUBTRACTOR
K-MAP
FOR DIFFERENCE
AB 00
01
10
Cin
0
1
0
0
TRUTH TABLE
A
Cin
Bo
11
1
D=A+B+Cin
FOR BORROW OUT
AB 00
Cin
0 0
1
01
10
11
Bo=A'B+Cin(A+B)
USING X-OR AND NAND
B
Cin
A
2
5
9
6
10
8
12
13
Bo
11
USING NAND ONLY

4
A
B
12
11
10
VIET
5
3
Cin
13
1
2
6
12
9
10
13
11
8
1
Bo
30

EXPERIMENT NO: 7
FOUR BIT BINARY ADDER, SUBTRACTOR & BCD

ADDER
AIM
To design and setup the following arithmetic circuits using IC 7483

a) 4 bit binary adder
b) 4 bit binary substractor
c) BCD adder
COMPONENTS REQUIRED
a) IC Trainer kit
b) ICs 7483,7486(EXOR) and 7400(NAND)
THEORY
Adder circuits are used to add binary numbers. A 4bit binary adder adds two four
bit numbers and gives the result in another four bit format. A carry will also be produced.
In 7483 IC A3, A2, A1, A0) constitute the first bit and B3, B2, B1, B0 constitute the second
bit. The output is given by S3, S2, S1, S0.
A four bit binary adder/subtractor works on the select input. If S= 0, the circuit
will acts as an adder. If S= 1, the circuit will acts as a subtractor. This is provided by
EX-OR . As the input of all the EX-OR gates are provided with one high input, it will just
compliment the other input given to the gate. Here we use 1s complement subtraction.
The inputs to ICs are the ones complement of the input that we give. If carry is
generated, it will add around to the output. If zero is generated the number will be
negative.
BCD adder is used to add two BCD numbers. Here two BCD numbers are given as
input. A decoding circuit is also used. In case of carry the decoding circuit will provide an
output 1.So the out put adder will be added with 6. So the corresponding BCD will b get
at the output of second flip-flop along with carry.
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31

PROCEDURE
1) Verify whether all the components and wires are in good condition.
2) Place the ICs on the trainer kit and make sure that the pins are properly
connected to Vcc and ground.
3) Set up the circuits and by few input condition, verify the working of the
circuits.
4) Set up the adder/ subtractor circuit, by making sum = 0, and check whether it
works as adder and subtractor when sum = 1
RESULT
Designed and setup the following arithmetic circuit
a) 4- bit binary adder
b) 4-bit binary subtractor
c) BCD adder
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32
Single Digit BCD Adder
A3A2A1A0
+5V
1 3 8 10
B3
16
B2
B1
B0
11
13
7483
15
1 3 8 10
Vcc
16 4
11
13
Cin
5
7483
14
Cout
15 2 6 9
S3S2S1S0
4 Bit Adder/Subtractor Circuit

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33
EXPERIMENT NO: 8
MULTIVIBRATORS USING GATES

AIM
To design and setup an astable multivibrator and monostable multivibrator
using logic gates.
COMPONENTS REQUIRED
IC trainer kit, IC 7400, capacitors and resistors.
THEORY
Astable multivibrator
Here the output switches between two unstable states. Refer the circuit. In one
state Vo1 is high and Vo2 is low and vice versa in other state. Consider the moment Vo2 is
high. Capacitor C1 starts charging through R1.When voltage at Vi1 becomes lower than
threshold voltage Vt of the gate, Vo1 becomes high. At the same moment, Vo2 goes low
since the sudden rise of voltage at Vo1 gets transferred to Vi2 by the capacitor C2.Now C2
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34

charges through R2 and when Vi2 becomes less than Vt ,Vo2 becomes high and cycle
repeats.
Time period of output waveform is T= 0.693R1C1+0.693R2C2

If duty cycle of output waveform is 50%, T=1.386RC
Where, R=R1=R2 & C=C1=C2
Monostable multivibrator
Monostable multivibrator has one stable state.When trigger input is applied,it
goes to quasi-stable state ,comes back and settles after designed time period.
In the stable state, the trigger input is held at logic 1 level. A resistor is wired
from the input of the inverter to ground. Now both inputs to NAND gates are at logic 1
and output at logic 0.In this state capacitor is discharged.
When a trigger pulse(logic 0)appears at one input of first NAND gate, output
goes high as inputs are 0 and 1.The capacitor acts as a short circuit for sudden rise of
voltage at the input of the inverter and the output becomes 0.Capacitor suddenly charges
and settles the circuit in stable state after T=0.693RC.
PROCEDURE
1. Setup multivibrator circuits on the bread board after verifying the ICs.
2. Vcc and GND of ICs used must be given properly.
3. In case of monostable multivibrator,feed a pulse train of designed frequency and
amplitude 5V(obtained from the functional generator)at trigger input and observe
the output waveform.
Time period of trigger pulse should be less than the designed time period of
monostable multivibrator.
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35

4. Use potentiometers in place of resistors and observe changes in the waveform.
5. Observe output waveforms at Vo1,Vo2, Vi1 and Vi2.
RESULT
Designed and setup astable and monostable multivibrators using gates for the
desired frequency and output waveforms were plotted.
Design:Frequency = 1 KHz
Duty cycle of waveform=1/3
We have,T= T1+T2=1ms
Since duty cycle=T1/ (T1+T2)= 1/3,we get T1=0.33ms and T2=0.66ms.
T1=0.33ms=0.69R1C1.
T2=0.66ms=0.69R2C2.
Take R1=R2=R.
By considering internal block diagram of TTL NAND gate, voltage developed across R at
logic 0 state should be < Vil=0.7V (il=input low)
Then (Vcc-VBE) R/(R+4K) <Vil
Substituting the values, we get, R < 778
Circuit diagram
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36
Design:Required pulse width T=2RC=1ms

Since (Vcc-VBE)R/(R+4K)< Vil ,
Take R=680.Then C = 0.7F.
Use 1 F
Use a diode to protect the gate from negative voltage.
R= (5V-0.6V)/2mA = 2.2K
Circuit diagram
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37
EXPERIMENT NO: 9
REALIZATION OF RS, T, D, JK& MASTER SLAVE

FLIP-FLOPS USING GATES
AIM
To design and set up the following flip-flops using gates
1. Clocked RS flip flop
2. J-K flip-flop
3. Master Slave J-K flip-flop
4. D flip flop
5. T flip flop
COMPONENTS REQUIRED
1. IC trainer kit
2. IC 7400(2 nos) & 7410 (2nos)
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38
THEORY
Flip flop is the basic building block in any memory systems. Its output will
remain in its state until it is forced to change by some means.
Clocked RS flip-flop: R & S stands for reset and set .There are 4 input combinations
possible at the inputs. But S=R=1 is forbidden since output will be an indeterminate
form. When the flip-flop is switched ON, its output state will be uncertain. When an
initial state is to be assigned, two separate inputs called preset and clear are used which
are active low.
J-K Flip-flop: The indeterminate output state of RS flip-flop is avoided by converting it
into J-K flip-flop. In J-K flip-flop the indeterminate form is changed by the compliment
of previous output.
Master-Slave J-K flip-flop: The race-around condition of J-K flip-flop is restricted in
Master-Slave J-K flip-flop. Racing is the toggling of the output more than once during a
positive clock edge. MS J-K flip-flop is created by cascading two J-K flip-flops. The
clock fed to the first stage eliminates the change of racing. The clock is inverted and fed
to the second stage .This ensures that the slave follows master and eliminates the change
of racing.
D flip-flop: It has only one input referred to as D-input or data input. Its also called delay
input. The input data is transferred to the output after a clock pulse is applied.
T flip-flop: It stands for toggle. The output toggles when a clock pulse is applied, i.e. the
output of T flip-flop changes state for an input pulse. T flip-flop can be derived from J-K
by shorting J & K inputs.
PROCEDURE
1. Test all components and IC packages using multimeter digital IC tester.
2. Place the ICs on the kit and make sure that the Vcc and GND are properly done.
3. Set up the circuit and feed the input combinations
4. Verify the truth table of the circuit by feeding the input bit combinations for SR, JK,
MSJK, D and T flip-flops
RESULT
Designed and set up the following flip-flops using gates
1. Clocked RS flip flop
2. J-K flip flop
3. Master Slave J-K flip-flop
4. D flip flop
5. T flip flop
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EXPERIMENT NO: 10
SHIFT REGISTERS
AIM
To design and set up shift registers in different modes of operation.
COMPONENTS REQUIRED
IC 7404,IC 74OO, IC7432, IC 7408, IC 7474
THEORY & PROCEDURE
Shift registers are a type of sequential logic circuit, mainly for storage of digital data.
They are a group of flip-flops connected in a chain so that the output from one flip-flop
becomes the input of the next flip-flop. Most of the registers possess no characteristic
internal sequence of states. All the flip-flops are driven by a common clock, and all are
set or reset simultaneously.
The basic types of shift registers studied are
Serial in - Serial Out,
Serial in - Parallel Out,
Parallel In - Serial Out,
Parallel In - Parallel Out,
And bidirectional shift registers. .
Serial In - Serial Out Shift Registers
A basic four-bit shift register can be constructed using four D flip-flops, is shown
in fig.1. The operation of the circuit is as follows. The register is first cleared, forcing all
four outputs to zero. The input data is then applied sequentially to the D input of the first
flip-flop on the left (FF0). During each clock pulse, one bit is transmitted from left to
right. Assume a data word to be 1001. The least significant bit of the data has to be
shifted through the register from FF0 to FF3.
In order to get the data out of the register, they must be shifted out serially. This
can be done destructively or non-destructively. For destructive readout, the original data
is lost and at the end of the read cycle, all flip-flops are reset to zero.
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To avoid the loss of data, an arrangement for a non-destructive reading can be
done by adding two AND gates, an OR gate and an inverter to the system. The
construction of this circuit is shown in fig.2
The data is loaded to the register when the control line is HIGH (i.e. WRITE).
The data can be shifted out of the register when the control line is LOW (i.e. READ).
Parallel In - Parallel Out Shift Registers
For parallel in - parallel out shift registers, all data bits appear on the parallel
outputs immediately following the simultaneous entry of the data bits. The circuit ( fig.3)
is a four-bit parallel in - parallel out shift register constructed by D flip-flops.
The D's are the parallel inputs and the Q's are the parallel outputs. Once the
register is clocked, all the data at the D inputs appear at the corresponding Q outputs
simultaneously.
Parallel In - Serial Out Shift Registers
A four-bit parallel in - serial out shift register is shown in fig.4. The circuit uses D
flip-flops and NAND gates for entering data (ie writing) to the register.
D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit
and D3 is the least significant bit. To write data in, the mode control line is taken to
LOW and the data is clocked in. The data can be shifted when the mode control line is
HIGH as SHIFT is active high.
Serial In - Parallel Out Shift Registers
For this kind of register, data bits are entered serially in the same manner as
discussed in the last section. The difference is the way in which the data bits are taken
out of the register. Once the data are stored, each bit appears on its respective output line,
and all bits are available simultaneously. The construction of a four-bit serial in - parallel
out register is shown in fig.5.
Bidirectional Shift Registers
The registers discussed so far involved only right shift operations. Each right
shift operation has the effect of successively dividing the binary number by two. If the
operation is reversed (left shift), this has the effect of multiplying the number by two.
With suitable gating arrangement a serial shift register can perform both operations.
A bidirectional, or reversible, shift register is one in which the data can be shift
either left or right. A four-bit bidirectional shift register using D flip-flops is shown in
fig.6. In fig.6 as you can see, a set of NAND gates are configured as OR gates to select
data inputs from the right or left adjacent bistables, as selected by the LEFT/RIGHT
control line.
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Applications
Shift registers can be found in many applications. Some special applications are listed
below
To produce time delay
The serial in -serial out shift register can be used as a time delay device. The
amount of delay can be controlled by:
1. the number of stages in the register
2. the clock frequency
To simplify combinational logic.
The ring counter technique can be effectively utilized to implement synchronous

sequential circuits. A major problem in the realization of sequential circuits is the
assignment of binary codes to the internal states of the circuit in order to reduce the
complexity of circuits required. By assigning one flip-flop to one internal state, it is
possible to simplify the combinational logic required to realize the complete sequential
circuit. When the circuit is in a particular state, the flip-flop corresponding to that state is
set to HIGH and all other flip-flops remain LOW.
To convert serial data to parallel data
A computer or microprocessor-based system commonly requires incoming data to

be in parallel format. But frequently, these systems must communicate with external
devices that send or receive serial data. So, serial-to-parallel conversion is required. As
shown in the previous sections, a serial in - parallel out register can achieve this.
RESULT
Various shift registers has been set up and modes of data transfer studied in each
case.
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Fig.1 Serial In - Serial Out Shift Register
Fig.2 Serial in - Parallel out Shift Registers
Fig.3. Four-bit parallel in - serial out shift register
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Fig.4 Parallel in - Parallel out Shift Registers
Fig.6 Bidirectional Shift Registers
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EXPERIMENT NO: 11
REALIZATION OF RING, JOHNSON & RIPPLE COUNTERS

AIM
To design and set up the following counters.
1. Ripple counter
2. Johnson counter
3. Ring counter
COMPONENTS REQUIRED
IC 7476, IC 7400& Digital trainer kit
THEORY
Ripple Counter
Asynchronous counters (ripple counters) are those in which all flip flops are not
clocked simultaneously. On the other hand in synchronous counters all the flip flops are
synchronized by providing a common clock pulse.
A group of n flip flops will have 2n states. So it is possible to make a modulo 2 n
counter using n flip-flops. In a 4-bit ripple counter the number of states is 16. The Qo
output of least significant flip flop changes at each clock pulse. This is achieved by using
JK flip-flops(IC 7476 is dual JK master slave flip flop with preset and clear). The counter
gives a natural binary count from 0 to 15 and resets to initial state on 16 th input pulse.
With the application of the first clock pulse Q0 changes from 0 to 1 and Q1, Q2, Q3 remains
unaffected. With the second clock pulse Q 0 becomes 0 and Q1 becomes 1. At the 16th
clock pulse all Q outputs become reset and cycle repeats.
Johnson Counter
If the output Q0 of a shift register is connected to the serial input, the resulting circuit is
referred to as a Johnson Counter. The Johnson counter is a divide by 2N counter.
Ring Counter
If the serial output Q0 of a shift register is connected back to the serial input, then a pulse
will keep circulating. This circuit is referred to as ring counter.
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PROCEDURE
1. Check all the components using IC testers and multimeters. For ripple counter
first clear all the flip-flops by giving signal at the CLEAR input. After clearing,
make the CLEAR pin open. Then apply the monopulse or clock for counting.
2. For ring counter, set up the serial input right shift register, make Q 3Q2Q1Q0=1000
using clear and preset pins. Note down the outputs on the truth table for
successive clocks.
3. For Johnson counter reverse the Q and Q connections of the last flip-flop. First
clear all the flip-flops and then apply the clock pulse and observe the outputs.
RESULT
The following counter circuits were designed and set up
1. Ripple counter
2 .Johnson counter
3 .Ring counter
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EXPERIMENT NO: 12
SYNCHRONOUS COUNTERS
AIM
To design and set up the following counter circuits.
1. Synchronous MOD 10 counter
2. Synchronous UP/DOWN MOD 6 counter
COMPONENTS REQUIRED
ICs 7476, 7400, 7408, digital IC trainer kit etc
THEORY
In synchronous counters all flip-flops are working in synchronism with the input clock
pulse. The additive propagation delay in asynchronous counters in synchronous counters.
If M is the modulus of the counter and N is the minimum number of flip-flops used, then
N=log 2M
DESIGN
For designing the synchronous counter, first write down the counting sequence. If we are
designing the counter using the JK flip-flop, consider the excitation table of JK flip-flop.
Qn represents the state before the clock pulse is applied and Qn+1 represent the state
after the application of pulse. From the excitation table find out the inputs J & K to get
Qn+1(next state) from Qn (present state). The excitation of JK flip-flop is given below
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Excitation table of JK flip-flop
Qn Qn+1 J
Consider the counter sequence. For e.g., let the first state be 0011 (Q 3Q2Q1Q0) and the
next state be 0100.Q3 changes from 0 to 0 (i.e. change).From the excitation table the J 3 &
K3 inputs for this state is obtained as 0X.Similarly Q2 changes from 0 to 1, for this J2 and
K2 inputs are obtained as 1X .Similarly from 1 to 0 J 1 and K1 are X1and from 1 to 0 they
are again X1.In order to find the equation for J and K plot all the combinations in the Kmap. Similarly for all other inputs find out the equations for J & K using K-map. The
excitation table of the MOD 10 counter is shown. The realization of J & K inputs using
K=maps is also shown.
mod 6 up/down counter
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A counter which is capable of counting either UP or DOWN is known as UP/DOWN
counter. Counter counts either up or down according to a mode control input
M=0 or M=1 respectively.
MOD 6 counter has 6 states .But when we are considering both UP and DOWN counting
there are twelve states. Since we are using MOD control M here, M is also a variable in
the K-Map realization.
PROCEDURE
Check all the components and set up the circuit.
Initially clear the flip-flops so that the first output of the counter is 0000.After this, apply
the clock and verify the counter output states for each clock pulse.
RESULT
The following counter circuits were designed and set up.
1. Synchronous MOD 10 counter
2. Synchronous UP/DOWN MOD 6 counter
4 BIT UP COUNTER
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MOD 10 UP Counter
Excitation Table
Counter states
J K flipflop inputs
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
X
1
X
1
X
1
X
1
X
X
1
X
1
X
1
X
1
X
1
0
1
X
X
0
1
X
X
0
0
X
X
0
1
X
X
0
1
X
X
0
0
0
1
X
X
X
X
0
0
X
X
X
X
0
0
0
1
X
X
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
0
1
REALIZATION USING K-MAPS
J1=Q3Q0
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K1=Q0
57
J2=Q0Q1
J3=Q0Q1Q2
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K2=Q1Q0
K3=Q0
58
MOD 6 UP/DOWN COUNTER
J2 = MQ1Q0+MQ1Q0
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K2 = MQ0+MQ0
59
J1 = MQ2Q0+MQ2Q0
J0 = 1
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K1 = MQ0+MQ0
K0 = 1
60
EXPERIMENT NO: 13
SEQUENCE DETECTOR
AIM
To design and set up a sequence detector to detect the sequence 101
COMPONENTS & EQUIPMENTS REQUIRED

IC7474, IC7404, IC 7408 and digital trainer kit.
THEORY
A sequence detector is a sequence network that detects a particular sequence from a
sting of 0s and 1s applied to the input and generates an output. For designing a circuit
we have to first construct the partial state graph. Here we need only three states since the
given sequence has three bits. In the state graph the 1 occurring after S2 may be the
starting point of another 101. So after S2 we have to return to S1, also we can include
other input-output options in the state graph. From the state graph option obtain the state
table and assign codes to each state. Then drive the flip flop input equation by plotting the
state table in a K-map. Using this implement the logic diagram.
STATE GRAPH
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PROCEDURE
3. Set up the circuit as shown in the figure.
4. Check whether it detects the sequence 101
RESULT
Designed a logic circuit to detect the sequence 101 and verified the output.
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STATE TABLE
Next State
X=0 X = 1
Present
state
S0
S1
S2
S0
S2
S0
S1
S1
S1
QA
QB
0
0
1
0
1
0
QA + 1
QB + 1
X=0
X=1
00
10
00
01
01
01
Z (O/P)
X=0
X=1
0
0
0
0
0
1
QA +1 = QB X
QB + 1 = X
Z= QAX
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EXPERIMENT NO: 14
MULTIPLEXER & DE MULTIPLEXER USING GATES

AIM
To design and set up multiplexer and de multiplexer circuit using logic gates.
COMPONENTS REQUIRED
IC 7404, IC 7408, IC 7432
THEORY
Multiplexer
A multiplexer, sometimes referred to as a "multiplexer" or simply "mux", is a device that
selects between a number of input signals. In its simplest form, a multiplexer will have
two signal inputs, one control input, and one output. An everyday example of an analog
multiplexer is the source selection control on a home stereo unit.
Multiplexers are used in building digital semiconductors such as CPUs and graphics
controllers. In these applications, the number of inputs is generally a multiple of 2 (2, 4,
8, 16, etc.), the number of outputs is either 1 or relatively small multiple of 2, and the
number of control signals is related to the combined number of inputs and outputs. For
example, a 2-input, 1-output mux requires only 1 control signal to select the input, while
a 16-input, 4-output mux requires 4 control signals to select the input and 2 to select the
output. Similarly to create a 4 to 1 MUX, we need 2 selector lines to route either of the
four input lines through a single output line.
The truth table for a multiplexer is constructed as the initial step towards design
(shown in figure.1). As is clear from the truth table, to create a 4 to 1 MUX, we need 2
selector lines to select either of the four input lines.
As a general rule a MUX with n selection inputs can route 2 n data inputs through a single
output. Selection input determines the input that should be connected to the output
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Demultiplexer
A Demultiplexer is just the opposite of a multiplexer. It takes 1 input and creates n
outputs. As shown in Figure it is designed to pass a 0 on all outputs except the one
selected which passes the true value of the input.
As in case of a MUX with n selection inputs can route 1 data inputs through 2 n output
lines. Selection input determines the out put line through which data is to be routed.
PROCEDURE
Truth tables are constructed, Expressions for each output lines are separately derived and
circuit realized using logic gates.
RESULT
A multiplexer and demultiplexer circuits are designed and set up using logic gates and
outputs verified.
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Fig. 1. 4 line -1 line multiplexer

If I0 through I3 are the input lines, output is either of the four lines depending on
the status of selection lines. For a TRUE input on any one input line the output is TRUE
if that particular line is selected. Or in general, the output may be expressed by the
function,
O = S0S1I0+ S0S1I1+ S0S1I2+ S0S1I3
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TRUTH TABLE FOR A DE MULTIPLEXER

D
S0
S1
O0
O1
O2
O3
1
0
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
0
1
For a TRUE i/p the truth table for the de multiplexer may be constructed as shown and
the logic expressions for distinct output lines may be individually derived from the truth
table. Thus,
O0
O1
O2
O3
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=
=
=
=
S0S1D
S0S1D
S0S1D
S0S1D
68

EXPERIMENT NO: 15
COMBINATIONAL LOGIC DESIGN USING DECODERS AND

MULTIPLEXERS
AIM
To implement different logic functions using multiplexer and decoder
a) full adder
b) full subtractor
COMPONENTS REQUIRED
IC trainer kit, ICs 74151 & 74138, 7400
THEORY
Multiplexer is a combinational logic circuit, which can select any of the inputs and route
it to the output. Various multiplexer ICs are available with 4,8 and 16 inputs and one
output. They have control inputs to carry out this operation. The 74151 is an 8 line to 1
line multiplexer. It has three select inputs A0, A1 ,A2 and an active low enable input EN.
The data inputs are designated as D0 through D7.The binary number at the data select
input at the select lines select the data to be directed to output. For example if A2A1A0 is
001, D1 will be available at the output .The enable input is used to activate or deactivate
the chip. Multiplexer can be used to realize logic circuits .A MUX with n inputs can be
used to realize a n variable Boolean expression. With additional gates or circuits, an n +1
variable expression can be realized with the same MUX.
A decoder is a combinational logic circuit which has n input lines and 2 n output lines. It
activates a single output lines at a time according to the input combinations. It has a one
to one correspondence between the 2n output lines and the possible 2n input combinations.
So the output lines can be considered as minterm in case of active low decoders .IC
74138 decoder accepts three binary weighted inputs A0A1A2 and when enabled
provides eight mutually exclusive active low inputs, which has three enable inputs, two
active low inputs and one active high input.
PROCEDURE
1. Obtain and test the components.
2. Set up the circuits.
3. Provide the inputs and verify the outputs
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RESULT
Logic circuit for full adder and full subtractor were set up using multiplexers and
decoders and their truth tables were verified.
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FULL ADDER
FULL SUBSTRACTOR
TRUTH TABLE
TRUTH TABLE
A
Cin
Cout
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Cin
Bo
71
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FULL ADDER USIN DECODER
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EXPERIMENT NO: 16
PARITY GENERATOR / CHECKER

AIM
To design and set up a circuit to generate a parity bit to be associated with data
so as to assign odd/even parity for the data or check the parity of the parity encoded data,
available as the input. The condition is specified by a control bit denoted by Pi whose
logic states 0 or 1 which corresponds to odd or even parity as is decided by the designer.
COMPONENTS REQUIRED
IC 7486, IC 7404, TRAINER KIT
THEORY
Even parity means an n bit data has even number of 1s in it. Similarly Odd parity
means an n bit data has an odd no: of 1s in it.
Parity generator
A parity generator generates a parity bit to be associated with the data so that the
encoded data is assigned an odd or even parity.
For the generator, the input bits are Pi D3 D2 D1 D0, where Pi whose logic states 0
or 1 corresponds to odd or even parity as is decided by the designer. We get a
corresponding output Po to be associated with the data bits. The same circuit can also be
used to check the parity of a parity encoded data.
Parity checker
A Parity checker checks the no: of 1s in a data and gives a high out put depending on
the condition you are checking for. It gives a high if you have even no of 1s and you are
checking for even parity. Similarly it gives a high out put if you have odd no of 1s and
you are checking for odd parity. For the checker, the input bits are Pi D3 D2 D1 D0,
where Pi (is the P0 from generator) whose logic states 0 or 1 corresponds to odd or even
parity as is decided by the designer. We get a corresponding output Po to be a 0 or 1 to
indicate an error or no error.
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PROCEDURE
Using XOR gate for any number of inputs, output is high if the no: of 1s are odd.
This condition +Pi should give you Po
Accordingly, construct the truth table.
Encoded data will be of the form D3 D2 D1 D0 Po
This encoded data is now the input to the checker .Now Pi =Po =1.
The same generator circuit now generates bit Po=0 for opposite parity(odd parity in this
case.). OR . TRUE condition (Logic HIGH) of Po is a check for even parity.
Let us discuss in detail with an example;
Let D3 D0 be the data bits. Assume that you have to set even parity and this has
to be set by setting Pi =0.
P =0. ----Even parity
P =1. -----Odd parity
RESULT
A 4 bit parity generator/checker circuit has been designed and set up and out put
verified for all possible combinations of the four bit data.
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Parity
generator
/checker
Truth table:
Data bits
D3
D2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Parity encoded data
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Pi=0
Po
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
Pi=1
Po
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
Parity generator/checker circuit diagram.
D1
D2
optional
Po
D3
D4
Pi
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EXPERIMENT NO: 17
MAGNITUDE COMPARATOR
AIM
To design and set up magnitude comparators to compare two n bit binary
numbers A & B and hence visually indicate the relative magnitudes ( ie: if A is
greater than B, A is equal to B Or A is less than B)
COMPONENTS REQUIRED
IC 7408, IC 7404, IC 7486, IC 7432
THEORY
A magnitude comparator compares two n-bit binary numbers and generates

outputs indicating the relative magnitudes of the binary numbers. which is greater
or if they are equal or which is smaller
This may easily be implemented using the simplified solutions of the
corresponding truth tables constructed.
Obviously the simplification of truth tables becomes tedious when the no of bits
increases and in such cases we go for some short hand methods like cascading of
single bit comparators with some minor modifications. (Reference
recommended)
Comparators can be used in a central processing unit (CPU) or microcontroller in

branching software.
PROCEDURE
Construct the truth tables for a one bit and two bit magnitude comparators
Find out solutions for the conditions A=B, A > B, and A < B
Realize the expressions using logic gates.
Verify the out puts with the help of truth table.
The operation of a single bit digital comparator can be expressed as a truth table:
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77
RESULT
A one bit and two bit magnitude comparators has been designed and set up and outputs
verified in each case.
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78
Inputs
Outputs
A B A<BA=B A>B
0 0
0
1
0
0 1
1
0
0
1 0
0
0
1
1 1
0
1
0
A one bit magnitude comparator may easily be realized by

finding the solutions for the three distinct columns of the truth
table.Thus the functions may be written as
F1 = (A > B): AB
F2 = (A = B): AB + AB
F3 = (A < B): AB
KARNAUGH MAPING:
A>B
BBB
B
A=B
A<B
figure of a 1-bit magnitude comparator.
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Similarly the operation of a two bit digital comparator can be expressed as a truth table:
Inputs
Outputs
A1 A0 B1 B0 A < B A = B A > B
0 0 0 0 0
1
0
0 0 0 1 1
0
0
0 0 1 0 1
0
0
0 0 1 1 1
0
0
0 1 0 0 0
0
1
0 1 0 1 0
1
0
0 1 1 0 1
0
0
0 1 1 1 1
0
0
1 0 0 0 0
0
1
1 0 0 1 0
0
1
1 0 1 0 0
1
0
1 0 1 1 1
0
0
1 1 0 0 0
0
1
1 1 0 1 0
0
1
1 1 1 0 0
0
1
1 1 1 1 0
1
0
A1
B1
Ao
A two bit magnitude comparator may easily be realized by

finding the solutions for the three distinct columns of the truth
table. Thus the functions may be written as
F1 = (A > B): A1B1 + A0B1B0 + A1 A0B0
F2 = (A = B): (A1 B1) (A0 B0)
F3 = (A < B): A1 B1 + A1 A0B0 + A0 B1 B0
Bo
A>B
A=B
A<B
EXPERIMENT NO: 18
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CODE CONVERTERS
AIM
To design and setup to following code converter circuits
(ii)
4 bit binary to gray code
(iii)
4 bit gray to binary code
(iv)
BCD to XS-3 code
COMPONENTS REQUIRED
(i)
(ii)
IC Trainer kit
IC 7486, IC 7408, IC 7404. IC 7432
THEORY
To convert a binary number to corresponding gray code, the following rules are
applied. The MSB in the gray code is same as the corresponding digit in the binary code.
While going from left to right each adjacent pair of binary digit is added to get the next
gray code digit.
As first step to design a binary to gray code converter setup a truth table with
binary number B3 B2 B1 B0 and corresponding gray code number G3 G2 G1 G0. Setup a
circuit realizing the simplified logic expressions obtained using Kmap for Gs as function
of Bs.
To convert the gray code to binary code the following rules are used. The MSB of
the binary number is the same as the corresponding digit in gray code. Add each binary
digit generated to the gray code and digit in next adjacent position. Disregard the carry.
To design Gray to binary converter setup the truth table and get simplified expression
using Kmap.
To convert BCD to XS-3 code, a binary three(0011) is added with the
corresponding BCD and thus obtained the XS-3 code.BCD codes are valid up to binary
nine and after that it is of invalid state.
PROCEDURE
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81

3. Set up the circuit and feed the input combinations
4. Observe the output for the given input code.
4. Verify the truth table for all the cases.
RESULT
Designed and setup to following code converter circuits
(i)
4 bit binary to gray code
(ii)
4 bit gray to binary code
(iii)
BCD to XS-3 code
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82
G3 = B3
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83
Circuit Diagram
G0
B0
B1
G1
B2
G2
B3
G3
Grey to Binary
VIET
G3
G2
G1
G0
B3
B2
B1
B0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
84
B3 = G 3
G3
B3
G2
B2
B1
G1
B0
G0
BCD to XS-3
Truth table
B3
B2
X3
X 2 X1
X0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
VIET
1
0
0
1
1
0
0
1
1
0
85

K-map
X0 = B0
X3 = B3+B2(B1+B0)
Circuit Diagram
B0
X0
X1
B1
B2
B3
VIET
X2
X3
86

EXPERIMENT NO: 19
ASTABLE AND MONOSTABLE MULTIVIBRATOR USING 555 IC

AIM
To design and set up monostable and astable multivibrators using 555 IC.
COMPONENTS REQUIRED
CRO, bread board, 555 IC, dc supply, resistors and capacitors.
THEORY
A 555 timer is a highly stable device for generating accurate time delay or
oscillation. Internally it contains upper and lower comparators, RS FLIP FLOP two
transistors and a power amplifier circuit which is an inverter.
In the stable state ,FF holds transistor Q1 ON, thus clamping external capacitor
C to ground. Then output remains at low state. As trigger passes through Vcc/3, FF is set,
(Q=1) which makes tr Q1 off and short circuit across timing capacitor C is released. As
Q=1, output goes high .Since C is unclamped, voltage across it rises exponentially
through R towards Vcc with a time constant RC. After a time period T, the capacitor
voltage is just greater than 2/3Vcc and Upper Comparator resets FF (R=1 and S=0).This
makes Q=0 and tr Q1 goes ON, there by discharging capacitor C rapidly to ground
potential. The output returns to stand by state.
The voltage across capacitor is given by
Vc=Vcc(1- e-t/RC )
At t=T, Vc=2Vcc/3
Therefore, 2Vcc/3 = Vcc (1- e-T/RC)
Or, T=RC ln 1/3
Or, T= 1.1RC (in seconds)
Thus timing interval is independent of supply voltage. Once triggrerd, output remains in
high state until time T elapses, which depends only upon R & C.
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87
When the power supply Vcc is connected, the external timing capacitor C charges
towards Vcc with a time constant (RA+RB) C. By this time R=0, S=1 and so Q=0 .So
output is High. When capacitor voltage equals 2/3Vcc, upper comparator (UC) triggers
the control FF
so that Q=1.This makes transistor Q1 ON and capacitor C starts discharging towards
ground through RB and transistor Q1 with a time constant RB C
During discharge of timing capacitor C, as it reaches Vcc/3, the lower comparator is
triggered and at this stage S=1,R=0 which turns Q=0.This makes Q1 OFF and again
capacitor C starts to charge. Thus capacitor periodically changes between 2/3Vcc and
1/3Vcc.
The charging period of capacitor C = 0.69(RA+RB) C
The discharging period of capacitor C = 0.69(RB) C
PROCEDURE
1. Verify conditions of 555 IC using IC tester
2. Setup circuit on the breadboard of the IC trainer kit.
3. For mono stable multi-vibrator, adjust function generator to get a square wave output
of T = 3ms.
4. Connect the output pin of functional generator to the trigger input by using probes.
5. Observe waveform at pin no:3 ( output pin) and also across timing capacitor C and
ground.
RESULT
Designed and set up a stable and mono stable multi vibrator using 555.
VIET
88

Design
Take Vcc = 10V
T = 1.1 RC = 1ms
Take R=10K to limit current through internal transistor.
Then C = 0.1 F
For triggering circuit
Ri Ci 0.0016 Tt (condition for good differentiation)
Let Tt = 3ms
Take Ri = 5.6K
Then Ci = 0.01microF
Circuit diagram
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89

Waveforms
Design
Take Vcc = 10V and
Tc= 1ms an Td = 0.5ms
We have , Tc = 0.69 (RA +RB) C

And Td = 0.69 RB C
Take RA = RB = 6.8 K
Let C = 0.1 F and C1 = 0.01F.
Circuit diagram
Waveforms
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90

EXPERIMENT NO: 20
SEQUENCE GENERATOR
AIM
Design of Sequence Generator.
COMPONENTS REQUIRED
IC 7495, IC 7486
THEORY
To generate a sequence of length S it is necessary to use at least N number of
Flip-Flops, which satisfies the condition S= 2
-1.
N
The given sequence length S = 15.
Therefore N = 4.
Note: - There is no guarantee that the given sequence can be generated by 4 f/fs.
If the sequence is not realizable by 4 f/fs then 5 f/fs must be used and so on.
PROCEDURE
1. Connections are made as per the circuit diagram.
2. Clock pulses are applied one by one and truth table is verified.
RESULT
Designed and set up a sequence generator.
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91
Circuit Diagram: - Sequence Generator
Truth Table:Map
Value Clock QA QB QC QD o/p D
15
VIET
1
1
0
1
0 0
92

4
0 0
1 0
12
10
11
0 0
0 1
11
1 0
12
1 1
10
13 1
0 1
13
14 1
1 1
14
15 1
0 1
VIET
93

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EXPERIMENT NO: 1

VERIFICATION OF TRUTH TABLES OF DIGITAL ICS

Digital Electronics lab manual

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2) Quad two input OR gates IC 7432

3) Hex inverter gates -IC7404

4) NAND gates- IC 7400

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5) NOR gates-IC 7402

6) XOR gate- IC 7486

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INTERNAL CIRCUIT DIAGRAM 1

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VERIFICATION OF DE MORGANS THEOREM AND

The complement of a product equals the sum of the complements.

Postulates of Boolean algebra

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the same input lines].

REALIZATION OF LOGIC EQNS. AND CORRESPONDING TRUTH TABLES

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Postulates of Boolean algebra

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REALISATION OF LOGIC GATES USING UNIVERSAL

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LOGIC GATES USING NAND

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LOGIC GATES USING NOR

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ARITHMETIC LOGIC CIRCUITS-HALF ADDER

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USING X-OR & NAND

USING NAND ONLY

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USING NAND ONLY

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ARITHMETIC LOGIC CIRCUITS-HALF SUBTRACTOR & FULL

The expression for the borrow of full subtractor is

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a)USING X-OR AND NAND

b)USING NAND ONLY

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USING X-OR AND NAND

USING NAND ONLY

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FOUR BIT BINARY ADDER, SUBTRACTOR & BCD

To design and setup the following arithmetic circuits using IC 7483

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Single Digit BCD Adder

4 Bit Adder/Subtractor Circuit