Codigo:

0104

Instituto Tecnolgico de Costa Rica

Programa de Maestra en Ciencia de la Computacin

Sistemas Operativos Avanzados

Resumen - Chapter 10 Exceptions and Interrupts

I Semestre 2014

Prof: Dr. Francisco Torres

Marco Len Sarkis

2014160469

Exceptions and Interrupts

The exceptions and interrupts are part of a mechanism provided by the majority of embedded
processor architectures to allow for the disruption of the processors normal execution path.
An exception is any event that disrupts the normal execution of the processor and forces the
processor into execution of special instructions in a privileged state. Exceptions can be
classified into two categories: synchronous and asynchronous.
An interrupt is an asynchronous exception triggered by an event that an external hardware
generates. What differentiates interrupts from other exceptions is the source of the event.
General exceptions have classifications and are prioritized based on the classifications. It is
possible there exists another level of priorities, imposed and enforced by the interrupt hardware,
among the external interrupts.
Programable Input Controller
Most embedded designs have more than one source of external interrupts, and these multiples
external interrupt sources are prioritized. This process is handled by a programmable input
controller (PIC). The PIC is in charge of prioritizing multiple interrupt sources and offloading the
core CPU with the processing required to determine an interrupts exact source.
Installing Exception Handlers
Before exceptions and interrupts can be handled we must install exception service routines
(ESR) and interrupt service routines (ISR) to the system. Service routines need to store blocks
of information, called processor state information, to ensure proper return of program execution
after the service routing is complete.
An interrupt can be disabled, active or pending. A disabled interrupt is also called a masked
interrupt. The PIC ignores a disabled interrupt. A pending interrupt is an unacknowledged
interrupt, which occurs when the processor is currently processing a higher priority interrupt. An
active interrupt is the one that the processor is acknowledging and processing.
Nested Exceptions
Nested exceptions refer to the ability for higher priority exceptions to preempt the processing of
lower priority exceptions. Much like a context switch for tasks when a higher priority one
becomes ready, the lower priority exception is preempted, which allows the higher priority ESR

to execute. When the higher priority service routing is complete, the earlier running service
routing returns to complete.
Exception Frame
The exception frame is also called the interrupt stack in the context of asynchronous exceptions.
Two main reasons exist for needing an exception frame. One reason is to handle nested
exceptions. The other reason is that, as embedded architecture becomes more complex, the
ESR or ISR consequently increases complexity.
ESR and ISR Differences
One of the main differences between ESR and ISR is in the additional processor state
information saved. Another one is that an exception handler in many cases cannot prevent other
exceptions from occurring, while an ISR can prevent interrupts of the same or lower priority from
occurring.
Questions
Why is this an interesting topic?
This in an interesting topic because many real-time operating systems provide wrapper
functions to handle exceptions and interrupts in order to shield the embedded systems
programmer from the low-level details. This application programming layer allows the
programmer to focus on high-level exception processing rather than on the necessary, but
tedious, prologue and epilogue system-level processing for that exception. This isolation,
however, can create misunderstanding and become an obstacle when the programmer is
transformed from an embedded applications programmer intro an embedded systems
programmer.