TK3723+Data+Sheet+v0 23

http://www.elecfans.com/ http://www.hqpcb.
com/ PCB
TK3723 Data Sheet Preliminary

Dual Turbo-EPONTM MAC Traffic Manager for OLT
FEATURES
Two IEEE 802.3ah Ethernet-PON MAC
Controllers
2.5 Gbps and 1.25 Gbps downstream rate
options on each PON channel
1.25 Gbps upstream rate on each PON
channel
Two IEEE 802.3z Gigabit Ethernet MAC
Controllers with MII, GMII and TBI interfaces
Hardware-based
configurable
Dynamic
Bandwidth Allocation (DBA)
System solution with firmware for embedded
ARM9 processor
IEEE 802.3ah OAM
IEEE 802.3ah Forward Error Correction on
the PON interfaces
IEEE 802.1D bridging: 8K MAC Address
learning and aging on local interface
IEEE 802.1p with four priority queues per
LLID
IEEE 802.1Q VLAN mapping to LLID
Supports 256 bidirectional (downstream and
upstream) LLIDs for each PON interface plus
128 downstream-only multicast LLIDs per
PON
Per-LLID/customer downstream security

using AES-128 encryption or Triple Churning
(CTC) algorithms
Line-rate
Layer-2/3/4
filtering
and
classification including IPv6 support
Bi-Directional SLA enforcement per LLID
IGMP/MLD Proxy and IP Multicast Shaping
Supports multiple mesh and WDM system
configurations
10/100 MII (CRAFT) or Asynchronous Bus
Management Interface
2048 queues (FIFOs) shared between
downstream and upstream direction, stored
in up to 256 Megabytes of low-cost external
DDRII DRAM memory
Supports Local and Remote Loop-back test
Strobe pins for optical burst monitoring
32 GPIO pins
IEEE 1149.1 JTAG Boundary Scan
3.3V/1.8V I/O and 1.2V Core supply
35 x 35 mm 927 HSBGA package
DESCRIPTION
The TK3723 is a dual IEEE 802.3ah standard Ethernet PON (EPON) MAC controller for Optical Line Terminals
(OLT). It incorporates two EPON MACs for WAN connectivity to a passive point-to-multipoint (PON) optical fiber
network, and two IEEE 802.3z Gigabit Ethernet MACs as a Central Office Network Interface. Each TK3723 EPON
channel provides 2.5 Gbps and 1.25 Gbps downstream rate options while maintaining a 1.25 Gbps upstream rate.
The TK3723 provides service policy, security and authentication management to meet the requirements for carrier
applications. An embedded ARM9 processor provides a management system for self management, auto
discovery, and bandwidth provisioning. The TK3723 can be used in either a Media Converter or Line-card
configuration.
The TK3723 is compatible with all Teknovus ONU chipsets.
Rev 0.23
Teknovus Confidential - View Under NDA Only
This document contains information on a new product. Specifications and information herein are subject to change without notice.
http://www.elecfans.com/ http://www.hqpcb.com/ PCB

Figure 1. Block Diagram of TK3723-Based Turbo-EPONTM Dual OLT
Page 2 of 89
Rev 0.23

Revision History
This section records the change history of this Data Sheet.
Table 1. Revision History
Date
Version
August 3, 2007
0.10
Revision Description
- Preliminary Initial Release
Author
Jerry Wojtowicz
- Updated power consumption characteristics

- Listed DDRII DRAM and SDRAM required characteristics
August 6, 2007
0.11
- Added Data Sheet progression information (back page)
Bill Burns
- Added System Organizations sections
Jerry Wojtowicz
- Removed presently unsupported encryption modes

- Added DDRII DRAM and SDRAM layout guidelines
- Updated SDRAM layout guidelines to include 16-bit wide devices
December 17,
2007
Jerry Wojtowicz
- Updated supported FLASH list to include Spansion device

0.12
- Updated System Organizations section with WDM modes

- Added Reset and Output Clocks AC characteristics
- Added DDRII DRAM AC characteristics
- Added FLASH AC characteristics
Jerry Wojtowicz
- Added SDRAM AC characteristics

February 29,
2008
0.13
- Added FLASH layout guidelines

- Updated I/O latch-up current to be JEDEC compliant
- Updated JEDEC IDCODE code
- Updated DDRII DRAM AC characteristics
- Updated SDRAM AC characteristics
April 25, 2008
0.20
Jerry Wojtowicz
- Updated supported FLASH list to include Intel/Numonyx device

- Updated TK3723 Ordering Information for rev. B of the chip
- Updated DDRII AC characteristics
December 12,
2008
Jerry Wojtowicz
- Changed GPI027 pin name to GPI27

0.21
- Updated LOC_Px_DNCOMDET pins description in GMII mode

- Updated ARM_WDOUT_N / ARM_RSTOUT_N pin description
- Updated power consumption characteristics
February 13,
2009
0.22
- Corrected max Tc value in Table 21
Jerry Wojtowicz
- Added Leaded package option in TK3723 Ordering Information

- Modified Reset AC characteristics
Jerry Wojtowicz
- Added ARM_WDOUT_N AC characteristics

May 12, 2009
0.23
- Changed Teknovus Logo

- Updated DDRII, SDRAM and FLASH Interfaces PCB layout guidelines
- Added EPON SerDes and Transceiver Interfaces sections
- Updated supported FLASH list to include ST Micro device
Page 3 of 89
Rev 0.23

Table of Contents
1
TK3723 Functional Description ..................................................................................................................................... 8

1.1
System Organizations ......................................................................................................................................... 10
1.1.1 Two Network-side Interfaces to Two 1.25 Gbps EPONs ........................................................................ 10
1.1.2 Two Network-side Interfaces Aggregated to a Single 2.5 Gbps EPON .................................................. 10
1.1.3 One Network-side Interface Expanded to Two 1.25 Gbps Separate EPONs ......................................... 11
1.1.4 Two Network-side Interfaces Expanded to Two 2.5 Gbps EPONs ......................................................... 11
1.1.5 Two Network-side Interfaces Expanded to 1.25 Gbps and 2.5 Gbps EPONs ........................................ 12
1.1.6 Two Network-side Interfaces Aggregated to a Single WDM EPON ........................................................ 12
1.2
IEEE 802.3ah EPON MACs ................................................................................................................................ 13
1.2.1 EPON SerDes Interfaces ........................................................................................................................ 13
1.2.2 EPON Transceivers Interfaces ............................................................................................................... 14
1.3
Dynamic Bandwidth Allocation Control (DBA) ..................................................................................................... 15
1.4
IEEE 802.3z Gigabit Ethernet MACs ................................................................................................................... 16
1.5
Lookup Engines (LUEs)....................................................................................................................................... 16
1.6
Packet Buffering (FIFOs) ..................................................................................................................................... 17
1.6.1 DDRII Interfaces PCB Layout Guidelines ............................................................................................... 17
1.7
Shapers/Schedulers ............................................................................................................................................ 18
1.8
ARM9 Processor Subsystem............................................................................................................................... 18
1.8.1 FLASH Interface PCB Layout Guidelines ............................................................................................... 20
1.8.2 SDRAM Interface PCB Layout Guidelines .............................................................................................. 20
1.9
Host Interfaces .................................................................................................................................................... 20
1.10 GPIO Interface .................................................................................................................................................... 22
1.11 UART Interface .................................................................................................................................................... 23
1.12 Ethernet Serial Management Interface ................................................................................................................ 24
1.13 JTAG and Test Interfaces.................................................................................................................................... 24
TK3723 Signals Description......................................................................................................................................... 26

2.1
Signals Types ...................................................................................................................................................... 26
2.2
Signals Names Description ................................................................................................................................. 26
2.3
Signals Sorted in Ball Numerical Order ............................................................................................................... 52
TK3723 Electrical Specifications ................................................................................................................................. 60

3.1
Absolute Maximum Ratings ................................................................................................................................. 60
3.2
Recommended Operating Conditions ................................................................................................................. 61
3.3
Power Supplies Current and Power .................................................................................................................... 61
3.4
Power Supplies Sequencing................................................................................................................................ 62
3.5
DC Characteristics .............................................................................................................................................. 63
3.5.1 CMOS I/O DC Characteristic .................................................................................................................. 63
3.5.2 SSTL-18 I/O DC Characteristic ............................................................................................................... 63
3.6
AC Characteristics ............................................................................................................................................... 65
3.6.1 System Clock Timing .............................................................................................................................. 65
3.6.2 Local-Side MII/GMII/TBI Timing .............................................................................................................. 66
3.6.3 Plant-Side TBI Timing ............................................................................................................................. 69
3.6.4 DDRII DRAM Interfaces Timing .............................................................................................................. 71
3.6.5 ARM9 Interface Timing ........................................................................................................................... 73
3.6.6 CRAFT Port MII Timing .......................................................................................................................... 77
Page 4 of 89
Rev 0.23

3.6.7
3.6.8
3.6.9
3.6.10
Ethernet Serial Management Timing ...................................................................................................... 78

Asynchronous Bus Timing ...................................................................................................................... 79
GPIO Timing ........................................................................................................................................... 81
Reset Timing .......................................................................................................................................... 82
TK3723 Mechanical Specifications ............................................................................................................................. 83

4.1
Package Diagram ................................................................................................................................................ 83
4.2
Package Thermal Specifications ......................................................................................................................... 85
4.3
Package Thermal Requirements ......................................................................................................................... 85
4.4
Heatsink Selection ............................................................................................................................................... 86
TK3723 Ordering Information ...................................................................................................................................... 88
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Revision History ................................................................................................................................................. 3

JTAG Instructions............................................................................................................................................. 24
ARM9 Processor Bus Interface ........................................................................................................................ 26
Inter-Processor Asynchronous Bus Interface ................................................................................................... 29
Ethernet Serial Management Interface............................................................................................................. 30
Management Port (CRAFT) MII Interface ........................................................................................................ 31
Local-Side PHY/SerDes MII/GMII/TBI Interface - Port 1 .................................................................................. 31
Plant-Side SerDes Interface Port 1 ............................................................................................................... 33
Ethernet PON Transceiver Interface Port 1 ................................................................................................... 36
Packet Buffer DDRII DRAM Interface Port 1 ................................................................................................. 37
Local-Side PHY/SerDes MII/GMII/TBI Interface Port 2 ................................................................................. 39
Plant-Side SerDes Interface Port 2 ............................................................................................................... 41
Ethernet PON Transceiver Interface Port 2 ................................................................................................... 45
Packet Buffer DDRII DRAM Interface Port 2 ................................................................................................. 45
JTAG and Test Interface .................................................................................................................................. 48
Reference Clocks, System Reset, PLL and GPIO Interface ............................................................................ 48
Power and Ground ........................................................................................................................................... 49
Signals Sorted in Ball Numerical Order ............................................................................................................ 52
Absolute Maximum Ratings ............................................................................................................................. 60
Recommended Operating Supply Voltages ..................................................................................................... 61
Recommended Operating Temperatures ......................................................................................................... 61
Power Consumption ......................................................................................................................................... 61
CMOS I/O DC Characteristics .......................................................................................................................... 63
SSTL-18 I/O DC Characteristics ...................................................................................................................... 63
System Clock Source Requirements................................................................................................................ 65
Local-Side MII Input Timing (MAC Mode) ........................................................................................................ 66
Local-Side MII Output Timing (MAC Mode) ..................................................................................................... 66
Local-Side GMII Input Timing (PHY and MAC Mode) ...................................................................................... 67
Local-Side GMII Output Timing (PHY and MAC Mode) ................................................................................... 67
Local-Side TBI Input Timing (MAC Mode) ........................................................................................................ 68
Local-Side TBI Output Timing (MAC Mode) ..................................................................................................... 68
Plant-Side TBI Input Timing ............................................................................................................................. 69
Plant-Side TBI Output Timing .......................................................................................................................... 70
Page 5 of 89
Rev 0.23

Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
DDRII DRAM Write Timing (BL=8, WL=2, AL=0, WR=2) ................................................................................. 71

DDRII DRAM Read Timing (BL=8, RL=3, AL=0, CL=3) ................................................................................... 72
FLASH Write Timing ........................................................................................................................................ 73
FLASH Read Timing ........................................................................................................................................ 74
SDRAM Write Timing (CL=3, BL=8)................................................................................................................. 75
SDRAM Read Timing (CL=3, BL=8) ................................................................................................................ 76
CRAFT Port MII Input Timing (MAC Mode) ...................................................................................................... 77
CRAFT Port MII Output Timing (MAC Mode) ................................................................................................... 77
MDIO Serial Management Timing .................................................................................................................... 78
Asynchronous Bus Read Timing ...................................................................................................................... 79
Asynchronous Bus Write Timing ...................................................................................................................... 79
GPIO Timing .................................................................................................................................................... 81
Reset Timing .................................................................................................................................................... 82
927-HSBGA Package Dimensions ................................................................................................................... 84
927-HSBGA Thermal Specifications for JEDEC 4-layer PCB .......................................................................... 85
INL35001-10/1.7BU Heatsink Thermal Characteristics .................................................................................... 86
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Block Diagram of TK3723-Based Turbo-EPONTM Dual OLT.............................................................................. 2

TK3723 Block Diagram ...................................................................................................................................... 9
Two Distinct EPONs......................................................................................................................................... 10
Two Network Interfaces Aggregated to a Single 2.5 Gbps EPON ................................................................... 10
One Network Interface Expanded to Two 1.25 Gbps EPONs .......................................................................... 11
Two Network Interfaces Expanded to Two 2.5 Gbps EPONs .......................................................................... 11
Two Network Interfaces Expanded to 1.25 Gbps and 2.5 Gbps EPONs.......................................................... 12
Two Network Interfaces Aggregated to a WDM EPON with two 1.25 Gbps Downstream Flows ..................... 12
Two Network Interfaces Aggregated to a WDM EPON with 1.25 Gbps and 2.5 Gbps Downstream Flows ..... 13
EPON SerDes Interfaces* ................................................................................................................................ 14
FEC and Squelch Regions for typical APD receiver......................................................................................... 15
TK3723 DDRII Interfaces ................................................................................................................................. 17
TK3723 Host Interfaces ................................................................................................................................... 22
Simplified GPIO Pin Block Diagram ................................................................................................................. 23
UART Interface Timing..................................................................................................................................... 23
MDIO Serial Management Read and Write Timing .......................................................................................... 24
DEVICE IDENTITY Register Fields.................................................................................................................. 25
System Clock Source Timing ........................................................................................................................... 65
Local-Side MII Input Timing (MAC Mode) ........................................................................................................ 66
Local-Side MII Output Timing (MAC Mode) ..................................................................................................... 66
Local-Side GMII Input Timing (PHY and MAC Mode) ...................................................................................... 67
Local-Side GMII Output Timing (PHY and MAC Mode) ................................................................................... 67
Local-Side TBI Input Timing (MAC Mode) ........................................................................................................ 68
Local-Side TBI Output Timing (MAC Mode) ..................................................................................................... 68
Plant-Side TBI Input Timing ............................................................................................................................. 69
Plant-Side TBI Output Timing .......................................................................................................................... 70
DDRII DRAM Write with Auto-precharge Timing .............................................................................................. 71
Page 6 of 89
Rev 0.23

Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
DDRII DRAM Read with Auto-precharge Timing ............................................................................................. 72

FLASH Write Timing ........................................................................................................................................ 73
FLASH 16-bit Read Timing .............................................................................................................................. 74
FLASH 32-bit Read Timing .............................................................................................................................. 74
SDRAM Write with Auto-precharge Timing ...................................................................................................... 75
SDRAM Read with Auto-precharge Timing ...................................................................................................... 76
CRAFT Port MII Input Timing (MAC Mode) ...................................................................................................... 77
CRAFT Port MII Output Timing (MAC Mode) ................................................................................................... 77
MDIO Serial Management Timing .................................................................................................................... 78
Asynchronous Bus 32-bit Data Read Timing ................................................................................................... 79
Asynchronous Bus 16-bit Data Read Timing ................................................................................................... 79
Asynchronous Bus 32-bit Data Write Timing .................................................................................................... 80
Asynchronous Bus 16-bit Data Write Timing .................................................................................................... 80
GPIO Timing .................................................................................................................................................... 81
Reset Timing .................................................................................................................................................... 82
927-HSBGA Package Diagram ........................................................................................................................ 83
Derating Curves for 927-HSBGA Package on 4-layer JEDEC PCB for TJ=125C (without Heatsink) ............. 85
Derating Curves for 927-HSBGA Package on 4-layer JEDEC PCB for TJ=125C (with Heatsink) .................. 87
TK3723 Ordering Information ........................................................................................................................... 88
Page 7 of 89
Rev 0.23

TK3723 Functional Description
The TK3723 provides OLT functionality to access an IEEE 802.3ah standard Ethernet Passive Optical Network
(EPON). Local-side connectivity is Gigabit (or 100Mbit) Ethernet to either a switch for media-converter mode, or a
PHY device for line-card mode.
The TK3723 provides dual PON-side interfaces and dual Network-side interfaces. Each EPON MAC provides 256
bi-directional LLIDs plus 128 downstream multicast LLIDs.
The EPON interfaces on the TK3723 can be configured to operate at 2.5 Gbps or 1.25 Gbps downstream rate.
The upstream rate is 1.25 Gbps.
EPON security is provided on a per-LLID basis. TK3723 supports downstream AES128 CFB and Triple Churning
(CTC) encryption modes.
Forward Error Correction (FEC) is supported on the EPON interface. IEEE 802.3ah FEC provides improved
system performance in noisy optical environments.
Downstream data passes from the receiving interface into an Ethernet Lookup Engine module which determines
the appropriate LLID based on the Layer 2 MAC Addresses, L2/L3 protocol types, IEEE 802.1p priority, and/or
IEEE 802.1Q VLAN tag information. In the upstream direction, incoming frames are pre-tagged with the
appropriate LLID.
In the upstream direction, an Ethernet PON MAC checks and manages the range delays for incoming frames.
Timing strobes for an external burst mode transceiver can be configured. An EPON Lookup Engine modifies the
frames to insert VLAN tags, learn MAC Addresses, and classify upstream traffic. Frames are then written into the
queues in external SDRAM by the FIFO Controller.
The Lookup Engines may duplicate packets to multiple ports. This enables IP multicast to duplicate downstream
packets to both PON interfaces.
The FIFO queues are read by the Shaper/Scheduler modules according to the provisioned Service Level
Agreement (SLA). The frames are passed to a local-side Gigabit Ethernet interface, or to an EPON MAC.
The Shaper/Scheduler modules schedule downstream traffic to provisioned SLAs. The internal DBA Controllers
generate GATE messages to schedule upstream traffic based on provisioned latency and bandwidth SLAs.
Page 8 of 89
Rev 0.23

Figure 2. TK3723 Block Diagram
Page 9 of 89
Rev 0.23

1.1
System Organizations
The TK3723 supports a variety of system organizations. This section describes seven possible configurations.
1.1.1
Two Network-side Interfaces to Two 1.25 Gbps EPONs
The TK3723s dual-channel architecture allows using single OLT chip to create two completely separate EPONs.
Figure 3. Two Distinct EPONs
1.1.2
Two Network-side Interfaces Aggregated to a Single 2.5 Gbps EPON
Traffic from the two network-side Ethernet ports can be combined (fully or partially) to provide enough
downstream bandwidth to fill either 2.5 Gbps EPON channel.
Channel 1
ONU
1
Channel 1
2.5Gbps Downstream
Network (1)
Gigabit
Ethernet
802.3z
MAC
802.3ah
MAC
ONU
2
PON
1.25Gbps Upstream
ONU
3
Channel 2
Network (2)
Gigabit
Ethernet
Channel 2
802.3z
MAC
802.3ah
MAC
TK3723 Dual OLT
1.25G Dn/
1.25G Up
TK3713 or TK3714/15 ONU
2.5G Dn/
1.25G Up
TK3714/15 ONU
Figure 4. Two Network Interfaces Aggregated to a Single 2.5 Gbps EPON
Page 10 of 89
Rev 0.23

1.1.3
One Network-side Interface Expanded to Two 1.25 Gbps Separate EPONs
For configurations with a large number of subscribers but limited total bandwidth, either network-side Ethernet
port can be expanded to two separate 1.25 Gbps EPON channels.
Figure 5. One Network Interface Expanded to Two 1.25 Gbps EPONs
1.1.4
Two Network-side Interfaces Expanded to Two 2.5 Gbps EPONs
For configurations with a large number of subscribers and high bandwidth requirements, traffic from two networkside Ethernet ports can be copied (fully or partially) to two separate 2.5 Gbps EPON channels (mesh
configuration).
Figure 6. Two Network Interfaces Expanded to Two 2.5 Gbps EPONs
Page 11 of 89
Rev 0.23

1.1.5
Two Network-side Interfaces Expanded to 1.25 Gbps and 2.5 Gbps EPONs
For configurations with a large number of subscribers with different bandwidth requirements, traffic from two
network-side Ethernet ports can be copied (fully or partially) to two separate EPON channels which can have
different downstream rates (mesh configuration).
Figure 7. Two Network Interfaces Expanded to 1.25 Gbps and 2.5 Gbps EPONs
1.1.6
Two Network-side Interfaces Aggregated to a Single WDM EPON
For configurations with very high downstream bandwidth requirements, traffic from two network-side Ethernet
ports can be copied (fully or partially) to two separate downstream flows feeding a single EPON. The two
downstream flows can be transmitted at different wavelengths using WDM techniques. In this configuration only
channel 1 can be receiving upstream traffic. This configuration allows (but is not limited to) using mixed speed
ONUs (1.25 Gbps and 2.5 Gbps) on the same EPON.
Channel 1
Channel 1
1.25Gbps Downstream
Network (1)
Gigabit
Ethernet
802.3z
MAC
802.3ah
MAC
1490nm Dn
1310nm Up
1.25Gbps Upstream
ONU
1
WDM Splitter
Channel 2
Channel 2
1.25Gbps Downstream
Network (2)
Gigabit
Ethernet
802.3z
MAC
802.3ah
MAC
WDM PON
ONU
2
ONU
3
1550nm Dn
TK3723 Dual OLT
1.25G Dn/
1.25G Up
TK3713 or TK3714/15 ONU
2.5G Dn/
1.25G Up
TK3714/15 ONU
Figure 8. Two Network Interfaces Aggregated to a WDM EPON with two 1.25 Gbps Downstream
Flows
Page 12 of 89
Rev 0.23

Channel 1
Channel 1
1.25Gbps Downstream
Gigabit
Ethernet
Network (1)
802.3z
MAC
802.3ah
MAC
1490nm Dn
1310nm Up
1.25Gbps Upstream
ONU
1
WDM Splitter
Channel 2
Channel 2
2.5Gbps Downstream
Gigabit
Ethernet
Network (2)
802.3z
MAC
802.3ah
MAC
WDM PON
ONU
2
ONU
3
1550nm Dn
TK3723 Dual OLT
1.25G Dn/
1.25G Up
TK3713 or TK3714/15 ONU
2.5G Dn/
1.25G Up
TK3714/15 ONU
Figure 9. Two Network Interfaces Aggregated to a WDM EPON with 1.25 Gbps and 2.5 Gbps
Downstream Flows
1.2
IEEE 802.3ah EPON MACs
The two IEEE 802.3ah EPON MACs send downstream data to the PON and receive upstream data from the
PON. Each of the EPON MACs may operate at 2.5 Gbps or 1.25 Gbps downstream rate. The upstream rate is
1.25 Gbps.
The EPON MACs each support 256 LLIDs for bidirectional traffic, plus an additional 128 LLIDs for downstreamonly multicast traffic.
EPON security is provided on a per-LLID basis. TK3723 supports downstream AES128 CFB and Triple Churning
(CTC) encryption modes.
Forward Error Correction (FEC) is provided on the EPON interface on a per-LLID basis. IEEE 802.3ah FEC
provides improved system performance in noisy optical environments.
The EPON MACs collect statistics (per-LLID) to support RMON Level 2 requirements.
1.2.1
EPON SerDes Interfaces
The EPON MACs connect to EPON SerDes devices via Ten-Bit interfaces (TBI) at 1.25 Gbps, or via 16..20-bit
wide interfaces (2xTBI) at 2.5 Gbps.
The following SerDes devices were verified to function properly in EPON and Turbo-EPONTM applications:
Texas Instruments:
o TLK2541 (2.5 Gbps or 1.25 Gbps, Teknovus recommended)
o TLK1221 (bidirectional 1.25 Gbps only; low-cost)
o TLK1211 (bidirectional 1.25 Gbps only)
o TLK2201B (bidirectional 1.25 Gbps only)
AMCC:
o
S2060A/QSC (bidirectional 1.25 Gbps only, End-of-Life).
TK3723 allows two ways to provide reference clocks to the SerDes devices (see Figure 10). For SerDes devices
that have only one input clock (e.g. TLK1211, TLK1221, TLK2201B, S2060A/QSC) which serves as both the
PLA_Px_DND bus clock and the SerDes Tx reference clock source, an externally distributed 125MHz clock
source is recommended (see section 3.6.3 Plant-Side TBI Output Timing for detailed AC characteristics).
Page 13 of 89
Rev 0.23

Figure 10. EPON SerDes Interfaces*

* any SerDes can be connected to either OLT channel.
PLA_Px_DNCLK signals are not recommended to be used as reference clock sources to the SerDes.
For SerDes devices that have two input clocks (e.g. TLK2541), the TK3723 PLA_Px_DNCLK signals can be used
to clock-in the PLA_Px_DND buses, while externally distributed clean 125MHz clocks are recommended to be
used as SerDes reference sources.
1.2.2
EPON Transceivers Interfaces
The EPON SerDes connects to optical transceivers devices via differential serial interfaces. Since the upstream
1.25 Gbps flows are of the burst nature it is recommended that the interface between the Optical Transceiver Rx
output and the SerDes Rx input is DC coupled, i.e. does not use AC coupling capacitors. This approach will allow
minimizing SerDes synchronization time which will maximize PON performance.
1.2.2.1
Squelch Function and FEC
Typical optical transceivers perform a squelch function. This function eliminates optical noise from entering the
system when no optical signal is present. Optical noise may cause SerDes receive clocks to operate out of their
intended frequency range, and prevent them from locking when a valid signal returns. Optical noise may also
result in invalid characters being received into the MAC interface.
The squelch function in a typical transceiver module asserts a loss of signal when the input optical signal drops
below a defined optical power threshold. The loss of signal pin is then connected to an output enable pin at the
post amp which disables the output signal when no signal is present. This blocks the noise between bursts from
reaching the SerDes.
Squelch may limit the performance of FEC. Some transceivers have been observed to squelch the output at
optical powers in the range where FEC is beneficial. Squelch can therefore limit the performance of FEC if its
receive threshold is not set to the correct level.
Page 14 of 89
Rev 0.23

Optical Power
[dBm]
Receiver not FEC-ready
Receiver FEC-ready
0
-5
outside operating range - above saturation level
-10
-15
within operating range
-20
-25
-30
FEC Gain
SD hysteresis
-35
SD hysteresis
-40
outside operating range below noise level
-45
(SD function must prevent entering this region)
-50
Figure 11. FEC and Squelch Regions for typical APD receiver
The FEC coding is effective on bit error rates (BER) down to 1E-4. The loss of signal level should be set to an
optical power level that corresponds to a BER of 1E-4. This is typically adjusted through a resistor setting
connected to the post amp.
The timing of the squelch circuit is important as well. The threshold should be adjusted such that the squelch is
activated at the end of an upstream burst prior to noise being output.
Teknovus does not recommend disabling the squelch function, even when FEC is used. The optical noise
between burst at BER rates higher than 1E-4 has been shown to result in packet loss and deregistration on the
PON.
1.3
Dynamic Bandwidth Allocation Control (DBA)
The Dynamic Bandwidth Allocation (DBA) modules schedule upstream traffic on the PON (see Figure 2.
DBA schedules two major types of traffic:
Solicited Shaped, scheduled grants which dynamically respond to the amount of upstream data
reported by ONUs, and to the amount of space available in the destination queue
TDM High priority, unsolicited, fixed-period grants used to transport traffic requiring low latency.
Page 15 of 89
Rev 0.23

For Solicited traffic, DBA contains a Shaper/Scheduler that supports two Shaping elements and two Scheduling
elements per LLID for true minimum- and maximum-rate PON scheduling. The Shaper enforces rate and burst
size parameters for each LLID, and the Scheduler ensures that the PON bandwidth is divided into the desired
proportions. The Shaper supports rates between 256 Kbps and 1 Gbps. The Scheduler is a hierarchical weighted
round-robin (HWRR) design, with 8 priority levels and drop-down reservations between priority levels.
A Polling engine in DBA supports Solicited granting. The polling engine allows the user to configure regular
report-only grants to each solicited LLID. These grants alert DBA to the presence of ONU data that must be sent
upstream. The polling interval is programmable to allow tradeoffs between latency and bandwidth overhead.
A TDM grant engine in DBA generates high-priority grants at regular intervals. The TDM engine supports 64
channels of TDM grants. Each channel can be assigned to an LLID and is programmable for grant length and
grant interval.
EPON uses a nominal PON loop time of 250us. The TK3723 DBA supports loop times between 150us and 750us.
1.4
IEEE 802.3z Gigabit Ethernet MACs
The two IEEE 802.3z Gigabit Ethernet MACs make up the Network-side interface of the TK3723. They support
full duplex operation at 100 or 1000 Mbps, auto-negotiation and 802.3x Flow Control.
The Gigabit MACs connect to external 100/1000 Mbps Ethernet PHY devices via GMII or TBI.
The Gigabit MACs collect statistics to support RMON Level 2 requirements.
1.5
Lookup Engines (LUEs)
The Lookup Engines (LUEs) are used to modify frames and switch frames between queues, LLIDs, and VLANs.
The LUEs support static bridging, learning bridging, and VLAN bridging architectures. A total of 16K MAC
addresses are supported.
When configured for static bridging in the downstream direction, MAC addresses can be mapped to
the 256 possible LLIDs. Additional packet fields, such as IP DiffServ and protocol, can be used to
separate traffic into different LLIDs or queues. In this configuration, the Ethernet LUE would be
configured only to parse OAM traffic to the ARM processor.
When configured for learning bridging, the downstream EPON LUEs look up a frames Destination
Address (DA) in the MAC Address table. They then set a destination for the frame. Along with lookups
on other fields, the destination lookup results in determining a queue and an LLID for the frame. In
upstream bridging mode, the LUEs search for an SA. If the SA is not found, it is added to the MAC
address table. The new Address allows downstream frames (with a DA matching the recently learned
SA) to be forwarded to the appropriate LLID. Address aging times can be provisioned through the Host
Interface. They can take on values of the form 2^N * 8.75ms for N from 0 to 15, and are accurate to
within 12.5% of the provisioned value.
When configured for VLAN bridging, the downstream EPON Lookup Engines map the VLAN tag to an
LLID and a downstream queue. The VLAN tag is removed from the packet before being queued for the
downstream. The upstream engine maps the upstream LLID to a VLAN tag. The LLID is removed and
the appropriate VLAN tag is inserted.
The Lookup Engines process all frames at full line rate, including continuous minimum-sized frames. The LUE
tables are stored in dedicated internal SRAM.
Page 16 of 89
Rev 0.23

1.6
Packet Buffering (FIFOs)
External DDRII DRAM memory is used for packet buffering (FIFOs). The TK3723 supports 2048 packet FIFOs,
512 to each of the four FIFO destinations (2 EPON interfaces, 2 Gigabit Ethernet interfaces). Each FIFO has a
programmable size up to 1 MB, with a granularity of 4 KB.
Packets are stored in two banks of DDRII DRAM memory. Each port (channel) uses two 512 Mbit, 16-bit-wide
DDRII DRAM chips to implement a 32-bit wide, 128 MB memory array. DDRII DRAM memories are clocked at
125MHz. Both DDRII DRAM memory chips forming a single 32-bit wide data bus must have identical AC
characteristics. Each DDRII DRAM memory chip must support following features/parameters:
32M x 16-bit capacity (512Mb, 2 per port)

Operating Frequency = 125MHz (DDR)
Burst Type = Sequential
Burst Length = 8
CAS Latency (CL) = 3
Write Recovery (WR) = 2
Additive CAS Latency (AL) = 0
On-Die Termination (ODT) = 75
tAC = +/-800ps
tRCD = 16ns
tRP = 16ns
tRC = 60ns
tRFC = 105ns
Refresh Rate = 7.8125us (8192 refresh cycles every 64ms; commercial).
1.6.1
DDRII Interfaces PCB Layout Guidelines

separate bias resistors
for CLK signals
VTT
VTT
VTT
differential pairs (Zdiff = 80)

single-ended signals (Zo = 50)
must be 40mm longer than

DDR2_P1_CLK1_P/N

DDR2_P2_CLK1_P/N
VTT
separate bias resistors

for CLK signals
VTT
VTT
VTT
VTT
VTT = 0.9V
50
(2x)
50
(2x)
50
(16x)
50
(4x)
50
(4x)
DDR2_P1_U/LDQS1_P/N
DDR2_P2_DQ1_[15..0]
DDR2_P1_CLK1_P/N
DDR2_P1_DQ0_[15..0]
DDRII
(port 1, chip 0)
DDR2_P1_CLK0_P/N
4.7K
(2x)

DDR2_P1_CLK0_P/N
DDRII
(port 2, chip 1)
DDR2_P2_CLK1_P/N
TK3723
Channel 2
DDR2_P2_RAS/CAS/CS/WE_N
Channel 1
DDR2_P1_RAS/CAS/CS/WE_N
DDR2_P1_U/LDQS0_P/N
50
(2x)
DDR2_P2_A[12..0]/BA[2..0]
DDR2_P1_DQ1_[15..0]
DDR2_P1_ODT/CKE
50
(2x)
DDR2_P2_U/LDQS1_P/N
DDR2_P1_A[12..0]/BA[2..0]
DDRII
(port 1, chip 1)
50
(16x)
DDR2_P2_ODT/CKE
DDR2_P2_U/LDQS0_P/N
DDR2_P2_DQ0_[15..0]
DDRII
(port 2, chip 0)
DDR2_P2_CLK0_P/N

DDR2_P2_CLK0_P/N
4.7K
(2x)
Figure 12. TK3723 DDRII Interfaces

Following are PCB layout guidelines for DDRII interfaces (applicable to each port x independently):
Single-ended DDR2_Px_DQ0/1_[15..0] data signals should be matched in length to +/-5mm and be

shorter than 50mm (per port i.e. to both memory chips)
Differential DDR2_Px_CLK0/1_P/N signal should be matched within the differential pair to +/-1mm, and
should be matched in length with DDR2_Px_DQ0/1_[15..0] (max 50mm; +/-5mm)
Page 17 of 89
Rev 0.23

1.7
All DDR2_Px_U/LDQS0/1_P/N strobe signals should be matched within the differential pair to +/-1mm
and must be longer by 40mm than corresponding DDR2_Px_CLK0/1_P/N clock signals pairs (see Table
34 for AC timing details)
DDR2_Px_A[12..0], DDR2_Px_BA[1..0], DDR2_Px_CS_N, DDR2_Px_WE_N, DDR2_Px_RAS_N,
DDR2_Px_CAS_N, DDR2_Px_L/UDM0/1 signals should be matched in length to +/-5mm and be shorter
than 75mm
All DDRII signals must be impedance controlled. Single-ended signals must have impedance of 50
(+/-10%), and differential signals 80 (+/-10%). Differential signals are recommended to be loosely
coupled to prevent excessive impedance variations due to PCB manufacturing variability
Use biasing/termination and decoupling methods as implemented on Teknovus TK3723 evaluation
boards.
Shapers/Schedulers
The Shaper/Scheduler blocks schedule traffic as follows:
Downstream from the FIFO queues to the EPON MACs (EPON Shapers/Schedulers)
Upstream from the

Shapers/Schedulers).
FIFO
queues
to
the
Network-side
Gigabit
Ethernet
MACs
(Ethernet
Each Shaper/Scheduler supports two Shaping elements and two Scheduling elements per FIFO queue, for true
minimum and maximum-rate scheduling.
The Shaper enforces rate and burst-size parameters for each FIFO. Rates are configurable per-queue between
256 Kbps and 1 Gbps. Burst sizes are set in 1 KB increments between 1 KB and 256 KB.
The Scheduler ensures that the channel bandwidth is divided into the desired proportions. The Scheduler is a
hierarchical weighted round-robin (HWRR) design, with 8 priority levels and drop-down reservations between
priority levels. Scheduling weights have a range of 1 to 255.
In addition to the per-Queue shaper/scheduler function, the Shaper/Scheduler blocks contain per-Priority and
Aggregate shapers. The per-Priority shaper allows shaping control of all FIFOs assigned to a given Priority level.
The Aggregate shaper allows shaping of the final, summed output of each Shaper/Scheduler block.
1.8
ARM9 Processor Subsystem
The ARM9 processor is responsible for running Teknovus OLT firmware. The ARM9 processor subsystem
consists of an embedded ARM946E processor running at 125MHz, plus:
8KB Data Cache
8KB Instruction Cache
Memory Controller (interface to external 32-bit wide SDRAM and 16-bit wide FLASH)
Watchdog timer
Four general-purpose timers
UART.
Page 18 of 89
Rev 0.23

The ARM9 processor requires external FLASH (static memory) and SDRAM (dynamic memory) connected via the
32-bit wide memory interface. It requires 32 MB (8M x 32-bits, or 2 x 8M x 16-bits) of SDRAM memory and 8 MB
(4M x 16-bits) of FLASH memory.
Teknovus firmware and the OLT configuration data are stored in the FLASH. At boot time the ARM9 copies its
firmware program and OLT configuration data from the FLASH and stores in the SDRAM. After boot the ARM9
runs its program using the SDRAM memory.
The SDRAM memory is clocked at 125MHz and must have access time of less than 5.5ns with CAS Latency of 3
(CL=3). PC133 compliant SDRAM memory can work in this application.
The SDRAM memory must support following features/parameters:
256Mb capacity (8M x 32-bit, or 2 x (8M x 16-bit))

Operating Frequency = 125MHz
Burst Type = Sequential
Burst Length = 8
CAS Latency (CL) = 3
Write Recovery (WR) = 2
tAC = 5.5ns
tRAS = 56ns
tRCD = 24ns
tRP = 24ns
tRC = 72ns
tRFC = 72ns
Refresh Rate = 7.8125us (8192 refresh cycles every 64ms).
The following 256 Mb SDRAM memories are suitable for TK3723 ARM9 application:
ISSI:
o IS42S32800B-(6)/(7)B(A)(L)(I)
o IS45S32800B-7B(L)(A)(1)
Hynix:
o HY5V52A(L)F(P)-(6)/(H)
o HY5V52E(L)M(P)-(6)/(H)
o HY5V52AEMP-(6)/(H)
Micron:
o MT48LC8M32B2(F)/(B)5-6.
32-bit wide SDRAM memories are recommended in this application. Using two 16-bit wide SDRAM devices is
possible, but requires careful PCB layout and SDRAM selection (see Section 1.8.2 for more details). Both 16-bit
wide SDRAM memory chips forming a single 32-bit wide data bus must have identical AC characteristics.
The firmware requires the use of FLASH memory which supports either an AMD or Intel command set for erasing
and programming. The FLASH must have the following features:
4M x 16-bit capacity (64 Mb)
64KB or 128KB sector size (128KB sector size requires CFI-compatible command set)
AMD or Intel style programming commands
Read Access time of 84 ns or faster.
The following 64 Mb FLASH memories are confirmed to work properly and are currently supported by Teknovus
firmware:
MX29LV640DB (Macronix)
Page 19 of 89
Rev 0.23

S29JL064H (Spansion)
(TE)/(JS)/(RC)28F640J3D (Intel/Numonyx)
M29W640GB (ST Micro)
[TBD].
MC_A[0] of the ARM9 processor address bus needs to connect to the Word address of the Flash memory i.e.
MC_A[0] is a Word address (not Byte select).
1.8.1
FLASH Interface PCB Layout Guidelines
Following are PCB layout guidelines for ARM9 FLASH memory:
All FLASH signals should be matched in length to +/-10mm and be shorter than 75mm
MC_STC_SYNCOUT output must be connected via 33 series termination resistor to the
MC_STC_SYNCIN input with a trace of total length matching FLASH other signals length to +/-10mm
All FLASH signals must be impedance controlled and have impedance of 50 (+/-10%)
Use termination and decoupling methods as implemented on Teknovus TK3723 evaluation boards.
1.8.2
SDRAM Interface PCB Layout Guidelines
Following are PCB layout guidelines for ARM9 SDRAM memory:
MC_DYN_CLK signal must be shorter than 50mm and be loaded with less than 15pF total
(including TK3723 load)
MC_DYN_SYNCOUT output must be connected via 33 series termination resistor to the
MC_DYN_SYNCIN input with a trace of total length equal or longer by no more than 25mm than
MC_DYN_CLK signal
All other SDRAM signals should be matched in length to +/-10mm and be shorter than 75mm
All SDRAM signals must be impedance controlled and have impedance of 50 (+/-10%)
Use termination and decoupling methods as implemented on Teknovus TK3723 evaluation boards.
With a careful PCB layout and the SDRAM selection, it is possible to use 2 16-bit wide SDRAM memories in this
application. Since in such configuration the MC_DYN_CLK signal must be shared between two SDRAM devices,
and the total capacitive loading on this signal is still limited to 15pF, the MC_DYN_CLK trace length must be
controlled to allow following capacitance:
CTRACE 15pF - CPACKAGE - 2*(CCLK)
where:
CTRACE is total MC_DYN_CLK trace capacitance (must be calculated; usually about 2.5~3.5pF/inch)
CPACKAGE is TK3723 pin package capacitance = 2.0pF
CCLK is SDRAM memory clock input pin capacitance (from SDRAM vendors data sheet; usually about
3~4pF).
To help limit the CTRACE capacitance, installing the 2 SDRAMs on opposite sides of the PCB should be considered.
1.9
Host Interfaces
Two physical interfaces can be used by the host system to communicate with the TK3723 ARM9 processor:
Page 20 of 89
Rev 0.23

MII-based 10/100 Mbps Ethernet CRAFT port connected internally to the management FIFO. This port
provides a message-based interface to pass management, control and statistics information. The 10/100
Ethernet port can layer the management and statistics interface on UDP/IP, TCP/IP or Ethernet Layer 2.
Asynchronous Parallel Bus internally connected to the management FIFO. This interface is meant for
interfacing a generic external host processor. The host processor may reside on the line-card with the
TK3723, or it may reside beyond a backplane interface on a separate controller card.
Additionally, for system development and debug purposes, a hyper-terminal can be connected to the ARM9 via
the UART interface for Command Line Interface (CLI) access.
Both Ethernet-based and asynchronous parallel bus-based management interfaces are common backplane
architectures. Both are supported by the TK3723. However, since both interfaces share the same buffer RAM
memory, only one interface can be used at a time.
The mailbox interface is accessed through the Asynchronous Bus Interface and the 10/100 Ethernet CRAFT Port.
It provides two different physical layers to carry the same messages to the firmware. The Asynchronous Bus
requires less processing, since it does not go through a UDP/IP stack. Overhead requirements are insignificant,
since bandwidth requirements are fairly low.
The Asynchronous Parallel Bus Interface allows an external host to access the ARM9 processor. This 16-bit wide,
mailbox-based interface is memory-mapped. It allows single-word and double-word read/write cycles.
The 16-bit Asynchronous Bus interface is of little endian format; AB_D[0] is the least significant bit of the data
bus. As a 16-bit interface, AB_A[0] addresses the even/odd word (16-bits). It is the least significant bit of the
address bus. Byte access is not supported. The interface provides 11 bits of addressing. Hence, 4 Kbytes (2K x
16-bits) of address space is provided.
To connect the Asynchronous Bus to a Motorola PowerPC processors 60x bus (e.g. MPC8270VR), the following
interconnect is recommended:
AB_A[10:0] 60x_A[20:30]
AB_D[15:0] 60x_D[0:15].
Note: AB_A[0] and 60x_A[31] bits are LSB, and AB_D[15] and 60x_D[0] bits are MSB.
The mailbox interface allows the host and the TK3723 processor to enqueue management messages for the peer
processor. There are two queues in the mailbox. One queue is for messages from the Host to the ARM9
processor. The other queue is for messages from the ARM to the Host. For each message, an interrupt is
generated for the destination processor. This interrupt indicates the presence of a message which needs to be
processed. Figure 11 shows the internal blocks of the TK3723 and the external Host interface.
Page 21 of 89
Rev 0.23

Host System
16
Asynchronous Bus
MII
(CRAFT)
16
TK3723 chip
FIFO
Manager
32
TK3723
Core
32
Interrupt
Controller
Memory
Controller
ARM 9
Processor
AMBA-AHB
Figure 13. TK3723 Host Interfaces
1.10
GPIO Interface
32 GPIO pins are provided in the TK3723. These are programmable via the TK3723 Host Interface Software.
These pins can be programmed as inputs or outputs. Refer to Figure 12.
Note: Teknovus does not recommend sinking or sourcing more than 8mA on any GPIO pin.
Page 22 of 89
Rev 0.23

Figure 14. Simplified GPIO Pin Block Diagram
1.11
UART Interface
The TK3723 provides one UART interface. The UART enables debugging, and provides command line access to
the Host Interface Software. The baud rate is generated from the 125.00MHz reference oscillator. An external RS232 buffer, such as the Maxim MAX3222E, can be used to connect to a standard RS-232 connector. The
Teknovus Host Interface software default line settings are as follows. Refer to Figure 13. .
Baud Rate 9600

No-Parity
8 bit Data
1 Stop bit
The first pin, UART_DOUT, refers to UART transmit data (output) from the TK3723. The second pin, UART_DIN,
refers to UART receive data (input) to the TK3723. The UART interface is asynchronous; it does not include any
clock.
Figure 15. UART Interface Timing
Page 23 of 89
Rev 0.23

1.12
Ethernet Serial Management Interface
The Ethernet serial management interface (MDIO) consists of a data interface, basic register set, and a serial
management interface to the register set. This interface is used to control and configure multiple PHY devices,
gather status and error information, and determine the type and capabilities of the attached PHY devices.
Figure 16. MDIO Serial Management Read and Write Timing
1.13
JTAG and Test Interfaces
A standard five-port JTAG interface is provided for in-circuit testing. During normal TK3723 operation JTAG is not
functional and all JTAG pins except TRST_N should be pulled high. The TRST_N pin should be pulled low during
normal OLT operation. Please contact Teknovus for programming details.
The TK3723 implements a 4-bit instruction register that supports IEEE 1149.1 mandatory instructions BYPASS,
EXTEST and SAMPLE/PRELOAD. In addition, IDCODE and CLAMP instructions are supported. Teknovus also
supports reading the chip identity and the manufacturers identity using the JTAG interface. The following table
shows the supported instructions and their operation codes.
Table 2. JTAG Instructions
Code
0000
Instruction
EXTEST
Selected
Register
BSR
Result
Outputs cells apply their values to ports. Input cells sample values on ports
Captures 32-bit Identity with following fields:
0100
IDCODE
DEVICE
IDENTITY
0010
SAMPLE/
PRELOAD
BSR
0011
CLAMP
BSR + BYPASS
Bits
Field
Decimal
Hex
0
Default Value
1
0x1
1:11
Teknovus Identity
515
0x203
12:27
Part Number
3723
0x0E8B
28:31
Part Version
2
0x0010
Sets up the boundary scan cells to either sample values moving in or out of
devices, or preload known values in Boundary Scan cells prior to next
operation to be performed.
First preset values in output cells are taken to output ports, then BYPASS
register is selected between TDI and TDO pins.
Page 24 of 89
Rev 0.23

Code
Instruction
1111
Selected
Register
BYPASS
Result
BYPASS
TDO gets value of TDI on clock, all logic is bypassed.
Figure 15. shows the DEVICE IDENTITY register fields. Bit 0 of the 32-bit register is always 1.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
0 0 1 0 0 0 0 0 1 1 1 0 1 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1
Version
0x0010
Part Number
0x0E8B (3723)
Teknovus JEDEC Identity

0x203
Figure 17. DEVICE IDENTITY Register Fields
Page 25 of 89
Rev 0.23

TK3723 Signals Description
2.1
Signals Types
Signal Type
Type Description
I*
CMOS Input
O*
CMOS Output
I/O*
CMOS Input/Output
OD*
CMOS Open-Drain Output
O18
SSTL-18 Output
I/O18
SSTL-18 Input/Output
Power
AP
Analog Power
NC
No Connect
* All CMOS signals contain internal pull-up resistors. Internal pull-up resistor values range between 39K-85K.
2.2
Signals Names Description
Table 3. ARM9 Processor Bus Interface

Ball
Signal Name
Type
Signal Description
B4
ARM_TCK
ARM JTAG Test Clock Input. Leave unconnected (NC) for normal operation
D6
ARM_TMS
ARM JTAG Test Mode Select Input. Leave unconnected (NC) for normal operation
E7
ARM_TDI
ARM JTAG Test Data Input. Leave unconnected (NC) for normal operation
E6
ARM_TDO
ARM JTAG Test Data Output
C4
ARM_TRSTN
ARM JTAG Test Reset Input (active low). Pull-down with 1K-4.7Kohm resistor to
disable JTAG functionality
C6
EXT_PROC_N
External Processor Enable (active low). Pull up for normal operation
AH4
ARM_TM_N
ARM Processor Test Mode Select (active low). Pull up for normal operation
D7
UART_DIN
ARM Processor UART Serial Data Input
E8
UART_DOUT
ARM Processor UART Serial Data Output
AF6
B5
ARM_WDOUT_N
OD
ARM Processor Watchdog Timer Output (open-drain, active low).

Pull-up with 1K-4.7Kohms resistor and connect to either the RST_N input directly, or
to the board RESET chip input that produces RST_N signal
ARM_INT_N
I/O
This is a dual function pin (EXT_PROC_N dependant):
Internal ARM9 Processor Interrupt Input (active low)

External Processor Interrupt Output (active low)
Page 26 of 89
Rev 0.23

Ball
Signal Name
Type
I
Signal Description
AK1
ARM_RST_N
ARM Processor Reset Input (active low). Pull up for normal operation
AJ2
MC_D31
I/O
Memory Controller Data [31]
AG4
MC_D30
I/O
AE6
MC_D29
I/O
AF5
MC_D28
I/O
AJ1
MC_D27
I/O
AH2
MC_D26
I/O
AG3
MC_D25
I/O
AF4
MC_D24
I/O
AE5
MC_D23
I/O
AD6
MC_D22
I/O
AH1
MC_D21
I/O
AG2
MC_D20
I/O
AF3
MC_D19
I/O
AE4
MC_D18
I/O
AD5
MC_D17
I/O
AG1
MC_D16
I/O
AF2
MC_D15
I/O
AE3
MC_D14
I/O
AD4
MC_D13
I/O
AC5
MC_D12
I/O
AF1
MC_D11
I/O
AE2
MC_D10
I/O
AC4
MC_D9
I/O
AE1
MC_D8
I/O
AB5
MC_D7
I/O
AD2
MC_D6
I/O
AC3
MC_D5
I/O
AD1
MC_D4
I/O
AB4
MC_D3
I/O
AC2
MC_D2
I/O
AA5
MC_D1
I/O
AB3
MC_D0
I/O
Page 27 of 89
Rev 0.23

Ball
Signal Name
Type
Signal Description
AC1
MC_A26
I/O
Memory Controller Address [26]
AA4
MC_A25
I/O
AB2
MC_A24
I/O
AB1
MC_A23
I/O
Y5
MC_A22
I/O
AA3
MC_A21
I/O
AA2
MC_A20
I/O
Y4
MC_A19
I/O
AA1
MC_A18
I/O
W5
MC_A17
I/O
Y2
MC_A16
I/O
Y1
MC_A15
I/O
W4
MC_A14
I/O
W3
MC_A13
I/O
W2
MC_A12
I/O
W1
MC_A11
I/O
AG5
MC_DYN_A10
I/O
Memory Controller Dynamic Address [10] / Auto-Precharge Control
V5
MC_STC_A10
I/O
Memory Controller Static Address [10]
V4
MC_A9
I/O
V3
MC_A8
I/O
V2
MC_A7
I/O
V1
MC_A6
I/O
U5
MC_A5
I/O
U4
MC_A4
I/O
U3
MC_A3
I/O
U2
MC_A2
I/O
U1
MC_A1
I/O
T2
MC_A0
I/O
Memory Controller Address [0].

This is the FLASH memory Word address (not Byte select), and the SDRAM Byte
select.
T5
MC_STC_SYNCOUT
Memory Controller Static Sync Output.

Connect to MC_STC_SYNCIN via 33 resistor
T3
MC_STC_SYNCIN
Memory Controller Static Sync Input
E5
MC_STC_CLK
Memory Controller Static Clock Output
P5
MC_STC_CS3_N
Memory Controller Static Chip [3] Select (active low)
Page 28 of 89
Rev 0.23

Ball
Signal Name
Type
Signal Description
N1
MC_STC_CS2_N
Memory Controller Static Chip [2] Select (active low)
N2
MC_STC_CS1_N
TK3723 Chip Select (active low). Leave unconnected (NC) for normal operation
N3
MC_STC_CS0_N
Memory Controller Static Chip [0] Select (active low).

This is the internal ARM9 boot memory (FLASH) Chip Select (required)
R5
MC_STC_WE_N
I/O
Memory Controller Static Write Enable (active low)
R2
MC_STC_OE_N
I/O
Memory Controller Static Output Enable (active low)
L2
MC_STC_BSEL3_N
Memory Controller Static Byte [3] Select (active low)
M5
MC_STC_BSEL2_N
K1
MC_STC_BSEL1_N
K2
MC_STC_BSEL0_N
J1
MC_DYN_SYNCOUT*
Memory Controller Dynamic Sync Output.

Connect to MC_DYN_SYNCIN via 33 resistor
L4
MC_DYN_SYNCIN*
Memory Controller Dynamic Sync Input
AJ3
MC_DYN_CLK*
Memory Controller Dynamic Clock Output
M2
MC_DYN_CLKEN
Memory Controller Dynamic Clock Enable
P1
MC_DYN_CS3_N
Memory Controller Dynamic Chip [3] Select (active low)
P2
MC_DYN_CS2_N
P3
MC_DYN_CS1_N
P4
MC_DYN_CS0_N
Memory Controller Dynamic Chip [0] Select (active low).

This is the internal ARM9 program memory (SDRAM) Chips Select (required)
R4
MC_DYN_WE_N
I/O
Memory Controller Dynamic Write Enable (active low)
N4
MC_DYN_RAS_N
Memory Controller Dynamic Row Address Select (active low)
M1
MC_DYN_CAS_N
Memory Controller Dynamic Column Address Select (active low)
T1
MC_DYN_BA1
Memory Controller Dynamic Bank Address Select [1]
R1
MC_DYN_BA0
Memory Controller Dynamic Bank Address Select [0]
N5
MC_DYN_DQM3
Memory Controller Dynamic Data Mask [3] for R/W Access
M3
MC_DYN_DQM2
L1
MC_DYN_DQM1
M4
MC_DYN_DQM0
* Refer to Section 1.8.2 for length restrictions for these signals.
Table 4. Inter-Processor Asynchronous Bus Interface

Ball
AL31
Signal Name
AB_CS_N
Type
I*
Signal Description
Asynchronous Bus Chip Select (active low)
Page 29 of 89
Rev 0.23

Ball
Signal Name
Type
Signal Description
AK30
AB_WE_N
Asynchronous Bus Write Enable (active low)
AL32
AB_OE_N
Asynchronous Bus Output Enable (Read Enable) (active low)
AJ29
AB_INT_N
Asynchronous Bus Interrupt (active low)
AM32
AB_A10
Asynchronous Bus Address [10]
AK29
AB_A9
AL30
AB_A8
AM31
AB_A7
AN32
AB_A6
AK28
AB_A5
AL29
AB_A4
AN31
AB_A3
AK27
AB_A2
AL28
AB_A1
AM29
AB_A0
AJ33
AB_D15
I/O
Asynchronous Bus Data [15]
AK34
AB_D14
I/O
AF29
AB_D13
I/O
AG30
AB_D12
I/O
AH31
AB_D11
I/O
AJ32
AB_D10
I/O
AK33
AB_D9
I/O
AL34
AB_D8
I/O
AG29
AB_D7
I/O
AH30
AB_D6
I/O
AJ31
AB_D5
I/O
AK32
AB_D4
I/O
AL33
AB_D3
I/O
AH29
AB_D2
I/O
AJ30
AB_D1
I/O
AK31
AB_D0
I/O
* Pull up when not used.
Table 5. Ethernet Serial Management Interface
Page 30 of 89
Rev 0.23

Ball
Signal Name
Type
Signal Description
AK11
MDIO_DATA
I/O
Management Serial Data I/O. I/O data for PHY(s) registers access
AN9
MDIO_CLK
Management Serial Data Clock. Clock for PHY(s) registers access
Table 6. Management Port (CRAFT) MII Interface

Ball
Signal Name
Type
Signal Description
AP5
MII_RXD0
Receive Data [0] from PHY
AN6
MII_RXD1
AM7
MII_RXD2
AK9
MII_RXD3
AK8
MII_RXDV
Receive Data Valid from PHY
AL7
MII_RXER
Receive Error from PHY
AP6
MII_RXCLK
I*
25MHz/2.5MHz Receive Clock from PHY
AN7
MII_TXD0
Transmit Data [0] to PHY
AM8
MII_TXD1
AK10
MII_TXD2
AN8
MII_TXD3
AM9
MII_TXEN
Transmit Data Enable to PHY
AL10
MII_TXER
Transmit Error to PHY
AL8
MII_TXCLK
I*
25MHz/2.5MHz Transmit Clock from PHY
* When not used, pull down both clock inputs with the 1K-4.7Kohm resistors, and leave all other MII pins unconnected (NC).
Table 7. Local-Side PHY/SerDes MII/GMII/TBI Interface - Port 1
Note: Data flows are named Downstream (DN) or Upstream (UP), relative to the EPON fiber.
Ball
AK2
Signal Name
LOC_P1_DNRBC0
Type
I*
Signal Description
This is a triple function pin:
AL2
LOC_P1_DNRBC1
I*
MII: 25.0MHz Receive Clock. Generated by PHY to clock-in

LOC_P1_DND[3:0], LOC_P1_DNER, and LOC_P1_DNEN
GMII: 125MHz Receive Clock. Generated by PHY to clock-in
TBI: 62.5MHz Receive RBC0 Clock. Generated by SerDes to clock-in
LOC_P1_DND[9:0] (odd code)
MII: 25.0MHz Transmit Clock. Generated by PHY to clock-out

LOC_P1_UPD[3:0], LOC_P1_UPER, and LOC_P1_UPDV
LOC_P1_DND[9:0] (even code)
GMII: unused; pull down with 1K- 4.7Kohm resistor
Page 31 of 89
Rev 0.23

Ball
AM2
Signal Name
LOC_P1_DNER /
Type
I
LOC_P1_DNEN /
LOC_P1_DND7
LOC_P1_DND6
LOC_P1_DND5
LOC_P1_DND4
TBI/GMII: Downstream Receive Data [6]

MII: unused; leave unconnected (NC)
This is a dual function pin:
AK4

AJ5
GMII/MII: Downstream Receive Data Enable

TBI: Downstream Receive Data [8]
AH6
GMII/MII: Downstream Receive Data Error

LOC_P1_DND8
AK5
LOC_P1_DND9
AJ6
Signal Description


AJ4
LOC_P1_DND3
MII/GMII/TBI: Downstream Receive Data [3]
AG6
LOC_P1_DND2
AH5
LOC_P1_DND1
AK3
LOC_P1_DND0
AL4
LOC_P1_DNCOMDET
AM3
LOC_P1_UPCLK
AM6
LOC_P1_UPER /
AN5
LOC_P1_UPDV /
AP4
LOC_P1_UPD7
LOC_P1_UPD6
GMII/MII: Upstream Transmit Data Valid

TBI: Upstream Transmit Data [8]
AK7
GMII/MII: Upstream Data Error

LOC_P1_UPD8
GMII: 125MHz Transmit Clock. Used by Gigabit PHY for clocking-in

LOC_P1_UPD[7:0], LOC_P1_UPER, and LOC_P1_UPEN
TBI: 125MHz Transmit/Reference Clock. Used by SerDes for clocking-in
LOC_P1_UPD[9:0]
LOC_P1_UPD9
TBI (MAC mode): Downstream Receive Comma Character Detect

MII/GMII: unused; leave unconnected (NC)
TBI/GMII: Upstream Transmit Data [7]


Page 32 of 89
Rev 0.23

Ball
AL6
Signal Name
LOC_P1_UPD5
Type
O
Signal Description
AN4
LOC_P1_UPD4


AN3
LOC_P1_UPD3
MII/GMII/TBI: Upstream Transmit Data [3]
AM4
LOC_P1_UPD2
AL5
LOC_P1_UPD1
AK6
LOC_P1_UPD0
* When not used, pull down both clock inputs with the 1K-4.7Kohm resistors, and leave all other LOC_P1 pins unconnected (NC).
Table 8. Plant-Side SerDes Interface Port 1

Ball
Signal Name
Type
Signal Description
AC32
PLA_P1_UPD9
TBI Receive Data [9] from Plant-Side SerDes
AB30
PLA_P1_UPD8
AD33
PLA_P1_UPD7
AC31
PLA_P1_UPD6
AE34
PLA_P1_UPD5
AE33
PLA_P1_UPD4
AF34
PLA_P1_UPD3
AC30
PLA_P1_UPD2
AD31
PLA_P1_UPD1
AE32
PLA_P1_UPD0
AD34
PLA_P1_UPRBC0
I*
125MHz/62.5MHz TBI Receive Clock from Plant-Side SerDes
AB31
PLA_P1_UPRBC1
I*
62.5MHz TBI Receive Clock from Plant-Side SerDes
AC33
PLA_P1_UPSIGDET
Signal Detect from Plant-Side SerDes (optional; not used in EPON application), leave
unconnected (NC) if not used
PLA_P1_DND19
In 2.5 Gbps mode this is a dual function pin:
V31
16+2 bit mode: unused; leave unconnected (NC)

20 bit mode (2xTBI): upper-order 10B code bit [9] to Plant-Side SerDes

10 bit mode (TBI): duplicate PLA_P1_DND9 signal
Page 33 of 89
Rev 0.23

Ball
V30
Signal Name
PLA_P1_DND18
Type
O
Signal Description

W34
PLA_P1_DND17 /
PLA_P1_KMSB

16+2
bit
mode:
K-code
indicator
for
upper-order
byte
(PLA_P1_DND[15..8]) to Plant-Side SerDes
W33
PLA_P1_DND16 /
PLA_P1_KLSB
8+1 bit mode: duplicate PLA_P1_DND16 signal

16+2 bit mode: K-code indicator for lower-order byte (PLA_P1_DND[7..0])

to Plant-Side SerDes
W32
PLA_P1_DND15

16+2 bit mode: upper-order data/K-code byte bit [7] to Plant-Side SerDes
W31
PLA_P1_DND14

Y34
PLA_P1_DND13

W30
PLA_P1_DND12


Page 34 of 89
Rev 0.23

Ball
Y33
Signal Name
PLA_P1_DND11
Type
O
Signal Description
AA34
PLA_P1_DND10

Y31
PLA_P1_DND9

20 bit mode (2xTBI): lower-order 10B code bit [9] to Plant-Side SerDes
In 1.25Gbsp mode this is a dual function pin:
AA33
PLA_P1_DND8

10 bit mode (TBI): 10B code bit [9] to Plant-Side SerDes
Y30
PLA_P1_DND7

16+2 bit mode: lower-order data/K-code byte bit [7] to Plant-Side SerDes
AA32
PLA_P1_DND6
8+1 bit mode: data/K-code byte bit [7] to Plant-Side SerDes

AB34
PLA_P1_DND5


Page 35 of 89
Rev 0.23

Ball
AA31
Signal Name
PLA_P1_DND4
Type
O
Signal Description
AB33
PLA_P1_DND3

AC34
PLA_P1_DND2

AA30
PLA_P1_DND1

AB32
PLA_P1_DND0

V32
PLA_P1_DNCLK
O**

125MHz Transmit Clock to Plant-Side SerDes
* When not used, pull down both clock inputs with the 1K-4.7Kohm resistors, and leave all other PLA_P1 pins unconnected (NC).
** Not recommended to be used as a reference clock source to an external SerDes IC.
Table 9. Ethernet PON Transceiver Interface Port 1

Ball
Signal Name
Type
Signal Description
V33
PLA_P1_DNRECCLK
Programmable CDR reset strobe to the Plant-Side SerDes
V34
PLA_P1_DNRECTHR
Programmable AGC reset strobe to the Plant-Side optical receiver
U30
PLA_P1_DNRECSTRB0
Programmable General Purpose Receive Strobe [0]
U31
PLA_P1_DNRECSTRB1
U32
PLA_P1_RANGESTRB
Range Time Slot Strobe (asserted during entire range time slot)
Page 36 of 89
Rev 0.23

Ball
Signal Name
Type
U33
PLA_P1_UNASSIGNSTRB
Grant Time Slot Strobe (asserted during unassigned grant time slot)
AG31
P1_DEBUG15
I/O
Reserved for future use
AF30
P1_DEBUG14
I/O
AE29
P1_DEBUG13
I/O
AJ34
P1_DEBUG12
I/O
AH33
P1_DEBUG11
I/O
AG32
P1_DEBUG10
I/O
AF31
P1_DEBUG9
I/O
AE30
P1_DEBUG8
I/O
AD29
P1_DEBUG7
I/O
AH34
P1_DEBUG6
I/O
AG33
P1_DEBUG5
I/O
AF32
P1_DEBUG4
I/O
AE31
P1_DEBUG3
I/O
AD30
P1_DEBUG2
I/O
AG34
P1_DEBUG1
I/O
AF33
P1_DEBUG0
I/O
Table 10.
Ball
Signal Description
Packet Buffer DDRII DRAM Interface Port 1

Signal Name
Type
Signal Description
Port 1 DDRII DRAM 0 and 1 Common Signals

AM16
DDR2_P1_CKE
O18
Packet Buffer DRAMs Clock Enable
AP18
DDR2_P1_CS_N
O18
Packet Buffer DRAMs Chip Select (active low)
AN18
DDR2_P1_RAS_N
O18
Packet Buffer DRAMs Row Address Select (active low)
AM18
DDR2_P1_CAS_N
O18
Packet Buffer DRAMs Column Address Select (active low)
AL18
DDR2_P1_WE_N
O18
Packet Buffer DRAMs Write Enable (active low)
AP17
DDR2_P1_LDM
O18
Packet Buffer DRAMs Lower Byte Data Mask
AN17
DDR2_P1_UDM
O18
Packet Buffer DRAMs Upper Byte Data Mask
AN16
DDR2_P1_ODT
O18
Packet Buffer DRAMs On-Die-Termination Enable
AN20
DDR2_P1_BA2
O18
Packet Buffer DRAMs Bank Address [2]
AM19
DDR2_P1_BA1
O18
AN19
DDR2_P1_BA0
O18
AM24
DDR2_P1_A12
O18
Packet Buffer DRAMs Address [12]
Page 37 of 89
Rev 0.23

Ball
Signal Name
Type
Signal Description
AN25
DDR2_P1_A11
O18
AL22
DDR2_P1_A10
O18
AM23
DDR2_P1_A9
O18
AN24
DDR2_P1_A8
O18
AN23
DDR2_P1_A7
O18
AL21
DDR2_P1_A6
O18
AM22
DDR2_P1_A5
O18
AN22
DDR2_P1_A4
O18
AL20
DDR2_P1_A3
O18
AN21
DDR2_P1_A2
O18
AM20
DDR2_P1_A1
O18
AL19
DDR2_P1_A0
O18
AL17
DDR2_P1_IMPREF
AP
DDRII Port 1 Impedance Reference (connect to GND via 294, 1% resistor)
Port 1 DDRII DRAM 0 Signals

AP11
DDR2_P1_CLK0_P
AP12
DDR2_P1_CLK0_N
AP8
DDR2_P1_LDQS0_P
AP9
DDR2_P1_LDQS0_N
AP14
DDR2_P1_UDQS0_P
AP15
DDR2_P1_UDQS0_N
AL16
DDR2_P1_DQ0_15
I/O18
Packet Buffer DRAM Data [15]
AN15
DDR2_P1_DQ0_14
I/O18
AM15
DDR2_P1_DQ0_13
I/O18
AL15
DDR2_P1_DQ0_12
I/O18
AN14
DDR2_P1_DQ0_11
I/O18
AL14
DDR2_P1_DQ0_10
I/O18
AN13
DDR2_P1_DQ0_9
I/O18
AM13
DDR2_P1_DQ0_8
I/O18
AL13
DDR2_P1_DQ0_7
I/O18
AN12
DDR2_P1_DQ0_6
I/O18
AM12
DDR2_P1_DQ0_5
I/O18
AL12
DDR2_P1_DQ0_4
I/O18
AM11
DDR2_P1_DQ0_3
I/O18
AN10
DDR2_P1_DQ0_2
I/O18
O18*
I/O18*
I/O18*
Packet Buffer DRAM Differential Clock (active high)

Packet Buffer DRAM Differential Clock (active low)
Packet Buffer DRAM Lower Byte Differential Data Strobe (active high)
Packet Buffer DRAM Lower Byte Differential Data Strobe (active low)
Packet Buffer DRAM Upper Byte Differential Data Strobe (active high)
Packet Buffer DRAM Upper Byte Differential Data Strobe (active low)
Page 38 of 89
Rev 0.23

Ball
Signal Name
Type
Signal Description
AL11
DDR2_P1_DQ0_1
I/O18
AM10
DDR2_P1_DQ0_0
I/O18
AK14
DDR2_P1_VREF0
AP
0.9V DDRII Port 1 DRAM 0 Input Reference Voltage (VDD_P1_VQ / 2)

AP23
DDR2_P1_CLK1_P
AP24
DDR2_P1_CLK1_N
AP20
DDR2_P1_LDQS1_P
AP21
DDR2_P1_LDQS1_N
AP26
DDR2_P1_UDQS1_P
AP27
DDR2_P1_UDQS1_N
AN30
DDR2_P1_DQ1_15
I/O18
AP31
DDR2_P1_DQ1_14
I/O18
AK26
DDR2_P1_DQ1_13
I/O18
AL27
DDR2_P1_DQ1_12
I/O18
AN29
DDR2_P1_DQ1_11
I/O18
AK25
DDR2_P1_DQ1_10
I/O18
AP30
DDR2_P1_DQ1_9
I/O18
AM27
DDR2_P1_DQ1_8
I/O18
AK24
DDR2_P1_DQ1_7
I/O18
AN28
DDR2_P1_DQ1_6
I/O18
AP29
DDR2_P1_DQ1_5
I/O18
AM26
DDR2_P1_DQ1_4
I/O18
AN27
DDR2_P1_DQ1_3
I/O18
AM25
DDR2_P1_DQ1_2
I/O18
AN26
DDR2_P1_DQ1_1
I/O18
AL23
DDR2_P1_DQ1_0
I/O18
AK21
DDR2_P1_VREF1
AP
O18*
I/O18*
I/O18*

* Differential Pairs. Refer to Section 1.6.1 for layout guidelines for these signals.
Table 11.
Local-Side PHY/SerDes MII/GMII/TBI Interface Port 2
Note: Data flows are named Downstream (DN) or Upstream (UP), relative to the EPON fiber.
Ball
Signal Name
Type
Signal Description
Page 39 of 89
Rev 0.23

Ball
G1
Signal Name
LOC_P2_DNRBC0
Type
I*
Signal Description
G5
LOC_P2_DNRBC1
I*
H3
LOC_P2_DNER /
J5
LOC_P2_DNEN /
G2
LOC_P2_DND7
LOC_P2_DND6
LOC_P2_DND5
LOC_P2_DND4

J6

F1
GMII/MII: Downstream Receive Data Enable

H4
GMII/MII: Downstream Receive Data Error

LOC_P2_DND8
MII: 25.0MHz Transmit Clock. Generated by PHY to clock-out

LOC_P2_UPD[3:0], LOC_P2_UPER, and LOC_P2_UPDV
LOC_P2_DND[9:0] (even code)
GMII: unused; pull down with 1K- 4.7Kohm resistor
LOC_P2_DND9
MII: 25.0MHz Receive Clock. Generated by PHY to clock-in

GMII: 125MHz Receive Clock. Generated by PHY to clock-in
LOC_P2_DND[9:0] (odd code)


F2
LOC_P2_DND3
H5
LOC_P2_DND2
G4
LOC_P2_DND1
H6
LOC_P2_DND0
K6
LOC_P2_DNCOMDET
G6
LOC_P2_UPCLK
TBI (MAC mode): Downstream Receive Comma Character Detect

MII/GMII: unused; leave unconnected (NC)
GMII: 125MHz Transmit Clock. Used by Gigabit PHY for clocking-in

LOC_P2_UPD[7:0], LOC_P2_UPER, and LOC_P2_UPEN
TBI: 125MHz Transmit Clock. Used by SerDes for clocking-in
LOC_P2_UPD[9:0]
Page 40 of 89
Rev 0.23

Ball
K3
Signal Name
LOC_P2_UPER /
Type
O
LOC_P2_UPDV /
LOC_P2_UPD7
LOC_P2_UPD6
LOC_P2_UPD5
LOC_P2_UPD4

H1

L6
GMII/MII: Upstream Transmit Data Valid

K4
GMII/MII: Upstream Data Error

LOC_P2_UPD8
J2
LOC_P2_UPD9
L5
Signal Description


J3
LOC_P2_UPD3
K5
LOC_P2_UPD2
H2
LOC_P2_UPD1
J4
LOC_P2_UPD0
* When not used, pull down both clock inputs with the 1K-4.7Kohm resistors, and leave all other LOC_P2 pins unconnected.
Table 12.
Ball
Plant-Side SerDes Interface Port 2

Signal Name
Type
Signal Description
L33
PLA_P2_UPD9
M31
PLA_P2_UPD8
L34
PLA_P2_UPD7
M32
PLA_P2_UPD6
N30
PLA_P2_UPD5
M33
PLA_P2_UPD4
N31
PLA_P2_UPD3
M34
PLA_P2_UPD2
N32
PLA_P2_UPD1
N33
PLA_P2_UPD0
K34
PLA_P2_UPRBC0
I*
125MHz/62.5MHz TBI Receive Clock from Plant-Side SerDes
Page 41 of 89
Rev 0.23

Ball
Signal Name
Type
Signal Description
M30
PLA_P2_UPRBC1
I*
62.5MHz TBI Receive Clock from Plant-Side SerDes
K33
PLA_P2_UPSIGDET
Signal Detect from Plant-Side SerDes (optional)
J29
PLA_P2_DND19

F33
PLA_P2_DND18


H31
PLA_P2_DND17 /
PLA_P2_KMSB

16+2
bit
mode:
K-code
indicator
for
upper-order
byte
(PLA_P2_DND[15..8]) to Plant-Side SerDes
F34
PLA_P2_DND16 /
PLA_P2_KLSB


J30
PLA_P2_DND15

G33
PLA_P2_DND14


Page 42 of 89
Rev 0.23

Ball
K29
Signal Name
PLA_P2_DND13
Type
O
Signal Description
H32
PLA_P2_DND12

J31
PLA_P2_DND11

H33
PLA_P2_DND10

K30
PLA_P2_DND9

J32
PLA_P2_DND8

L29
PLA_P2_DND7


Page 43 of 89
Rev 0.23

Ball
H34
Signal Name
PLA_P2_DND6
Type
O
Signal Description
K31
PLA_P2_DND5

J33
PLA_P2_DND4

L30
PLA_P2_DND3

K32
PLA_P2_DND2

J34
PLA_P2_DND1

L31
PLA_P2_DND0

D34
PLA_P2_DNCLK
O**

125MHz Transmit Clock to Plant-Side SerDes
* When not used, pull down both clock inputs with the 1K-4.7Kohm resistors, and leave all other PLA_P2 pins unconnected (NC).
Page 44 of 89
Rev 0.23

** Not recommended to be used as a reference clock source to an external SerDes IC.
Table 13.
Ethernet PON Transceiver Interface Port 2
Ball
Signal Name
H30
PLA_P2_DNRECCLK
Programmable CDR reset strobe to the Plant-Side SerDes
G31
PLA_P2_DNRECTHR
Programmable AGC reset strobe to the Plant-Side optical receiver
F32
PLA_P2_DNRECSTRB0
H29
PLA_P2_DNRECSTRB1
G30
PLA_P2_RANGESTRB
Range Time Slot Strobe (asserted during entire range time slot)
G29
PLA_P2_UNASSIGNSTRB
Grant Time Slot Strobe (asserted during unassigned grant time slot)
U34
P2_DEBUG15
I/O
T34
P2_DEBUG14
I/O
T33
P2_DEBUG13
I/O
T32
P2_DEBUG12
I/O
T31
P2_DEBUG11
I/O
T30
P2_DEBUG10
I/O
R34
P2_DEBUG9
I/O
R33
P2_DEBUG8
I/O
R31
P2_DEBUG7
I/O
R30
P2_DEBUG6
I/O
P34
P2_DEBUG5
I/O
P33
P2_DEBUG4
I/O
P32
P2_DEBUG3
I/O
P31
P2_DEBUG2
I/O
N34
P2_DEBUG1
I/O
P30
P2_DEBUG0
I/O
Table 14.
Ball
Type
Signal Description
Packet Buffer DDRII DRAM Interface Port 2

Signal Name
Type
Signal Description
Port 2 DDRII DRAM 0 and 1 Common Signals

C20
DDR2_P2_CKE
O18
Packet Buffer DRAMs Clock Enable
D18
DDR2_P2_CS_N
O18
Packet Buffer DRAMs Chip Select (active low)
B18
DDR2_P2_RAS_N
O18
Packet Buffer DRAMs Row Address Select (active low)
A18
DDR2_P2_CAS_N
O18
Packet Buffer DRAMs Column Address Select (active low)
Page 45 of 89
Rev 0.23

Ball
Signal Name
Type
Signal Description
A17
DDR2_P2_WE_N
O18
Packet Buffer DRAMs Write Enable (active low)
D19
DDR2_P2_LDM
O18
Packet Buffer DRAMs Lower Byte Data Mask
C19
DDR2_P2_UDM
O10
Packet Buffer DRAMs Upper Byte Data Mask
B20
DDR2_P2_ODT
O18
Packet Buffer DRAMs On-Die-Termination Enable
D17
DDR2_P2_BA2
O18
C17
DDR2_P2_BA1
O18
B17
DDR2_P2_BA0
O18
C12
DDR2_P2_A12
O18
B11
DDR2_P2_A11
O18
B12
DDR2_P2_A10
O18
C13
DDR2_P2_A9
O18
D14
DDR2_P2_A8
O18
B13
DDR2_P2_A7
O18
D15
DDR2_P2_A6
O18
B14
DDR2_P2_A5
O18
C15
DDR2_P2_A4
O18
B15
DDR2_P2_A3
O18
D16
DDR2_P2_A2
O18
C16
DDR2_P2_A1
O18
B16
DDR2_P2_A0
O18
B19
DDR2_P2_IMPREF
AP
DDRII Port 2 Impedance Reference (connect to GND via 294, 1% resistor)

A24
DDR2_P2_CLK0_P
A23
DDR2_P2_CLK0_N
A27
DDR2_P2_LDQS0_P
A26
DDR2_P2_LDQS0_N
A21
DDR2_P2_UDQS0_P
A20
DDR2_P2_UDQS0_N
B21
DDR2_P2_DQ0_15
I/O18
D20
DDR2_P2_DQ0_14
I/O18
B22
DDR2_P2_DQ0_13
I/O18
D21
DDR2_P2_DQ0_12
I/O18
B23
DDR2_P2_DQ0_11
I/O18
D22
DDR2_P2_DQ0_10
I/O18
O18*
I/O18*
I/O18*

Page 46 of 89
Rev 0.23

Ball
Signal Name
Type
Signal Description
C23
DDR2_P2_DQ0_9
I/O18
B24
DDR2_P2_DQ0_8
I/O18
C24
DDR2_P2_DQ0_7
I/O18
D23
DDR2_P2_DQ0_6
I/O18
B25
DDR2_P2_DQ0_5
I/O18
B26
DDR2_P2_DQ0_4
I/O18
D24
DDR2_P2_DQ0_3
I/O18
C25
DDR2_P2_DQ0_2
I/O18
B27
DDR2_P2_DQ0_1
I/O18
C26
DDR2_P2_DQ0_0
I/O18
E21
DDR2_P2_VREF0
AP

A12
DDR2_P2_CLK1_P
A11
DDR2_P2_CLK1_N
A15
DDR2_P2_LDQS1_P
A14
DDR2_P2_LDQS1_N
A9
DDR2_P2_UDQS1_P
A8
DDR2_P2_UDQS1_N
C7
DDR2_P2_DQ1_15
I/O18
B6
DDR2_P2_DQ1_14
I/O18
E10
DDR2_P2_DQ1_13
I/O18
C8
DDR2_P2_DQ1_12
I/O18
E11
DDR2_P2_DQ1_11
I/O18
A6
DDR2_P2_DQ1_10
I/O18
D10
DDR2_P2_DQ1_9
I/O18
C9
DDR2_P2_DQ1_8
I/O18
B8
DDR2_P2_DQ1_7
I/O18
D11
DDR2_P2_DQ1_6
I/O18
C10
DDR2_P2_DQ1_5
I/O18
B9
DDR2_P2_DQ1_4
I/O18
D12
DDR2_P2_DQ1_3
I/O18
C11
DDR2_P2_DQ1_2
I/O18
B10
DDR2_P2_DQ1_1
I/O18
D13
DDR2_P2_DQ1_0
I/O18
O18*
I/O18*
I/O18*

Page 47 of 89
Rev 0.23

Ball
E14
Signal Name
DDR2_P2_VREF1
Type
AP
Signal Description
* Differential Pairs. Refer to Section 1.6.1 for layout guidelines for these signals.
Table 15.
JTAG and Test Interface
Ball
Signal Name
Type
Signal Description
E4
TM_N
Test Mode Select Input (active low). Pull up for normal operation
D3
SM_N
Scan Mode Select Input (active low). Pull up for normal operation
D2
TCK
JTAG Test Clock Input. Leave unconnected (NC) for normal operation
E3
TMS
JTAG Test Mode Select Input. Leave unconnected (NC) for normal operation
E2
TDI
JTAG Test Data Input. Leave unconnected (NC) for normal operation
F3
TDO
JTAG Test Data Output
F4
TRSTN
JTAG Test Reset Input (active low). Pull down with 1K-4.7Kohm resistor to disable
JTAG functionality
Table 16.
Ball
Reference Clocks, System Reset, PLL and GPIO Interface

Signal Name
Type
Signal Description
D1
CLK_125
125MHz Reference Clock Input
E1
CLK_125_OUT
125MHz Clock Output (based on CLK_125 input)
D5
CLK_25_OUT
25MHz Clock Output (derived from CLK_125 input). This output clock can be used as
REF_CLK input to external GMII/MII PHY(s).
D8
PLL_BYPASS_N
Internal PLL Bypass Control (active low). Pull up for normal operation.
E9
RST_N
Global Reset Input (active low)
E24
GPIO31
I/O
General Purpose I/O [31] (default input)
A29
GPIO30
I/O
B28
GPIO29
I/O
C27
GPIO28
I/O
E25
GPI27
A30
GPIO26
I/O
B29
GPIO25
I/O
C28
GPIO24
I/O
D27
GPIO23
I/O
E26
GPIO22
I/O
A31
GPIO21
I/O
B30
GPIO20
I/O
General Purpose Input [27] (restricted to input only)
Page 48 of 89
Rev 0.23

Ball
Signal Name
Type
Signal Description
C29
GPIO19
I/O
D28
GPIO18
I/O
E27
GPIO17
I/O
B31
GPIO16
I/O
D29
GPIO15
I/O
B32
GPIO14
I/O
E28
GPIO13
I/O
C31
GPIO12
I/O
D30
GPIO11
I/O
E29
GPIO10
I/O
C32
GPIO9
I/O
D31
GPIO8
I/O
C33
GPIO7
I/O
E30
GPIO6
I/O
D32
GPIO5
I/O
E31
GPIO4
I/O
D33
GPIO3
I/O
E32
GPIO2
I/O
E33
GPIO1
I/O
E34
GPIO0
I/O
Table 17.
Power and Ground

Ball
AB6, AB29, AC6, AC29, AE7, AE28,

AF7, AF28, AH7, AH8, AH27, AH28,
AL3, AM33, D4, F30, G7, G8, G27,
G28, J7, J28, K7, K28, M6, M29, N6,
N29, R6, R29, T6, T29, W6, W29, Y6,
Y29
Signal Name
VDDIO
Type
P
Signal Description
3.3V I/O Power Supply (36 signals)
Page 49 of 89
Rev 0.23

Ball
Signal Name
Type
Signal Description
AA6, AA7, AA28, AA29, AB7, AB28,

AC7, AC28, AD7, AD8, AD27, AD28,
AE8, AE27, AF8, AF27, AG7, AG8,
AG9, AG10, AG11, AG24, AG25,
AG26, AG27, AG28, AH12, AH13,
AH14, AH15, AH16, AH17, AH18,
AH19, AH20, AH21, AH22, AH23, G12,
G13, G14, G15, G16, G17, G18, G19,
G20, G21, G22, G23, H7, H8, H9, H10,
H11, H24, H25, H26, H27, H28, J8,
J27, K8, K27, L7, L8, L27, L28, M7,
M28, N7, N28, P6, P7, P28, P29, R7,
R28, T7, T28, U6, U7, U28, U29, V6,
V7, V28, V29, W7, W28, Y7, Y28
VDDCORE
1.2V Core Power Supply (92 signals)
AH9, AH10, AH11, AH24, AH25, AH26,

AJ12, AJ13, AJ14, AJ15, AJ16, AJ17,
AJ18, AJ19, AJ20, AJ21, AJ22, AJ23
VDD_P1_VQ
1.8V DDRII Port 1 I/O Power Supply (18 signals)
F12, F13, F14, F15, F16, F17, F18,

F19, F20, F21, F22, F23, G9, G10,
G11, G24, G25, G26
VDD_P2_VQ
AL24, AM28, AN11
VDD_P1_VD
P*
B7, C22, D25
VDD_P2_VD
P*
AJ11, AJ25, AJ26, AK12, AK16, AK19,

AK23
VDD_P1_AV
P*
3.3V Port 1 Internal Memories Power Supply (7 signals)
E12, E16, E19, E23, F9, F11, F24
VDD_P2_AV
P*
3.3V Port 2 Internal Memories Power Supply (7 signals)
A5
AVDD
AP*
3.3V PLL Analog Power Supply
A4
AGND
AP
Ground PLL Analog Supply
Page 50 of 89
Rev 0.23

Ball
A2, A3, A7, A10, A13, A16, A19, A22,
A25, A28, A32, A33, A34, AA12, AA13,
AA14, AA15, AA16, AA17, AA18, AA19,
AA20, AA21, AA22, AA23, AB12, AB13,
AB14, AB15, AB16, AB17, AB18, AB19,
AB20, AB21, AB22, AB23, AC12,
AC13, AC14, AC15, AC16, AC17,
AC18, AC19, AC20, AC21, AC22,
AC23, AD3, AD32, AH3, AH32, AJ7,
AJ8, AJ9, AJ10, AJ24, AJ27, AJ28,
AK13, AK15, AK17, AK18, AK20, AK22,
AL1, AL9, AL25, AL26, AM1, AM5,
AM14, AM17, AM21, AM30, AM34,
AN1, AN2, AN33, AN34, AP1, AP2,
AP3, AP7, AP10, AP13, AP16, AP19,
AP22, AP25, AP28, AP32, AP33, AP34,
B1, B2, B3, B33, B34, C1, C2, C3, C5,
C14, C18, C21, C30, C34, D9, D26,
E13, E15, E17, E18, E20, E22, F5, F6,
F7, F8, F10, F25, F26, F27, F28, F29,
F31, G3, G32, G34, L3, L32, M12, M13,
M14, M15, M16, M17, M18, M19, M20,
M21, M22, M23, N12, N13, N14, N15,
N16, N17, N18, N19, N20, N21, N22,
N23, P12, P13, P14, P15, P16, P17,
P18, P19, P20, P21, P22, P23, R3,
R12, R13, R14, R15, R16, R17, R18,
R19, R20, R21, R22, R23, R32, T4,
T12, T13, T14, T15, T16, T17, T18,
T19, T20, T21, T22, T23, U12, U13,
U14, U15, U16, U17, U18, U19, U20,
U21, U22, U23, V12, V13, V14, V15,
V16, V17, V18, V19, V20, V21, V22,
V23, W12, W13, W14, W15, W16, W17,
W18, W19, W20, W21, W22, W23, Y3,
Y12, Y13, Y14, Y15, Y16, Y17, Y18,
Y19, Y20, Y21, Y22, Y23, Y32
Signal Name
GND
Type
P
Signal Description
Ground Supply (246 signals)
* These power groups should be filtered individually with a suitable power filter. Noise amplitude must be limited to 50mV (peak-to-peak;
50KHz-125MHz).
Page 51 of 89
Rev 0.23

2.3
Signals Sorted in Ball Numerical Order
Table 18.
Signals Sorted in Ball Numerical Order
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
A10
GND
AA15
GND
AB29
VDDIO
A11
DDR2_P2_CLK1_N
AA16
GND
AB3
MC_D0
A12
DDR2_P2_CLK1_P
AA17
GND
AB30
PLA_P1_UPD8
A13
GND
AA18
GND
AB31
PLA_P1_UPRBC1
A14
DDR2_P2_LDQS1_N
AA19
GND
AB32
PLA_P1_DND0
A15
DDR2_P2_LDQS1_P
AA2
MC_A20
AB33
PLA_P1_DND3
A16
GND
AA20
GND
AB34
PLA_P1_DND5
A17
DDR2_P2_WE_N
AA21
GND
AB4
MC_D3
A18
DDR2_P2_CAS_N
AA22
GND
AB5
MC_D7
A19
GND
AA23
GND
AB6
VDDIO
A2
GND
AA28
VDDCORE
AB7
VDDCORE
A20
DDR2_P2_UDQS0_N
AA29
VDDCORE
AC1
MC_A26
A21
DDR2_P2_UDQS0_P
AA3
MC_A21
AC12
GND
A22
GND
AA30
PLA_P1_DND1
AC13
GND
A23
DDR2_P2_CLK0_N
AA31
PLA_P1_DND4
AC14
GND
A24
DDR2_P2_CLK0_P
AA32
PLA_P1_DND6
AC15
GND
A25
GND
AA33
PLA_P1_DND8
AC16
GND
A26
DDR2_P2_LDQS0_N
AA34
PLA_P1_DND10
AC17
GND
A27
DDR2_P2_LDQS0_P
AA4
MC_A25
AC18
GND
A28
GND
AA5
MC_D1
AC19
GND
A29
GPIO30
AA6
VDDCORE
AC2
MC_D2
AA7
VDDCORE
AC20
GND
A3
GND
A30
GPIO26
AB1
MC_A23
AC21
GND
A31
GPIO21
AB12
GND
AC22
GND
A32
GND
AB13
GND
AC23
GND
A33
GND
AB14
GND
AC28
VDDCORE
A34
GND
AB15
GND
AC29
VDDIO
A4
AGND
AB16
GND
AC3
MC_D5
A5
AVDD
AB17
GND
AC30
PLA_P1_UPD2
A6
DDR2_P2_DQ1_10
AB18
GND
AC31
PLA_P1_UPD6
A7
GND
AB19
GND
AC32
PLA_P1_UPD9
A8
DDR2_P2_UDQS1_N
AB2
MC_A24
AC33
PLA_P1_UPSIGDET
A9
DDR2_P2_UDQS1_P
AB20
GND
AC34
PLA_P1_DND2
AA1
MC_A18
AB21
GND
AC4
MC_D9
AA12
GND
AB22
GND
AC5
MC_D12
AA13
GND
AB23
GND
AC6
VDDIO
AA14
GND
AB28
VDDCORE
AC7
VDDCORE
Page 52 of 89
Rev 0.23

Ball
Signal Name
Ball
AD1
MC_D4
AF33
Signal Name
Ball
Signal Name
P1_DEBUG0
AH20
VDDCORE
AD2
MC_D6
AF34
PLA_P1_UPD3
AH21
VDDCORE
AD27
VDDCORE
AF4
MC_D24
AH22
VDDCORE
AD28
VDDCORE
AF5
MC_D28
AH23
VDDCORE
AD29
P1_DEBUG7
AF6
ARM_WDOUT_N
AH24
VDD_P1_VQ
AD3
GND
AF7
VDDIO
AH25
VDD_P1_VQ
AD30
P1_DEBUG2
AF8
VDDCORE
AH26
VDD_P1_VQ
AD31
PLA_P1_UPD1
AG1
MC_D16
AH27
VDDIO
AD32
GND
AG10
VDDCORE
AH28
VDDIO
AD33
PLA_P1_UPD7
AG11
VDDCORE
AH29
AB_D2
AD34
PLA_P1_UPRBC0
AG2
MC_D20
AH3
GND
AD4
MC_D13
AG24
VDDCORE
AH30
AB_D6
AD5
MC_D17
AG25
VDDCORE
AH31
AB_D11
AD6
MC_D22
AG26
VDDCORE
AH32
GND
AD7
VDDCORE
AG27
VDDCORE
AH33
P1_DEBUG11
AD8
VDDCORE
AG28
VDDCORE
AH34
P1_DEBUG6
AE1
MC_D8
AG29
AB_D7
AH4
ARM_TM_N
AE2
MC_D10
AG3
MC_D25
AH5
LOC_P1_DND1
AE27
VDDCORE
AG30
AB_D12
AH6
LOC_P1_DND6
AE28
VDDIO
AG31
P1_DEBUG15
AH7
VDDIO
AE29
P1_DEBUG13
AG32
P1_DEBUG10
AH8
VDDIO
AE3
MC_D14
AG33
P1_DEBUG5
AH9
VDD_P1_VQ
AE30
P1_DEBUG8
AG34
P1_DEBUG1
AJ1
MC_D27
AE31
P1_DEBUG3
AG4
MC_D30
AJ10
GND
AE32
PLA_P1_UPD0
AG5
MC_DYN_A10
AJ11
VDD_P1_AV
AE33
PLA_P1_UPD4
AG6
LOC_P1_DND2
AJ12
VDD_P1_VQ
AE34
PLA_P1_UPD5
AG7
VDDCORE
AJ13
VDD_P1_VQ
AE4
MC_D18
AG8
VDDCORE
AJ14
VDD_P1_VQ
AE5
MC_D23
AG9
VDDCORE
AJ15
VDD_P1_VQ
AE6
MC_D29
AH1
MC_D21
AJ16
VDD_P1_VQ
AE7
VDDIO
AH10
VDD_P1_VQ
AJ17
VDD_P1_VQ
AE8
VDDCORE
AH11
VDD_P1_VQ
AJ18
VDD_P1_VQ
AF1
MC_D11
AH12
VDDCORE
AJ19
VDD_P1_VQ
AF2
MC_D15
AH13
VDDCORE
AJ2
MC_D31
AF27
VDDCORE
AH14
VDDCORE
AJ20
VDD_P1_VQ
AF28
VDDIO
AH15
VDDCORE
AJ21
VDD_P1_VQ
AF29
AB_D13
AH16
VDDCORE
AJ22
VDD_P1_VQ
AF3
MC_D19
AH17
VDDCORE
AJ23
VDD_P1_VQ
AF30
P1_DEBUG14
AH18
VDDCORE
AJ24
GND
AF31
P1_DEBUG9
AH19
VDDCORE
AJ25
VDD_P1_AV
AF32
P1_DEBUG4
AH2
MC_D26
AJ26
VDD_P1_AV
Page 53 of 89
Rev 0.23

Ball
Signal Name
Ball
Signal Name
Ball
AL9
Signal Name
AJ27
GND
AK33
AB_D9
GND
AJ28
GND
AK34
AB_D14
AM1
GND
AJ29
AB_INT_N
AK4
LOC_P1_DND4
AM10
DDR2_P1_DQ0_0
AJ3
MC_DYN_CLK
AK5
LOC_P1_DND7
AM11
DDR2_P1_DQ0_3
AJ30
AB_D1
AK6
LOC_P1_UPD0
AM12
DDR2_P1_DQ0_5
AJ31
AB_D5
AK7
LOC_P1_UPD6
AM13
DDR2_P1_DQ0_8
AJ32
AB_D10
AK8
MII_RXDV
AM14
GND
AJ33
AB_D15
AK9
MII_RXD3
AM15
DDR2_P1_DQ0_13
AJ34
P1_DEBUG12
AL1
GND
AM16
DDR2_P1_CKE
AJ4
LOC_P1_DND3
AL10
MII_TXER
AM17
GND
AJ5
LOC_P1_DND5
AL11
DDR2_P1_DQ0_1
AM18
DDR2_P1_CAS_N
AJ6
LOC_P1_DND8
AL12
DDR2_P1_DQ0_4
AM19
DDR2_P1_BA1
AJ7
GND
AL13
DDR2_P1_DQ0_7
AM2
LOC_P1_DND9
AJ8
GND
AL14
DDR2_P1_DQ0_10
AM20
DDR2_P1_A1
AJ9
GND
AL15
DDR2_P1_DQ0_12
AM21
GND
AK1
ARM_RST_N
AL16
DDR2_P1_DQ0_15
AM22
DDR2_P1_A5
AK10
MII_TXD2
AL17
DDR2_P1_IMPREF
AM23
DDR2_P1_A9
AK11
MDIO_DATA
AL18
DDR2_P1_WE_N
AM24
DDR2_P1_A12
AK12
VDD_P1_AV
AL19
DDR2_P1_A0
AM25
DDR2_P1_DQ1_2
AK13
GND
AL2
LOC_P1_DNRBC1
AM26
DDR2_P1_DQ1_4
AK14
DDR2_P1_VREF0
AL20
DDR2_P1_A3
AM27
DDR2_P1_DQ1_8
AK15
GND
AL21
DDR2_P1_A6
AM28
VDD_P1_VD
AK16
VDD_P1_AV
AL22
DDR2_P1_A10
AM29
AB_A0
AK17
GND
AL23
DDR2_P1_DQ1_0
AM3
LOC_P1_UPCLK
AK18
GND
AL24
VDD_P1_VD
AM30
GND
AK19
VDD_P1_AV
AL25
GND
AM31
AB_A7
AK2
LOC_P1_DNRBC0
AL26
GND
AM32
AB_A10
AK20
GND
AL27
DDR2_P1_DQ1_12
AM33
VDDIO
AK21
DDR2_P1_VREF1
AL28
AB_A1
AM34
GND
AK22
GND
AL29
AB_A4
AM4
LOC_P1_UPD2
AK23
VDD_P1_AV
AL3
VDDIO
AM5
GND
AK24
DDR2_P1_DQ1_7
AL30
AB_A8
AM6
LOC_P1_UPD9
AK25
DDR2_P1_DQ1_10
AL31
AB_CS_N
AM7
MII_RXD2
AK26
DDR2_P1_DQ1_13
AL32
AB_OE_N
AM8
MII_TXD1
AK27
AB_A2
AL33
AB_D3
AM9
MII_TXEN
AK28
AB_A5
AL34
AB_D8
AN1
GND
AK29
AB_A9
AL4
LOC_P1_DNCOMDET
AN10
DDR2_P1_DQ0_2
AK3
LOC_P1_DND0
AL5
LOC_P1_UPD1
AN11
VDD_P1_VD
AK30
AB_WE_N
AL6
LOC_P1_UPD5
AN12
DDR2_P1_DQ0_6
AK31
AB_D0
AL7
MII_RXER
AN13
DDR2_P1_DQ0_9
AK32
AB_D4
AL8
MII_TXCLK
AN14
DDR2_P1_DQ0_11
Page 54 of 89
Rev 0.23

Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
AN15
DDR2_P1_DQ0_14
AP21
DDR2_P1_LDQS1_N
B28
GPIO29
AN16
DDR2_P1_ODT
AP22
GND
B29
GPIO25
AN17
DDR2_P1_UDM
AP23
DDR2_P1_CLK1_P
B3
GND
AN18
DDR2_P1_RAS_N
AP24
DDR2_P1_CLK1_N
B30
GPIO20
AN19
DDR2_P1_BA0
AP25
GND
B31
GPIO16
AN2
GND
AP26
DDR2_P1_UDQS1_P
B32
GPIO14
AN20
DDR2_P1_BA2
AP27
DDR2_P1_UDQS1_N
B33
GND
AN21
DDR2_P1_A2
AP28
GND
B34
GND
AN22
DDR2_P1_A4
AP29
DDR2_P1_DQ1_5
B4
ARM_TCK
AN23
DDR2_P1_A7
AP3
GND
B5
ARM_INT_N
AN24
DDR2_P1_A8
AP30
DDR2_P1_DQ1_9
B6
DDR2_P2_DQ1_14
AN25
DDR2_P1_A11
AP31
DDR2_P1_DQ1_14
B7
VDD_P2_VD
AN26
DDR2_P1_DQ1_1
AP32
GND
B8
DDR2_P2_DQ1_7
AN27
DDR2_P1_DQ1_3
AP33
GND
B9
DDR2_P2_DQ1_4
AN28
DDR2_P1_DQ1_6
AP34
GND
C1
GND
AN29
DDR2_P1_DQ1_11
AP4
LOC_P1_UPD7
C10
DDR2_P2_DQ1_5
AN3
LOC_P1_UPD3
AP5
MII_RXD0
C11
DDR2_P2_DQ1_2
AN30
DDR2_P1_DQ1_15
AP6
MII_RXCLK
C12
DDR2_P2_A12
AN31
AB_A3
AP7
GND
C13
DDR2_P2_A9
AN32
AB_A6
AP8
DDR2_P1_LDQS0_P
C14
GND
AN33
GND
AP9
DDR2_P1_LDQS0_N
C15
DDR2_P2_A4
AN34
GND
B1
GND
C16
DDR2_P2_A1
AN4
LOC_P1_UPD4
B10
DDR2_P2_DQ1_1
C17
DDR2_P2_BA1
AN5
LOC_P1_UPD8
B11
DDR2_P2_A11
C18
GND
AN6
MII_RXD1
B12
DDR2_P2_A10
C19
DDR2_P2_UDM
AN7
MII_TXD0
B13
DDR2_P2_A7
C2
GND
AN8
MII_TXD3
B14
DDR2_P2_A5
C20
DDR2_P2_CKE
AN9
MDIO_CLK
B15
DDR2_P2_A3
C21
GND
AP1
GND
B16
DDR2_P2_A0
C22
VDD_P2_VD
AP10
GND
B17
DDR2_P2_BA0
C23
DDR2_P2_DQ0_9
AP11
DDR2_P1_CLK0_P
B18
DDR2_P2_RAS_N
C24
DDR2_P2_DQ0_7
AP12
DDR2_P1_CLK0_N
B19
DDR2_P2_IMPREF
C25
DDR2_P2_DQ0_2
AP13
GND
B2
GND
C26
DDR2_P2_DQ0_0
AP14
DDR2_P1_UDQS0_P
B20
DDR2_P2_ODT
C27
GPIO28
AP15
DDR2_P1_UDQS0_N
B21
DDR2_P2_DQ0_15
C28
GPIO24
AP16
GND
B22
DDR2_P2_DQ0_13
C29
GPIO19
AP17
DDR2_P1_LDM
B23
DDR2_P2_DQ0_11
C3
GND
AP18
DDR2_P1_CS_N
B24
DDR2_P2_DQ0_8
C30
GND
AP19
GND
B25
DDR2_P2_DQ0_5
C31
GPIO12
AP2
GND
B26
DDR2_P2_DQ0_4
C32
GPIO9
AP20
DDR2_P1_LDQS1_P
B27
DDR2_P2_DQ0_1
C33
GPIO7
Page 55 of 89
Rev 0.23

Ball
C34
Signal Name
Ball
Signal Name
Ball
Signal Name
GND
E1
CLK_125_OUT
F16
VDD_P2_VQ
C4
ARM_TRSTN
E10
DDR2_P2_DQ1_13
F17
VDD_P2_VQ
C5
GND
E11
DDR2_P2_DQ1_11
F18
VDD_P2_VQ
C6
EXT_PROC_N
E12
VDD_P2_AV
F19
VDD_P2_VQ
C7
DDR2_P2_DQ1_15
E13
GND
F2
LOC_P2_DND3
C8
DDR2_P2_DQ1_12
E14
DDR2_P2_VREF1
F20
VDD_P2_VQ
C9
DDR2_P2_DQ1_8
E15
GND
F21
VDD_P2_VQ
D1
CLK_125
E16
VDD_P2_AV
F22
VDD_P2_VQ
D10
DDR2_P2_DQ1_9
E17
GND
F23
VDD_P2_VQ
D11
DDR2_P2_DQ1_6
E18
GND
F24
VDD_P2_AV
D12
DDR2_P2_DQ1_3
E19
VDD_P2_AV
F25
GND
D13
DDR2_P2_DQ1_0
E2
TDI
F26
GND
D14
DDR2_P2_A8
E20
GND
F27
GND
D15
DDR2_P2_A6
E21
DDR2_P2_VREF0
F28
GND
D16
DDR2_P2_A2
E22
GND
F29
GND
D17
DDR2_P2_BA2
E23
VDD_P2_AV
F3
TDO
D18
DDR2_P2_CS_N
E24
GPIO31
F30
VDDIO
D19
DDR2_P2_LDM
E25
GPI27
F31
GND
D2
TCK
E26
GPIO22
F32
PLA_P2_DNRECSTRB0
D20
DDR2_P2_DQ0_14
E27
GPIO17
F33
PLA_P2_DND18
D21
DDR2_P2_DQ0_12
E28
GPIO13
F34
PLA_P2_DND16
D22
DDR2_P2_DQ0_10
E29
GPIO10
F4
TRSTN
D23
DDR2_P2_DQ0_6
E3
TMS
F5
GND
D24
DDR2_P2_DQ0_3
E30
GPIO6
F6
GND
D25
VDD_P2_VD
E31
GPIO4
F7
GND
D26
GND
E32
GPIO_2
F8
GND
D27
GPIO23
E33
GPIO1
F9
VDD_P2_AV
D28
GPIO18
E34
GPIO0
G1
LOC_P2_DNRBC0
D29
GPIO15
E4
TM_N
G10
VDD_P2_VQ
D3
SM_N
E5
MC_STC_CLK
G11
VDD_P2_VQ
D30
GPIO11
E6
ARM_TDO
G12
VDDCORE
D31
GPIO8
E7
ARM_TDI
G13
VDDCORE
D32
GPIO5
E8
UART_DOUT
G14
VDDCORE
D33
GPIO3
E9
RST_N
G15
VDDCORE
D34
PLA_P2_DNCLK
F1
LOC_P2_DND5
G16
VDDCORE
D4
VDDIO
F10
GND
G17
VDDCORE
D5
CLK_25_OUT
F11
VDD_P2_AV
G18
VDDCORE
D6
ARM_TMS
F12
VDD_P2_VQ
G19
VDDCORE
D7
UART_DIN
F13
VDD_P2_VQ
G2
LOC_P2_DND7
D8
PLL_BYPASS_N
F14
VDD_P2_VQ
G20
VDDCORE
D9
GND
F15
VDD_P2_VQ
G21
VDDCORE
Page 56 of 89
Rev 0.23

Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
G22
VDDCORE
H9
VDDCORE
L32
GND
G23
VDDCORE
J1
MC_DYN_SYNCOUT
L33
PLA_P2_UPD9
G24
VDD_P2_VQ
J2
LOC_P2_UPD7
L34
PLA_P2_UPD7
G25
VDD_P2_VQ
J27
VDDCORE
L4
MC_DYN_SYNCIN
G26
VDD_P2_VQ
J28
VDDIO
L5
LOC_P2_UPD8
G27
VDDIO
J29
PLA_P2_DND19
L6
LOC_P2_UPD5
G28
VDDIO
J3
LOC_P2_UPD3
L7
VDDCORE
G29
PLA_P2_UNASSIGNSTRB
J30
PLA_P2_DND15
L8
VDDCORE
G3
GND
J31
PLA_P2_DND11
M1
MC_DYN_CAS_N
G30
PLA_P2_RANGESTRB
J32
PLA_P2_DND8
M12
GND
G31
PLA_P2_DNRECTHR
J33
PLA_P2_DND4
M13
GND
G32
GND
J34
PLA_P2_DND1
M14
GND
G33
PLA_P2_DND14
J4
LOC_P2_UPD0
M15
GND
G34
GND
J5
LOC_P2_DND8
M16
GND
G4
LOC_P2_DND1
J6
LOC_P2_DND4
M17
GND
G5
LOC_P2_DNRBC1
J7
VDDIO
M18
GND
G6
LOC_P2_UPCLK
J8
VDDCORE
M19
GND
G7
VDDIO
K1
MC_STC_BSEL1_N
M2
MC_DYN_CLKEN
G8
VDDIO
K2
MC_STC_BSEL0_N
M20
GND
G9
VDD_P2_VQ
K27
VDDCORE
M21
GND
H1
LOC_P2_UPD4
K28
VDDIO
M22
GND
H10
VDDCORE
K29
PLA_P2_DND13
M23
GND
H11
VDDCORE
K3
LOC_P2_UPD9
M28
VDDCORE
H2
LOC_P2_UPD1
K30
PLA_P2_DND9
M29
VDDIO
H24
VDDCORE
K31
PLA_P2_DND5
M3
MC_DYN_DQM2
H25
VDDCORE
K32
PLA_P2_DND2
M30
PLA_P2_UPRBC1
H26
VDDCORE
K33
PLA_P2_UPSIGDET
M31
PLA_P2_UPD8
H27
VDDCORE
K34
PLA_P2_UPRBC0
M32
PLA_P2_UPD6
H28
VDDCORE
K4
LOC_P2_UPD6
M33
PLA_P2_UPD4
H29
PLA_P2_DNRECSTRB1
K5
LOC_P2_UPD2
M34
PLA_P2_UPD2
H3
LOC_P2_DND9
K6
LOC_P2_DNCOMDET
M4
MC_DYN_DQM0
H30
PLA_P2_DNRECCLK
K7
VDDIO
M5
MC_STC_BSEL2_N
H31
PLA_P2_DND17
K8
VDDCORE
M6
VDDIO
H32
PLA_P2_DND12
L1
MC_DYN_DQM1
M7
VDDCORE
H33
PLA_P2_DND10
L2
MC_STC_BSEL3_N
N1
MC_STC_CS2_N
H34
PLA_P2_DND6
L27
VDDCORE
N12
GND
H4
LOC_P2_DND6
L28
VDDCORE
N13
GND
H5
LOC_P2_DND2
L29
PLA_P2_DND7
N14
GND
H6
LOC_P2_DND0
L3
GND
N15
GND
H7
VDDCORE
L30
PLA_P2_DND3
N16
GND
H8
VDDCORE
L31
PLA_P2_DND0
N17
GND
Page 57 of 89
Rev 0.23

Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
N18
GND
P4
MC_DYN_CS0_N
T21
GND
N19
GND
P5
MC_STC_CS3_N
T22
GND
N2
MC_STC_CS1_N
P6
VDDCORE
T23
GND
N20
GND
P7
VDDCORE
T28
VDDCORE
N21
GND
R1
MC_DYN_BA0
T29
VDDIO
N22
GND
R12
GND
T3
MC_STC_SYNCIN
N23
GND
R13
GND
T30
P2_DEBUG10
N28
VDDCORE
R14
GND
T31
P2_DEBUG11
N29
VDDIO
R15
GND
T32
P2_DEBUG12
N3
MC_STC_CS0_N
R16
GND
T33
P2_DEBUG13
N30
PLA_P2_UPD5
R17
GND
T34
P2_DEBUG14
N31
PLA_P2_UPD3
R18
GND
T4
GND
N32
PLA_P2_UPD1
R19
GND
T5
MC_STC_SYNCOUT
N33
PLA_P2_UPD0
R2
MC_STC_OE_N
T6
VDDIO
N34
P2_DEBUG1
R20
GND
T7
VDDCORE
N4
MC_DYN_RAS_N
R21
GND
U1
MC_A1
N5
MC_DYN_DQM3
R22
GND
U12
GND
N6
VDDIO
R23
GND
U13
GND
N7
VDDCORE
R28
VDDCORE
U14
GND
P1
MC_DYN_CS3_N
R29
VDDIO
U15
GND
P12
GND
R3
GND
U16
GND
P13
GND
R30
P2_DEBUG6
U17
GND
P14
GND
R31
P2_DEBUG7
U18
GND
P15
GND
R32
GND
U19
GND
P16
GND
R33
P2_DEBUG8
U2
MC_A2
P17
GND
R34
P2_DEBUG9
U20
GND
P18
GND
R4
MC_DYN_WE_N
U21
GND
P19
GND
R5
MC_STC_WE_N
U22
GND
P2
MC_DYN_CS2_N
R6
VDDIO
U23
GND
P20
GND
R7
VDDCORE
U28
VDDCORE
P21
GND
T1
MC_DYN_BA1
U29
VDDCORE
P22
GND
T12
GND
U3
MC_A3
P23
GND
T13
GND
U30
PLA_P1_DNRECSTRB0
P28
VDDCORE
T14
GND
U31
PLA_P1_DNRECSTRB1
P29
VDDCORE
T15
GND
U32
PLA_P1_RANGESTRB
P3
MC_DYN_CS1_N
T16
GND
U33
PLA_P1_UNASSIGNSTRB
P30
P2_DEBUG0
T17
GND
U34
P2_DEBUG15
P31
P2_DEBUG2
T18
GND
U4
MC_A4
P32
P2_DEBUG3
T19
GND
U5
MC_A5
P33
P2_DEBUG4
T2
MC_A0
U6
VDDCORE
P34
P2_DEBUG5
T20
GND
U7
VDDCORE
Page 58 of 89
Rev 0.23

Ball
Signal Name
Ball
W29
Signal Name
V1
MC_A6
VDDIO
V12
GND
W3
MC_A13
V13
GND
W30
PLA_P1_DND12
V14
GND
W31
PLA_P1_DND14
V15
GND
W32
PLA_P1_DND15
V16
GND
W33
PLA_P1_DND16
V17
GND
W34
PLA_P1_DND17
V18
GND
W4
MC_A14
V19
GND
W5
MC_A17
V2
MC_A7
W6
VDDIO
V20
GND
W7
VDDCORE
V21
GND
Y1
MC_A15
V22
GND
Y12
GND
V23
GND
Y13
GND
V28
VDDCORE
Y14
GND
V29
VDDCORE
Y15
GND
V3
MC_A8
Y16
GND
V30
PLA_P1_DND18
Y17
GND
V31
PLA_P1_DND19
Y18
GND
V32
PLA_P1_DNCLK
Y19
GND
V33
PLA_P1_DNRECCLK
Y2
MC_A16
V34
PLA_P1_DNRECTHR
Y20
GND
V4
MC_A9
Y21
GND
V5
MC_STC_A10
Y22
GND
V6
VDDCORE
Y23
GND
V7
VDDCORE
Y28
VDDCORE
W1
MC_A11
Y29
VDDIO
W12
GND
Y3
GND
W13
GND
Y30
PLA_P1_DND7
W14
GND
Y31
PLA_P1_DND9
W15
GND
Y32
GND
W16
GND
Y33
PLA_P1_DND11
W17
GND
Y34
PLA_P1_DND13
W18
GND
Y4
MC_A19
W19
GND
Y5
MC_A22
W2
MC_A12
Y6
VDDIO
W20
GND
Y7
VDDCORE
W21
GND
W22
GND
W23
GND
W28
VDDCORE
Page 59 of 89
Rev 0.23

TK3723 Electrical Specifications
3.1
Absolute Maximum Ratings
If absolute maximum ratings are exceeded, the device may fail permanently. Device operation at or above these
limits is not guaranteed and recommended. Exposure to absolute maximum ratings for extended periods of time
may diminish device functionality.
Absolute Maximum Ratings
Table 19.
Parameter
Symbol
Conditions
Min
Max
Unit
VDDCORE
-0.30
1.32
VDDIO
-0.30
3.60
VDD_P1_VQ,
VDD_P2_VQ
-0.30
1.98
VDD_P1_VD,
VDD_P2_VD
-0.30
3.60
VDD_P1_AV,
VDD_P2_AV
-0.30
3.60
-0.30
1.00
AVDD
-0.30
3.60
Storage Temperature
Tstg
-60
150
Junction Temperature
TJ (max)
125
Voltage applied to any input pin
VPIN
Undershoot / overshoot < 20% of the

cycle on GND/VDD
-0.3
VDD + 0.3
Power Dissipation
PMAX
Zero Air Flow
7.0
I/O Latch-Up Current
ILATCHUP
-100
100
mA
ESD Voltage at any pin
VESD(HBM)
Human Body Model
-2.0
2.0
KV
Power Supply Voltages
DDR2_P1_VREF0,
DDR2_P1_VREF1,
DDR2_P2_VREF0,
DDR2_P2_VREF1
ELECTROSTATIC DISCHARGE
This device can be damaged by ESD. Teknovus recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures may adversely affect reliability of the
device.
Page 60 of 89
Rev 0.23

3.2
Recommended Operating Conditions

Recommended Operating Supply Voltages
Table 20.
Parameter
Symbol
Min
Typ
Max
Unit
Core Supply Voltage
VDDCORE
1.14
1.20
1.26
CMOS I/O Supply Voltage
VDDIO
3.14
3.30
3.46
DDRII I/O 1.8V Supply Voltage
VDD_P1_VQ, VDD_P2_VQ
1.70
1.80
1.90
DDRII I/O 3.3V Supply Voltage
VDD_P1_VD, VDD_P2_VD
3.14
3.30
3.46
Internal Memories Supply Voltage VDD_P1_AV, VDD_P2_AV
3.14
3.30
3.46
50
mV
0.85
0.90
0.95
3.14
3.30
3.46
50
mV
Digital Supplies Noise

(peak-to-peak; 50KHz-125MHz)
DDRII Input Reference Voltage*
PLL Analog Supply Voltage
Analog Supply Noise
(peak-to-peak; 50KHz-125MHz)
VDD
DDR2_P1_VREF0, DDR2_P1_VREF1,
DDR2_P2_VREF0, DDR2_P2_VREF1
AVDD
AVDD
* DDR2_P[2..1]_VREF[1..0] values are expected to be about 50% of corresponding VDD_P[2..1]_VQ voltages of the transmitting devices, and
are expected to track corresponding VDD_P[2..1]_VQ variations. Peak-to-peak AC noise (50KHz-125MHz) may not exceed +2% of
corresponding DDR2_P[2..1]_VREF[1..0] voltage.
Recommended Operating Temperatures
Table 21.
Parameter
Symbol
Min
Typ
Max
Unit
Junction Temperature*
TJ
-40
125
Maximum Case Temperature*
TC
112
Typ*
Max**
Unit
* To select proper cooling method for desired ambient temperature, refer to sections 4.2..4.4.
3.3
Power Supplies Current and Power

Power Consumption
Table 22.
Parameter
Symbol
1.20V Core Supply Current
IVDDCORE
1.50
2.50
Core Power @ 1.20V
PVDDCORE
1.80
3.00
3.3V CMOS I/O Supply Current
IVDDIO
0.30
0.45
CMOS I/O Power @ 3.30V
PVDDIO
1.00
1.50
1.8V DDRII I/O Supply Current
IVDD_P1_VQ + IVDD_P2_VQ
0.50
0.75
DDRII I/O Power @ 1.80V
PVDD_P1_VQ + PVDD_P2_VQ
0.90
1.35
3.3V DDRII I/O Supply Current
IVDD_P1_VD + IVDD_P2_VD
50
100
mA
Page 61 of 89
Rev 0.23

Parameter
Symbol
Typ*
Max**
Unit
DDRII I/O Power @ 3.30V
PVDD_P1_VD + PVDD_P2_VD
165
330
mW
3.3V Internal Memories Supply

Current
IVDD_P1_AV + IVDD_P2_AV
50
100
mA
Internal Memories Power @

3.30V
PVDD_P1_AV + PVDD_P2_AV
165
330
mW
0.08
0.11
mA
0.07
0.10
mW
3.30V PLL Analog Supply Current IAVDD
mA
PLL Analog Power @ 3.30V
PAVDD
10
mW
Total Power
4.00
6.50
0.90V DDRII Input Reference

Current
IDDR2_P1_VREF0 + IDDR2_P1_VREF1 + IDDR2_P2_VREF0 + IDDR2_P2_VREF1
DDRII Input Reference Power @

0.90V
PDDR2_P1_VREF0 + PDDR2_P1_VREF1 + PDDR2_P2_VREF0 + PDDR2_P2_VREF1
* At 25C, typical voltage levels, both channels enabled at 2.5Gbps downstream and 1.25Gbps upstream, full traffic loads at all ports, reduced
drive strength for DDRII DQ and DQS signals, full drive strength for ADDRESS/COMMAND outputs, and ODT=75. These measured values
should be used for the purpose of thermal analysis.
** At 70C, maximum voltage levels, both channels enabled at 2.5Gbps downstream and 1.25Gbps upstream, full traffic loads at all ports,
reduced drive strength for DDRII DQ and DQS signals, full drive strength for ADDRESS/COMMAND outputs, and ODT=75. These
theoretical values should be used for the purpose of calculating power supplies peak currents.
3.4
Power Supplies Sequencing
The recommended power supply sequence is to either bring up all supplies simultaneously, or from the highest to
the lowest in following order:
1.
3.3V VDDIO, VDD_P[2..1]_VD, VDD_P[2..1]_AV, and AVDD
2.
1.8V VDD_P[2..1]_VQ and 0.9V DDRII Input Reference Voltages
3.
1.2V VDDCORE.
RST_N signal must remain LOW throughout the duration of the power up sequence.
Page 62 of 89
Rev 0.23

3.5
DC Characteristics
3.5.1
CMOS I/O DC Characteristic
Table 23.
CMOS I/O DC Characteristics

Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CMOS Input High Voltage
VIH
2.00
3.60
CMOS Input Low Voltage
VIL
-0.30
0.80
VI =3.30V or 0V
10
10
CMOS Input Leakage Current
II
CMOS Tri-State Output Leakage

Current
IOZ
VOZ =3.30V or 0V
CMOS Output High Voltage
VOH
VDDIO=Min
2.40
CMOS Output Low Voltage
VOL
VDDIO=Min
0.40
CMOS Output High Current
IOH
CLOAD=75pF,
VOH=2.40V
10.30
21.60
36.80
mA
CMOS Output Low Current
IOL
CLOAD=75pF,
VOL=0.40V
9.40
15.30
21.40
mA
CMOS Pin Pull-up Resistor
RPU
39
55
85
CMOS Pin Capacitance
CPIN
Excluding package
(package capacitance
typically adds 2.0pF)
3.6
pF
Min
Typ
Max
Unit
3.5.2
SSTL-18 I/O DC Characteristic
Table 24.
SSTL-18 I/O DC Characteristics

Parameter
Symbol
Conditions
SSTL-18 Input DC Characteristics (I/O18 pins)

SSTL-18 Input High Voltage
VIH
Guaranteed HIGH
Level
VREF +
0.125
VDDQ +
0.3
SSTL-18 Input Low Voltage
VIL
Guaranteed LOW
Level
-0.3
VREF - 0.125
SSTL-18 Input High Current
IIH
VDDQ=Max, VI=VDDQ
SSTL-18 Input Low Current
IIL
VDDQ=Max, VI=GND
SSTL-18 Input Hysteresis
VH
VDDCORE=Typ,
25C ambient
7.5
mV
1.42
SSTL-18 Output DC Characteristics (Reduced Drive Strength*, I/O18 and O18 pins)
SSTL-18 Output High Voltage
VOH
VDDCORE=Min,
VDDQ=Min,
IOH=-8.04mA
Page 63 of 89
Rev 0.23

Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SSTL-18 Output Low Voltage
VOL
VDDCORE=Min,
VDDQ=Min,
IOL=8.04mA
0.28
SSTL-18 Output High Current
IOH
VDDCORE=Min,
VDDQ=Min,
VO=1.42V
-8.04
mA
SSTL-18 Output Low Current
IOL
VDDCORE=Min,
VDDQ=Min,
VO=0.28V
8.04
mA
-30
mA
SSTL-18 Short Circuit Current
IOS
VDDQ=Max, VO=GND
SSTL-18 Output DC Characteristics (Full Drive Strength*, I/O18 and O18 pins)
SSTL-18 Output High Voltage
VOH
VDDCORE=Min,
VDDQ=Min,
IOH=-13.40mA
1.42
SSTL-18 Output Low Voltage
VOL
VDDCORE=Min,
VDDQ=Min,
IOL=13.40mA
0.28
SSTL-18 Output High Current
IOH
VDDCORE=Min,
VDDQ=Min,
VO=1.42V
-13.40
mA
SSTL-18 Output Low Current
IOL
VDDCORE=Min,
VDDQ=Min,
VO=0.28V
13.40
mA
SSTL-18 Short Circuit Current
IOS
VDDQ=Max, VO=GND
-60
mA
* Drive Strength is controlled by software.

Notes:
1: VDDQ is: VDD_P1_VQ, or VDD_P2_VQ
2: VREF is: DDR2_P1_VREF0, DDR2_P1_VREF1, DDR2_P2_VREF0, or DDR2_P2_VREF1.
Page 64 of 89
Rev 0.23

3.6
AC Characteristics
3.6.1
System Clock Timing
TK3723 requires single-ended CMOS 125MHz clock source with the following characteristics:
Table 25.
System Clock Source Requirements

Parameter
Symbol
Min
Typ
Max
Unit
CLK_125 Frequency
Cfreq
125.0
MHz
CLK_125 Frequency Deviation
PPM
-100
+100
ppm
CLK_125 Pulse Width (High)
t1
3.6
4.0
4.4
ns
CLK_125 Pulse Width (Low)
t2
3.6
4.0
4.4
ns
t 1 / t2
40
50
60
CLK_125 Period
t3
7.9992
8.0
8.0008
ns
CLK_125 Fall Time (80%/20%)
t4
1.0
ns
CLK_125 Rise Time (20%/80%)
t5
1.0
ns
CLK_125 Total Jitter (peak-to-peak)
TJP-P
40
ps
CLK_125 Total RMS Jitter
TJRMS
10
ps
CLK_125 Duty Cycle
Figure 18. System Clock Source Timing

Note:
Use of PLL-based clock buffers to distribute this clock signal is NOT recommended.
Page 65 of 89
Rev 0.23

3.6.2
Local-Side MII/GMII/TBI Timing
Table 26.
Local-Side MII Input Timing (MAC Mode)

Parameter
Symbol
Min
Max
Unit
LOC_Px_DNRBC0 Pulse Width (High)
t1
18.0
22.0
ns
LOC_Px_DNRBC0 Pulse Width (Low)
t2
18.0
22.0
ns
t 1 / t2
40
60
LOC_Px_DNRBC0 Period
t3
39.998
40.002
ns
LOC_Px_DNEN, LOC_Px_DNER, LOC_Px_DND[3..0] Setup to

LOC_Px_DNRBC0 Rising Edge
t4
10.0
ns
LOC_Px_DNEN, LOC_Px_DNER, LOC_Px_DND[3..0] Hold after

t5
10.0
ns
LOC_Px_DNRBC0 Duty Cycle
Figure 19. Local-Side MII Input Timing (MAC Mode)

Table 27.
Local-Side MII Output Timing (MAC Mode)

Parameter
Symbol
Min
Max
Unit
t1
18.0
22.0
ns
t2
18.0
22.0
ns
t 1 / t2
45
55
t3
39.998
40.002
ns
LOC_Px_UPDV, LOC_Px_UPER, LOC_Px_UPD[3..0] Setup to

t4
15.0
ns
LOC_Px_UPDV, LOC_Px_UPER, LOC_Px_UPD[3..0] Hold after

t5
0.0
ns
LOC_Px_UPDV Falling Edge to LOC_Px_UPDV Rising Edge
t6
120.0
ns
Figure 20. Local-Side MII Output Timing (MAC Mode)

Page 66 of 89
Rev 0.23

Table 28.
Local-Side GMII Input Timing (PHY and MAC Mode)

Parameter
Symbol
Min
Max
Unit
t1
3.6
4.4
ns
t2
3.6
4.4
ns
t 1 / t2
40
60
t3
7.9992
8.0008
ns
LOC_Px_DNEN, LOC_Px_DNER, LOC_Px_DND[7..0] Setup to

t4
2.0
ns
LOC_Px_DNEN, LOC_Px_DNER, LOC_Px_DND[7..0] Hold after

t5
0.0
ns
Figure 21. Local-Side GMII Input Timing (PHY and MAC Mode)
Table 29.
Local-Side GMII Output Timing (PHY and MAC Mode)

Parameter
Symbol
Min
Max
Unit
LOC_Px_UPCLK Pulse Width (High)
t1
3.6
4.4
ns
LOC_Px_UPCLK Pulse Width (Low)
t2
3.6
4.4
ns
t 1 / t2
45
55
LOC_Px_UPCLK Period
t3
7.9992
8.0008
ns
LOC_Px_UPDV, LOC_Px_UPER, LOC_Px_UPD[7..0] Setup to

LOC_Px_UPCLK Rising Edge
t4
2.5
ns
LOC_Px_UPDV, LOC_Px_UPER, LOC_Px_UPD[7..0] Hold after

LOC_Px_UPCLK Rising Edge
t5
0.5
ns
LOC_Px_UPCLK Duty Cycle
Figure 22. Local-Side GMII Output Timing (PHY and MAC Mode)
Page 67 of 89
Rev 0.23

Table 30.
Local-Side TBI Input Timing (MAC Mode)

Parameter
Symbol
Min
Max
Unit
LOC_Px_DNRBC[1..0] Pulse Width (High)
t1
7.5
8.5
ns
LOC_Px_DNRBC[1..0] Pulse Width (Low)
t2
7.5
8.5
ns
t 1 / t2
40
60
LOC_Px_DNRBC[1..0] Period
t3
15.9984
16.0016
ns
LOC_Px_DND[9..0] Setup to LOC_Px_DNRBC[1..0] Rising Edge
t4
2.0
ns
LOC_Px_DND[9..0] Hold after LOC_Px_DNRBC[1..0] Rising Edge
t5
1.0
ns
LOC_Px_DNRBC[1..0] Duty Cycle
Figure 23. Local-Side TBI Input Timing (MAC Mode)
Table 31.
Local-Side TBI Output Timing (MAC Mode)

Parameter
Symbol
Min
Max
Unit
LOC_Px_UPCLK Pulse Width (High)
t1
3.6
4.4
ns
LOC_Px_UPCLK Pulse Width (Low)
t2
3.6
4.4
ns
t 1 / t2
45
55
LOC_Px_UPCLK Period
t3
7.9992
8.0008
ns
LOC_Px_UPD[9..0] Setup to LOC_Px_UPCLK Rising Edge
t4
2.5
ns
LOC_Px_UPD[9..0] Hold after LOC_Px_UPCLK Rising Edge
t5
1.5
ns
LOC_Px_UPCLK Duty Cycle
Figure 24. Local-Side TBI Output Timing (MAC Mode)
Page 68 of 89
Rev 0.23

3.6.3
Plant-Side TBI Timing
Table 32.
Plant-Side TBI Input Timing

Parameter
Symbol
Min
Max
Unit
PLA_Px_UPRBC[1..0] Pulse Width (High) (62.5MHz Mode)
t1
7.5
8.5
ns
PLA_Px_UPRBC[1..0] Pulse Width (Low) (62.5MHz Mode)
t2
7.5
8.5
ns
t 1 / t2
40
60
PLA_Px_UPRBC[1..0] Period (62.5MHz Mode)
t3
15.9984
16.0016
ns
PLA_Px_UPRBC0 Pulse Width (High) (125MHz Mode)
t4
3.6
4.4
ns
PLA_Px_UPRBC0 Pulse Width (Low) (125MHz Mode)
t5
3.6
4.4
ns
t 4 / t5
40
60
PLA_Px_UPRBC0 Period (125MHz Mode)
t6
7.9992
8.0008
ns
PLA_Px_UPD[9..0] Setup to PLA_Px_UPRBC[1..0] Rising Edge
t7
2.0
ns
PLA_Px_UPD[9..0] Hold after PLA_Px_UPRBC[1..0] Rising Edge
t8
1.0
ns
PLA_Px_UPRBC[1..0] Duty Cycle (62.5MHz Mode)
PLA_Px_UPRBC0 Duty Cycle (125MHz Mode)
Figure 25. Plant-Side TBI Input Timing
Page 69 of 89
Rev 0.23

Table 33.
Plant-Side TBI Output Timing

Parameter
Symbol
Min
Max
Unit
PLA_Px_DNCLK Pulse Width (High)
t1
3.6
4.4
ns
PLA_Px_DNCLK Pulse Width (Low)
t2
3.6
4.4
ns
t1 / t2
45
55
PLA_Px_DNCLK Period
t3
7.9992
8.0008
ns
PLA_DND[19..0]* Setup to PLA_Px_DNCLK or CLK_125 Rising Edge
t4
2.5
ns
PLA_DND[19..0]* Hold after PLA_Px_DNCLK or CLK_125 Rising Edge
t5
1.5
ns
PLA_Px_DNCLK Duty Cycle
* All bus widths i.e. 8+1bit, 10bits, 16+2bits, and 20bits.
Figure 26. Plant-Side TBI Output Timing

Note:
PLA_Px_DNCLK signals are not recommended to be used as reference clock sources to an external SerDes. In application where a
SerDes transmit clock is also the SerDes reference clock, use of clean CLK_125 signal is recommended instead (see jitter requirements of
CLK_125 source in Table 25).
Page 70 of 89
Rev 0.23

3.6.4
DDRII DRAM Interfaces Timing
Table 34.
DDRII DRAM Write Timing (BL=8, WL=2, AL=0, WR=2)

Parameter
Symbol
Min
Max
Unit
CLK Period
tCK
7.9992
8.0008
ns
CLK Pulse Width (High)
tCH
0.48
0.52
tCK
CLK Pulse Width (Low)
tCL
0.48
0.52
tCK
tJITPER
-125
125
ps
ADDRESS/COMMAND Output Setup Time
tACS
800
ps
ADDRESS/COMMAND Output Hold Time
tACH
800
ps
ACTIVE-to-READ or WRITE Delay
tRCD
16.0
ns
ACTIVE-to-PRECHARGE Command
tRAS
40.0
70,000
ns
WRITE Pre-amble
tWPRE
0.25
tCK
WRITE Post-amble
tWPST
0.4
0.6
tCK
DQS Pulse Width (High)
tDQSH
0.35
tCK
DQS Pulse Width (Low)
tDQSL
0.35
tCK
Positive DQS Latching Edge to associated CLK Edge
tDQSS
-0.25*
0.25
tCK
DQ-DQS Output Setup Time
tDS
400
ps
DQ-DQS Output Hold Time
tDH
400
ps
DQS Falling Edge to CLK Rising Edge Setup Time
tDSS
0.2
tCK
DQS Falling Edge from CLK Rising Edge Hold Time
tDSH
0.2
tCK
CLK Periodic Jitter
* to guarantee this minimum tDQSS value it is required that DQS signals PCB traces are longer than their corresponding CLK signal PCB traces
by 40mm (see Section 1.6.1 for DDRII DRAM PCB layout guidelines).
Figure 27. DDRII DRAM Write with Auto-precharge Timing

Page 71 of 89
Rev 0.23

Table 35.
DDRII DRAM Read Timing (BL=8, RL=3, AL=0, CL=3)

Parameter
Symbol
Min
Max
Unit
CLK Period
tCK
7.9992
8.0008
ns
tCH
0.48
0.52
tCK
tCL
0.48
0.52
tCK
tJITPER
-125
125
ps
tACS
800
ps
tACH
800
ps
tRCD
16.0
ns
Internal READ-to-PRECHARGE Delay
tRTP
16.0
ns
tRAS
40.0
70,000
ns
PRECHARGE Command Period
tRP
16.0
ns
ACTIVE-to-ACTIVE (same bank command)
tRC
60.0
ns
tDQSCK
-500
500
ps
tPD
500
ps
READ Pre-amble
tRPRE
0.9
1.1
tCK
READ Post-amble
tRPST
0.4
0.6
tCK
DQ-DQS Input Setup Time
tDQSQ
-350
ps
DQ-DQS Input Hold Time
tQH
tCK/4 + 300
ps
CLK Periodic Jitter
DQS Output Access Time from CLK

DQ Propagation Delay
Notes:
1: ADDRESS is: DDR2_Px_A[12..0], DDR2_Px_BA[2..0] (for each corresponding port x)
2: COMMAND is: DDR2_Px_CS_N, DDR2_Px_RAS_N, DDR2_Px_CAS_N, DDR2_Px_WE_N (for each corresponding port x).
Figure 28. DDRII DRAM Read with Auto-precharge Timing

Page 72 of 89
Rev 0.23

3.6.5
ARM9 Interface Timing
Table 36.
FLASH Write Timing

Parameter
Symbol
Min
Max
Unit
MC_STC_CS0_N Pulse Width (Low)
t1
96.0
ns
MC_STC_WE_N Assertion Delay after MC_STC_CS0_N Falling Edge
t2
8.0
ns
MC_STC_WE_N Pulse Width (Low)
t3
64.0
ns
MC_STC_CS0_N Hold after MC_STC_WE_N Rising Edge
t4
24.0
ns
(MC_A[26:11,9:0],MC_STC_A10 and MC_D[15:0]) Setup to

MC_STC_WE_N Rising Edge
t5
70.0
ns
(MC_A[26:11,9:0],MC_STC_A10 and MC_D[15:0]) Hold after

MC_STC_WE_N Rising Edge
t6
22.0
ns
Figure 29. FLASH Write Timing
Page 73 of 89
Rev 0.23

Table 37.
FLASH Read Timing

Parameter
Symbol
Min
Max
Unit
MC_STC_CS0_N Pulse Width (High)
t1
120.0
ns
MC_STC_OE_N Assertion Delay after MC_STC_CS0_N Falling Edge
t2
24.0
ns
MC_STC_OE_N Pulse Width (Low)
t3
72.0
ns
(MC_A[26:11,9:0],MC_STC_A10) Setup to (MC_STC_CS0_N or

MC_STC_OE_N) Rising Edge
t4
94.0
ns
(MC_A[26:11,9:0],MC_STC_A10) Hold after (MC_STC_CS0_N or

MC_STC_OE_N) Rising Edge
t5
0.0
ns
MC_D[15:0] Setup to (MC_STC_CS0_N or MC_STC_OE_N) Rising Edge
t6
10.0
ns
MC_D[15:0] Hold after (MC_STC_CS0_N or MC_STC_OE_N) Rising

Edge
t7
0.0
ns
Figure 30. FLASH 16-bit Read Timing
Figure 31. FLASH 32-bit Read Timing
Page 74 of 89
Rev 0.23

Table 38.
SDRAM Write Timing (CL=3, BL=8)

Parameter
Symbol
Min
Max
Unit
CLK Period
tCK
7.9992
8.0008
ns
tCH
0.45
0.55
tCK
tCL
0.45
0.55
tCK
tACS
2.0
ns
tACH
1.0
ns
tRCD
24.0
ns
tRAS
56.0
ns
tRC
72.0
ns
CLK-to-DATA Valid
tCDV
6.2
ns
DATA Hold Time
tCDI
1.0
ns
Write Recovery Time
tWR
16.0
ns
Precharge Time
tRP
24.0
ns
Notes:
1. ADDRESS is: MC_A[26..11,9..0], MC_DYN_A10, MC_DYN_BA[1..0]
2. COMMAND is: MC_DYN_CS0_N, MC_DYN_RAS_N, MC_DYN_CAS_N, MC_DYN_WE_N
3. MC_DYN_CLKEN is always enabled.
Figure 32. SDRAM Write with Auto-precharge Timing
Page 75 of 89
Rev 0.23

Table 39.
SDRAM Read Timing (CL=3, BL=8)

Parameter
Symbol
Min
Max
Unit
CLK Period
tCK
7.9992
8.0008
ns
tCH
0.45
0.55
tCK
tCL
0.45
0.55
tCK
tACS
2.0
ns
tACH
1.0
ns
tRCD
24.0
ns
tRAS
56.0
ns
tRC
72.0
ns
DATA Input Setup Time
tDS
2.5*
ns
DATA Input Hold Time
tDH
1.0
ns
Precharge Time
tRP
24.0
ns
* to guarantee this minimum tDS value it is required that MC_DYN_SYNCOUT output to the MC_DYN_SYNCIN input total trace length be equal
or longer by no more than 25mm from MC_DYN_CLK signal (see Section 1.8.2 for SDRAM PCB layout guidelines).
Notes:
1. ADDRESS is: MC_A[26..11,9..0], MC_DYN_A10, MC_DYN_BA[1..0]
2. COMMAND is: MC_DYN_CS0_N, MC_DYN_RAS_N, MC_DYN_CAS_N, MC_DYN_WE_N
3. MC_DYN_CLKEN is always enabled.
Figure 33. SDRAM Read with Auto-precharge Timing
Page 76 of 89
Rev 0.23

3.6.6
CRAFT Port MII Timing
Table 40.
CRAFT Port MII Input Timing (MAC Mode)

Parameter
Symbol
Min
Max
Unit
MII_RXCLK Pulse Width (High)
t1
18.0
22.0
ns
MII_RXCLK Pulse Width (Low)
t2
18.0
22.0
ns
t1 / t2
40
60
MII_RXCLK Period
t3
39.996
40.004
ns
MII_RXDV, MII_RXER, MII_RXD[3..0] Setup to MII_RXCLK Rising Edge
t4
10.0
ns
MII_RXDV, MII_RXER, MII_RXDV, MII_RXD[3..0] Hold after MII_RXCLK

Rising Edge
t5
10.0
ns
MII_RXCLK Duty Cycle
Figure 34. CRAFT Port MII Input Timing (MAC Mode)
Table 41.
CRAFT Port MII Output Timing (MAC Mode)

Parameter
Symbol
Min
Max
Unit
MII_TXCLK Pulse Width (High)
t1
18.0
22.0
ns
MII_TXCLK Pulse Width (Low)
t2
18.0
22.0
ns
t 1 / t2
40
60
MII_TXCLK Period
t3
39.996
40.004
ns
MII_TXEN, MII_TXER, MII_TXD[3:0] Setup to MII_TXCLK Rising Edge
t4
15.0
ns
MII_TXEN, MII_TXER, MII_TXD[3:0] Hold after MII_TXCLK Rising Edge
t5
ns
MII_TXCLK Duty Cycle
Figure 35. CRAFT Port MII Output Timing (MAC Mode)
Page 77 of 89
Rev 0.23

3.6.7
Ethernet Serial Management Timing
Table 42.
MDIO Serial Management Timing

Parameter
Symbol
Min
Max
Unit
MDIO_CLK Pulse Width (High)
t1
254.0
258.0
ns
MDIO_CLK Pulse Width (Low)
t2
254.0
258.0
ns
MDIO_CLK Period
t3
510.0
514.0
ns
MDIO_DATA (output) Setup to MDIO_CLK Rising Edge
t4
40.0
ns
MDIO_DATA (output) Hold Time from MDIO_CLK Rising Edge
t5
40.0
ns
MDIO_DATA (input) Setup to MDIO_CLK Falling Edge
t6
20.0
ns
MDIO_DATA (input) Hold Time from MDIO_CLK Falling Edge
t7
0.0
ns
Figure 36. MDIO Serial Management Timing
Page 78 of 89
Rev 0.23

3.6.8
Asynchronous Bus Timing
Table 43.
Asynchronous Bus Read Timing

Parameter
Symbol
Min
Max
Unit
AB_CS_N Pulse Width (High)
t1
48.0
ns
AB_OE_N Falling Edge Setup to AB_CS_N Falling Edge
t2
4.0
ns
AB_CS_N Falling Edge Setup to AB_A[10:0] Valid
t3
16.0
ns
AB_CS_N Falling Edge Setup to AB_D[15:0] Active
t4
16.0
32.0
ns
AB_D[15:0] First Data Word Valid Latency
t5
240.0
ns
AB_D[15:0] Second Data Word Valid Latency
t6
16.0
32.0
ns
AB_D[15:0] Data Hold Time
t7
16.0
32.0
ns
(AB_OE_N, AB_WE_N and AB_A[10:0]) Hold after AB_CS_N Rising Edge
t8
0.0
ns
Figure 37. Asynchronous Bus 32-bit Data Read Timing
Figure 38. Asynchronous Bus 16-bit Data Read Timing

Table 44.
Asynchronous Bus Write Timing
Page 79 of 89
Rev 0.23

Parameter
Symbol
Min
Max
Unit
AB_CS_N Pulse Width (High)
t1
48.0
ns
AB_WE_N Falling Edge Setup to AB_CS_N Falling Edge
t2
4.0
ns
AB_CS_N Falling Edge Setup to (AB_A[10:0] and AB_D[15:0]) Valid
t3
16.0
ns
AB_D[15:0] Data Word Valid
t4
304.0
ns
(AB_WE_N, AB_A[10:0] and AB_D[15:0]) Hold after (AB_WE_N Rising

Edge or AB_CS_N Rising Edge)
t5
0.0
ns
AB_WE_N Pulse Width (High)
t6
32.0
ns
AB_OE_N Hold Time
t7
32.0
ns
Figure 39. Asynchronous Bus 32-bit Data Write Timing
Figure 40. Asynchronous Bus 16-bit Data Write Timing
Page 80 of 89
Rev 0.23

3.6.9
GPIO Timing
Table 45.
GPIO Timing
Parameter
Symbol
Min
Max
Unit
GPIO[n] pin(s) (input) Pulse Width (High)
t1
40.0
ns
GPIO[n] pin(s) (input) Pulse Width (Low)
t2
40.0
ns
GPIO[n] pin(s) (output) Pulse Width (High)
t3
16.0
ns
GPIO[n] pin(s) (output) Pulse Width (Low)
t4
16.0
ns
Note:
GPI27 is restricted to input-only.
Figure 41. GPIO Timing
Page 81 of 89
Rev 0.23

3.6.10
Reset Timing
Table 46.
Reset Timing
Parameter
Symbol
Min
Max
Unit
ARM_WDOUT_N Pulse Width (Low)
t1
1.0
us
Power On to RST_N High
t2
10.0
ms
RST_N Pulse Width (Low)
t3
1.0
mus
Power On to Valid CLK_25_OUT and CLK_125_OUT
t4
5.0
ms
CLK_25_OUT, CLK_125_OUT Invalid and GPIO[n] High-Z After RST_N

Assertion
t5
200
ns
Software Boot Time
t6
Note:
To enable self-reset functionality due to the ARM9 internal watchdog timer timeout, pull-up ARM_WDOUT_N signal with 1K-4.7Kohms resistor
and connect it to either:
a) RST_N input directly (t1 = t3), or
b) input to the board RESET chip which will extend RST_N signal beyond t1 duration (t3 > t1) (shown below).
VDD
CLK_125
Valid
t1
ARM_WDOUT_N
Hi-Z
t2
t3
RST_N
t4
CLK_25_OUT
CLK_125_OUT
Valid
Valid
t6
GPIO[n]
Hi-Z
t5
Valid
t6
Hi-Z
Valid
Figure 42. Reset Timing
Page 82 of 89
Rev 0.23

TK3723 Mechanical Specifications
4.1
Package Diagram
Figure 43. 927-HSBGA Package Diagram
Page 83 of 89
Rev 0.23

Table 47.
927-HSBGA Package Dimensions

Reference
Symbol
Common Dimension
Unit
Package Type
HSBGA
Ball Count
927
35.000
mm
35.000
mm
eD
1.000
mm
eE
1.000
mm
Total Thickness
2.280 +/- 0.130
mm
Mold Thickness
A3
1.170 Ref.
mm
Substrate Thickness
A2
0.610 Ref.
mm
0.600
mm
Stand Off
A1
0.400 ~ 0.600
mm
Ball Width
0.500 ~ 0.700
mm
30.000
mm
30.000
mm
Heat Slug Exposed Size
22.500 ~ 23.500
mm
Heat Slug Flatness
0.100
mm
Heat Slug Shift With Substrate Edge
0.300
mm
Heat Slug Shift With Mold Area
0.500
mm
Chamfer
CA
4.000 Ref.
mm
Package Edge Tolerance
aaa
0.200
mm
Substrate Flatness
bbb
0.250
mm
Mold Flatness
ccc
0.350
mm
Co-planarity
ddd
0.200
mm
Ball Offset (Package)
eee
0.250
mm
fff
0.100
mm
D1
33.000
mm
E1
33.000
mm
Body Size
Ball Pitch
Ball Diameter
Mold Area
Ball Offset (Ball)

Edge Ball Center To Center
Page 84 of 89
Rev 0.23

4.2
Package Thermal Specifications

927-HSBGA Thermal Specifications for JEDEC 4-layer PCB
Table 48.
Parameter
Air Flow (m/s)
Symbol
0.5
1.0
2.0
10.2
9.0
8.3
7.6
Unit
Junction-to-Ambient Thermal Resistance
JA
Junction-to-Case Thermal Resistance
JC
2.0
C/W
Junction-to-Board Thermal Resistance (2S2P JEDEC PCB)*
JB
3.8
C/W
C/W
* JEDEC High-K 4-layer PCB (2S2P), 4.0 x 4.5 x 0.62 dimensions.

Derating Curves for 927-HSBGA (4L PCB without Heatsink)
20.0
18.0
Maximum Power Dissipation [W]
16.0
14.0
12.0
Air Flow=0 [m/s]

Air Flow=0.5 [m/s]
10.0
Air Flow=1.0 [m/s]

Air Flow=2.0 [m/s]
8.0
6.0
4.0
2.0
0.0
0
10
20
30
40
50
60
70
80
90
100
Ambient Temperature [C]
Figure 44. Derating Curves for 927-HSBGA Package on 4-layer JEDEC PCB for TJ=125C (without
Heatsink)
4.3
Package Thermal Requirements
The temperature at which this device operates will determine its performance and reliability. Careful consideration
of factors effecting this devices operating temperature is required.
To satisfy the maximum junction temperature requirement (TJ (max)) with a given ambient air temperature (TA), the
thermal resistance of a package (JA) needs to be less or equal to:
JA = (TJ (max) TA) / P
Page 85 of 89
[1]
Rev 0.23

Using TK3723 maximum power consumption (P) from Table 22, while allowing commercial ambient air
temperature of 70C and limiting maximum junction temperature to below 125C, the thermal resistance junctionto-ambient of the 927-HSBGA package needs to be less or equal to:
JA = (125C 70C) / 6.5W = 8.5C/W
[2]
Since for the 927-HSBGA package thermal resistance at 0m/s air flow as specified in Table 48 is higher than
calculated in [2], TK3723 device requires the use of a heatsink AND presence of an air flow.
Next section describes method of selecting a proper heatsink.
4.4
Heatsink Selection
With the use of a heatsink the formula [1] expands to following format:
JA = JC + CS + SA = (TJ (max) TA) / P
[3]
Where:
CS is thermal resistance of the thermal compound between the case (heat slug) and the heatsink (can be
obtained from the thermal compound manufacturer data sheet), and
SA is thermal resistance from the heatsink-to-ambient air (can be obtained from the heatsink manufacturer data
sheet).
Solving [3] for SA with following assumptions:
TJ (max) = 125C
TA = 70C
JC = 2.0C/W
CS = 0.6C/W (from thermal compound data sheet)
P = 6.25W
produces worst case thermal resistance of the heatsink-to-ambient air of:

SA = JA - JC - CS = ((TJ(max) TA) / PTOTAL) - JC - CS =
[4]
8.5C/W 2.0C/W 0.6C/W = 5.9C/W

Thermal resistance of the chosen heatsink must be equal or lower of the calculated SA value in [4] for the junction
temperature of the device to be maintained at or below specified TJ (max) = 125C while TA = 70C.
INL35001-10/1.7BU is an example of a suitable heatsink (http://www.radianheatsinks.com/Store/INL.pdf). It has
following thermal characteristics:
Table 49.
INL35001-10/1.7BU Heatsink Thermal Characteristics

Parameter
Symbol
Heatsink-to-Ambient Thermal Resistance (INL3500110/1.7BU Heatsink)
SA
Air Flow (m/s)

1.0
2.0
3.0
2.6
1.8
1.4
Page 86 of 89
Unit
C/W
Rev 0.23

Derating Curves for 927-HSBGA (4L PCB with INL35001-10/1.7BU Heatsink)

20.0
18.0
Maximum Power Dissipation [W]
16.0
14.0
12.0
Air Flow=1.0 [m/s]
10.0
Air Flow=2.0 [m/s]

Air Flow=3.0 [m/s]
8.0
6.0
4.0
2.0
0.0
0
10
20
30
40
50
60
70
80
90
100
Ambient Temperature [C]
Figure 45. Derating Curves for 927-HSBGA Package on 4-layer JEDEC PCB for TJ=125C (with
Heatsink)
Page 87 of 89
Rev 0.23

TK3723 Ordering Information
Figure 46. TK3723 Ordering Information
Page 88 of 89
Rev 0.23

NOTICE
A Data Sheet is a technical document that describes the functionality of a device or component, including the
electrical characteristics, packaging, and signal connections. In the semiconductor industry, Data Sheet
information develops as the product progresses through its life-cycle. Therefore, in accordance with industry
standards, Teknovus categorizes its Data Sheets as follows:
Product Preview A Product Preview documents the current state of a new product or concept.
Functional definitions may be included, but all information is subject to change, including the
companys commitment to develop and manufacture the product. Changes are not subject to Product
Change Notification.
Advance Information Advance Information refers to the Data Sheet for a product that is in design or
early prototyping. The Data Sheet includes the pin-out or ball-out and package definition, but these
definitions may change due to evolving design, function, or timing requirements. All AC or DC
operating parameters are subject to change, pending device characterization. Changes are
communicated to customers via emailed Product Change Notifications.
Preliminary A Preliminary Data Sheet describes a device that is in the early stages of volume
manufacturing. AC and DC operating parameters are subject to change, pending further
characterization of multiple wafer lots. Changes are communicated to customers via emailed Product
Change Notifications.
No Label Contents of an unlabeled Data Sheet should be stable, although contents may be updated
due to refined characterization, bug discovery, and manufacturing issues. Changes are communicated
to customers via emailed Product Change Notifications.
To ensure receipt of these notifications, you must be registered with Teknovus customer support system. Please
visit our website at www.teknovus.com, click Login, and follow the displayed instructions. If you are not currently
registered, click Contact Us to locate the office in your region.
Teknovus Inc.
1351 Redwood Way
Petaluma, CA 94954
For more information or to find your local office, visit our website at:
www.teknovus.com
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TK3723 Data Sheet Preliminary

Per-LLID/customer downstream security

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TK3723 Data Sheet Preliminary

Figure 1. Block Diagram of TK3723-Based Turbo-EPONTM Dual OLT

http://www.elecfans.com/ http://www.hqpcb.com/ PCB

TK3723 Data Sheet Preliminary

- Updated power consumption characteristics

- Added Data Sheet progression information (back page)

- Added System Organizations sections

- Removed presently unsupported encryption modes

- Updated supported FLASH list to include Spansion device

- Updated System Organizations section with WDM modes

- Added SDRAM AC characteristics

- Added FLASH layout guidelines

April 25, 2008

- Updated supported FLASH list to include Intel/Numonyx device

- Changed GPI027 pin name to GPI27

- Updated LOC_Px_DNCOMDET pins description in GMII mode

- Corrected max Tc value in Table 21

- Added Leaded package option in TK3723 Ordering Information

- Added ARM_WDOUT_N AC characteristics

- Changed Teknovus Logo

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TK3723 Data Sheet Preliminary

TK3723 Functional Description ..................................................................................................................................... 8

TK3723 Signals Description......................................................................................................................................... 26

TK3723 Electrical Specifications ................................................................................................................................. 60

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TK3723 Data Sheet Preliminary

Ethernet Serial Management Timing ...................................................................................................... 78

TK3723 Mechanical Specifications ............................................................................................................................. 83

TK3723 Ordering Information ...................................................................................................................................... 88

Revision History ................................................................................................................................................. 3

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TK3723 Data Sheet Preliminary

DDRII DRAM Write Timing (BL=8, WL=2, AL=0, WR=2) ................................................................................. 71

Block Diagram of TK3723-Based Turbo-EPONTM Dual OLT.............................................................................. 2

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TK3723 Data Sheet Preliminary

DDRII DRAM Read with Auto-precharge Timing ............................................................................................. 72

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TK3723 Data Sheet Preliminary

TK3723 Functional Description

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TK3723 Data Sheet Preliminary

Figure 2. TK3723 Block Diagram

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TK3723 Data Sheet Preliminary

Two Network-side Interfaces to Two 1.25 Gbps EPONs

Figure 3. Two Distinct EPONs

Two Network-side Interfaces Aggregated to a Single 2.5 Gbps EPON

TK3723 Dual OLT

TK3713 or TK3714/15 ONU

Figure 4. Two Network Interfaces Aggregated to a Single 2.5 Gbps EPON

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TK3723 Data Sheet Preliminary

One Network-side Interface Expanded to Two 1.25 Gbps Separate EPONs

Figure 5. One Network Interface Expanded to Two 1.25 Gbps EPONs

Two Network-side Interfaces Expanded to Two 2.5 Gbps EPONs

Figure 6. Two Network Interfaces Expanded to Two 2.5 Gbps EPONs

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