GENERAL FEATURES
4,194,304 x 8 / 2,097,152 x 16 switchable
Sector Structure
- 8K-Byte x 8 and 64K-Byte x 63
Extra 64K-Byte sector for security
- Features factory locked and identifiable, and customer lockable
Twenty-Four Sector Groups
- Provides sector group protect function to prevent program or erase operation in the protected sector group
- Provides chip unprotect function to allow code changing
- Provides temporary sector group unprotect function
for code changing in previously protected sector groups
Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
Latch-up protected to 250mA from -1V to Vcc + 1V
Low Vcc write inhibit is equal to or less than 1.4V
Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
SOFTWARE FEATURES
Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from
or program data to another sector which is not being
erased
Status Reply
- Data polling & Toggle bits provide detection of program and erase operation completion
Support Common Flash Interface (CFI)
HARDWARE FEATURES
Ready/Busy (RY/BY) Output
- Provides a hardware method of detecting program
and erase operation completion
Hardware Reset (RESET) Input
- Provides a hardware method to reset the internal state
machine to read mode
WP/ACC input pin
- Provides accelerated program capability
PERFORMANCE
High Performance
- Fast access time: 70/90/120ns
- Fast program time: 7us/word typical utilizing accelerate function
- Fast erase time: 1.6s/sector, 112s/chip (typical)
PACKAGE
48-Pin TSOP
48-Ball CSP
GENERAL DESCRIPTION
The MX29LV320T/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and 2M words of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29LV320T/B is packaged in 48-pin TSOP and
48-ball CSP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.
P/N:PM0742
MX29LV320T/B
AUTOMATIC PROGRAMMING
The MX29LV320T/B is byte/word programmable using
the Automatic Programming algorithm. The Automatic
Programming algorithm makes the external system do
not need to have time out sequence nor to verify the
data programmed. The typical chip programming time at
room temperature of the MX29LV320T/B is less than 36
seconds.
Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE .
P/N:PM0742
MX29LV320T/B
PIN CONFIGURATION
48 TSOP
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
NC
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29LV320T/B
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
48-Ball CSP 8mm x 9mm (Ball Pitch = 0.8 mm), Top View, Balls Facing Down
A
B
C
D
E
F
G
H
6
A13
A12
A14
A15
A16
BYTE
Q15/A-1 GND
A9
A8
A10
A11
Q7
Q14
Q13
Q6
WE
RESET
NC
A19
Q5
Q12
Vcc
Q4
RY/BY WP/ACC
A18
A20
Q2
Q10
Q11
Q3
A7
A17
A6
A5
Q0
Q8
Q9
Q1
A3
A4
A2
A1
A0
CE
OE
GND
PIN DESCRIPTION
SYMBOL
A0~A20
Q0~Q14
Q15/A-1
CE
WE
OE
BYTE
RESET
RY/BY
VCC
WP/ACC
GND
NC
LOGIC SYMBOL
PIN NAME
Address Input
15 Data Inputs/Outputs
Q15(Data Input/Output, word mode)
A-1(LSB Address Input, byte mode)
Chip Enable Input
Write Enable Input
Output Enable Input
Word/Byte Selection Input
Hardware Reset Pin, Active Low
Read/Busy Output
3.0 volt-only single power supply
Hardware Write Protect/Acceleration
Pin
Device Ground
Pin Not Connected Internally
21
16 or 8
A0-A20
Q0-Q15
(A-1)
CE
OE
WE
RESET
BYTE
RY/BY
WP/ACC
P/N:PM0742
MX29LV320T/B
BLOCK DIAGRAM
CE
OE
WE
RESET
BYTE
WRITE
CONTROL
LOGIC
STATE
HIGH VOLTAGE
MACHINE
(WSM)
LATCH
BUFFER
STATE
MX29LV320T/B
FLASH
REGISTER
ARRAY
ARRAY
Y-DECODER
AND
X-DECODER
ADDRESS
A0-A20
PROGRAM/ERASE
INPUT
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
P/N:PM0742
MX29LV320T/B
Table 1.a: MX29LV320T SECTOR GROUP ARCHITECTURE
Sector
Group
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
10
10
10
10
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
P/N:PM0742
(x8)
Address Range
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
(x16)
Address Range
000000h-07FFFh
008000h-0FFFFh
010000h-17FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
REV. 1.4, JUL. 04, 2003
MX29LV320T/B
Sector
Group
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
17
18
19
20
21
22
23
24
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
(x8)
Address Range
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3F1FFFh
3F2000h-3F3FFFh
3F4000h-3F5FFFh
3F6000h-3F7FFFh
3F8000h-3F9FFFh
3FA000h-3FBFFFh
3FC000h-3FDFFFh
3FE000h-3FFFFFh
(x16)
Address Range
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-147FFFh
168000h-14FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1F8FFFh
1F9000h-1F9FFFh
1FA000h-1FAFFFh
1FB000h-1FBFFFh
1FC000h-1FCFFFh
1FD000h-1FDFFFh
1FE000h-1FEFFFh
1FF000h-1FFFFFh
Note:The address range is A20:A-1 in byte mode (BYTE=VIL) or A20:A0 in word mode (BYTE=VIH)
Sector Size
(Kbytes/Kwords)
64/32
(x8)
Address Range
3F0000h-3FFFFFh
P/N:PM0742
(x16)
Address Range
1F8000h-1FFFFFh
MX29LV320T/B
Table 1.b: MX29LV320B SECTOR GROUP ARCHITECTURE
Sector
Group
1
2
3
4
5
6
7
8
9
9
9
10
10
10
10
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
16
Sector Size
(Kbytes/Kwords)
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
P/N:PM0742
(x8)
Address Range
000000h-001FFFh
002000h-003FFFh
004000h-005FFFh
006000h-007FFFh
008000h-009FFFh
00A000h-00BFFFh
00C000h-00DFFFh
00E000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
(x16)
Address Range
000000h-000FFFh
001000h-001FFFh
002000h-002FFFh
003000h-003FFFh
004000h-004FFFh
005000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
MX29LV320T/B
Sector
Group
17
17
17
17
18
18
18
18
19
19
19
19
20
20
20
20
21
21
21
21
22
22
22
22
23
23
23
23
24
24
24
24
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
(x8)
Address Range
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
(x16)
Address Range
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
Note:The address range is A20:A-1 in byte mode (BYTE=VIL) or A20:A0 in word mode (BYTE=VIH)
Sector Size
(Kbytes/Kwords)
64/32
(x8)
Address Range
000000h-00FFFFh
P/N:PM0742
(x16)
Address Range
00000h-07FFFh
MX29LV320T/B
Table 2. BUS OPERATION--1
Operation
CE
OE
WE RESET WP/ACC
Addresses
Q0~Q7
(Note 2)
Read
L/H
AIN
DOUT
Q8 ~ Q15
Byte=VIH
Byte=VIL
DOUT
Q8-A14
=High-Z
Write (Note 1)
Note 3
AIN
DIN
DIN
Accelerate
V HH
AIN
DIN
DIN
VCC
VCC
High-Z
High-Z
High-Z
Q15=A-1
Program
Standby
0.3V
0.3V
Output Disable
L/H
High-Z
High-Z
High-Z
Reset
L/H
High-Z
High-Z
High-Z
Sector Group
VID
L/H
DIN
High-Z
Protect (Note 2)
Chip Unprotect
VID
Note 3
(Note 2)
Temporary Sector
VID
Note 3
AIN
DIN
Group Unprotect
Legend:
L=Logic LOW=VIL, H=Logic High=VIH, VID=12.00.5V, VHH=11.5-12.5V, X=Don't Care, AIN=Address IN, DIN=Data IN,
DOUT=Data OUT
Notes:
1. When the WP/ACC pin is at VHH, the device enters the accelerated program mode. See "Accelerated Program
Operations" for more information.
2.The sector group protect and chip unprotect functions may also be implemented via programming equipment. See
the "Sector Group Protection and Chip Unprotection" section.
3.If WP/ACC=VIL, the two outermost boot sectors remain protected. If WP/ACC=VIH, the two outermost boot sector
protection depends on whether they were last protected or unprotected using the method described in "Sector/
Sector Block Protection and Unprotection". If WP/ACC=VHH, all sectors will be unprotected.
4.DIN or Dout as required by command sequence, data polling, or sector protection algorithm.
5.Address are A20:A0 in word mode (BYTE=VIH), A20:A-1 in byte mode (BYTE=VIL).
P/N:PM0742
MX29LV320T/B
BUS OPERATION--2
Operation
Read Silicon ID
Manufacturer Code
Read Silicon ID
MX29LV320T
Read Silicon ID
MX29LV320B
Sector Group Protect
Chip Unprotect
Sector Protect
Verification
Security Sector
Indicater
Bit (Q7)
CE
OE
WE
A20
to
A12
X
A11
to
A10
X
A9
A6
VID
A8
to
A7
X
A5
to
A2
X
VID
VID
L
L
L
VID
VID
L
L
L
H
SA
X
SA
X
X
X
VID
VID
VID
VID
A1
A0
Q0-Q7
Q8-Q15
C2H
A7H
X
X
X
L
H
L
X
X
X
X
X
H
X
X
L
22h(word)
X (byte)
A8H 22h(word)
X (byte)
X
X
X
X
01h(1),
X
or 00h
99h(2),
X
or 19h
Notes:
1.Code=00h means unprotected, or code=01h protected.
2.Code=99 means factory locked, or code=19h not facory locked.
P/N:PM0742
10
MX29LV320T/B
REQUIREMENTS FOR READING ARRAY
DATA
STANDBY MODE
MX29LV320T/B can be set into Standby mode with two
different approaches. One is using both CE and RESET
pins and the other one is using RESET pin only.
P/N:PM0742
11
MX29LV320T/B
on address pin A9 and control pin OE, (suggest VID =
12V) A6 = VIL and CE = VIL.(see Table 2) Programming
of the protection circuitry begins on the falling edge of
the WE pulse and is terminated on the rising edge. Please
refer to sector group protect algorithm and waveform.
OUTPUT DISABLE
With the OE input at a logic high level (VIH), output from
the devices are disabled. This will cause the output pins
to be in a high impedance state.
MX29LV320T/B also provides another method which requires VID on the RESET only. This method can be implemented either in-system or via programming equipment.
This method uses standard microprocessor bus cycle
timing.
RESET OPERATION
The RESET pin provides a hardware method of resetting
the device to reading array data. When the RESET pin is
driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write
commands for the duration of the RESET pulse. The
device also resets the internal state machine to reading
array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another
command sequence, to ensure data integrity
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 (
with CE and OE at VIL and WE at VIH). When A1=1, it
will produce a logical "1" code at device output Q0 for a
protected sector. Otherwise the device will produce 00H
for the unprotected sector. In this mode, the addresses,
except for A1, are don't care. Address locations with
A1= VIL are reserved to read manufacturer and device
codes.(Read Silicon ID)
MX29LV320T/B also provides another method which requires VID on the RESET only. This method can be implemented either in-system or via programming equipment.
This method uses standard microprocessor bus cycle
timing.
P/N:PM0742
12
MX29LV320T/B
Performing a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected sector. It
is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8K Byte boot
sectors were last set to be protected or unprotected. That
is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in "Sector/Sector
Group Protection and Chip Unprotection".
P/N:PM0742
13
MX29LV320T/B
RESET may be at either VIH or VID. This allows in-system protection of the without raising any device pin to a
high voltage. Note that this method is only applicable to
the Security Sector.
DATA PROTECTION
The MX29LV320T/B is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transition. During power up the device automatically resets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down transition or system noise.
When VCC is less than VLKO the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional write
when VCC is greater than VLKO.
If the security feature is not required, the Security Sector can be treated as an additional Flash memory space,
expanding the size of the available Flash array by 64
Kbytes (32 Kwords). The Security Sector can be read,
programmed, and erased as often as required. The Security Sector area can be protected using one of the
following procedures:
P/N:PM0742
14
MX29LV320T/B
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
POWER-UP SEQUENCE
The MX29LV320T/B powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.
P/N:PM0742
15
MX29LV320T/B
TABLE 3. MX29LV320T/B COMMAND DEFINITIONS
First Bus
Command
Bus
Read(Note 5)
RA
RD
Reset(Note 4)
XXX
F0
Cycle
Cycle
Fourth Bus
Cycle
Cycle
Fifth Bus
Cycle
Data
Sixth Bus
Cycle
Automatic Select(Note 5)
Manufacturer ID
Device ID
Word
555
AA
2AA
55
555
90
X00
C2H
Byte
AAA
AA
555
55
AAA
90
X00
C2H
Word
555
AA
2AA
55
555
90
X01
ID
Byte
AAA
AA
555
55
AAA
90
X02
555
AA
2AA
55
555
90
X03
AAA
AA
555
55
AAA
90
X06
99/19
Word
555
AA
2AA
55
555
90
(SA)X02 00/01
(Note 7)
Byte
AAA
AA
555
55
AAA
90
(SA)X04
Word
555
AA
2AA
55
555
88
Region
Byte
AAA
AA
555
55
AAA
88
Word
555
AA
2AA
55
555
90
XXX
00
Byte
AAA
AA
555
55
AAA
90
XXX
00
Word
555
AA
2AA
55
555
A0
PA
PD
Byte
AAA
AA
555
55
AAA
A0
PA
PD
Word
555
AA
2AA
55
555
80
555
AA
2AA 55
555
Byte
AAA
AA
555
55
AAA
80
AAA
AA
555
AAA 10
55
10
Word
555
AA
2AA
55
555
80
555
AA
2AA 55
SA
30
Byte
AAA
AA
555
55
AAA
80
AAA
AA
555
SA
30
Word
55
98
Byte
AA
98
Erase Suspend(Note 9)
SA
B0
SA
30
55
Legend:
X=Don't care
RA=Address of the memory location to be read.
RD=Data read from location RA during read operation.
PA=Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE or CE
pulse.
Notes:
1.
2.
3.
4.
16
MX29LV320T/B
READING ARRAY DATA
RESET COMMAND
Writing the reset command to the device resets the
device to reading array data. Address bits are don't care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.
The Security Sector provides a secured area which contains a random, sixteen-byte electronic serial
number.(ESN)
The reset command may be written between the sequence cycles in a program command sequence before
programming begins. This resets the device to reading
array data (also applies to programming in Erase Suspend
mode). Once programming begins, however, the device
ignores reset commands until the operation is complete.
The system can access the Security Sector area by issuing the three-cycle "Enter Security Sector command
sequence. The device continues to access the security
section area until the system issues the four-cycle Exit
Security Sector command sequence. The Exit Security
Sector command sequence returns the device to normal
operation.
The reset command may be written between the sequence cycles in an Automatic Select command
sequence. Once in the Automatic Select mode, the reset
command must be written to return to reading array data
(also applies to Automatic Select during Erase Suspend).
P/N:PM0742
17
MX29LV320T/B
verifies the programmed cell margin. Table 3 shows the
address and data requirements for the byte/word program
command sequence.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming
operation. The Byte/Word Program command sequence
should be reinitiated once the device has reset to reading
array data, to ensure data integrity.
The MX29LV320T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read
silicon ID command sequence into the command register. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of A7H/A8H for MX29LV320T/B.
A0
A1
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Code (Hex)
Manufacture code
VIL
VIL
C2H
VIH VIL
22A7H
VIH VIL
22A8H
The system can determine the status of the erase operation by using Q7, Q6, Q2, or RY/BY. See "Write Operation Status" for information on these status bits. When
the Automatic Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 5 illustrates the algorithm for the erase operation.See the Erase/Program Operations tables in "AC
Characteristics" for parameters, and to Figure 4 for timing diagrams.
P/N:PM0742
18
MX29LV320T/B
Sector Erase operation. When the Erase Suspend command is issued during the sector erase operation, the
device requires a maximum 20us to suspend the sector
erase operation. However, When the Erase Suspend command is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation. After this command has
been executed, the command register will initiate erase
suspend mode. The state machine will return to read
mode automatically after suspend is ready. At this time,
state machine only allows the command register to respond to the Erase Resume, program data to, or read
data from any sector not selected for erasure. The system can use Q7, or Q6 and Q2 together, to determine if
a sector is actively erasing or is erase-suspended.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing.
ERASE SUSPEND
This command only has meaning while the state machine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
P/N:PM0742
19
MX29LV320T/B
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY.
Table 5 and the following subsections describe the functions of these bits. Q7, RY/BY, and Q6 each offer a
method for determining whether a program or erase operation is complete or in progress. These three bits are
discussed first.
Q7
Note1
Q6
Q5
Note2
Q3
Q2
RY/BY
Q7
Toggle
N/A
No
Toggle
Toggle
Toggle
No
Toggle
N/A Toggle
Data
Data
Data Data
Q7
Toggle
N/A
N/A
Q7
Toggle
N/A
No
Toggle
Toggle
Toggle
Q7
Toggle
N/A
N/A
In Progress
Erase Suspended Mode
Notes:
1. Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.
2. Performing successive read operations from any address will cause Q6 to toggle.
3. Reading the byte/word address being programmed while in the erase-suspend program mode will indicate logic "1"
at the Q2 bit.
However, successive reads from the erase-suspended sector will cause Q2 to toggle.
P/N:PM0742
20
MX29LV320T/B
after the rising edge of the final WE or CE, whichever
happens first pulse in the command sequence (prior to
the program or erase operation), and during the sector
time-out.
During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6
to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6
stops toggling.
During the Automatic Program algorithm, the device outputs on Q7 the complement of the datum programmed
to Q7. This Q7 status also applies to programming during Erase Suspend. When the Automatic Program algorithm is complete, the device outputs the datum programmed to Q7. The system must provide the program
address to read valid status information on Q7. If a program address falls within a protected sector, Data Polling on Q7 is active for approximately 1 us, then the device returns to reading array data.
After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles for
100us and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended.
When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When
the device enters the Erase Suspend mode, Q6 stops
toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended.
Alternatively, the system can use Q7.
During the Automatic Erase algorithm, Data Polling produces a "0" on Q7. When the Automatic Erase algorithm
is complete, or if the device enters the Erase Suspend
mode, Data Polling produces a "1" on Q7. This is analogous to the complement/true datum out-put described
for the Automatic Program algorithm: the erase function
changes all the bits in a sector to "1" prior to this, the
device outputs the "complement, or "0". The system
must provide an address within any of the sectors selected for erasure to read valid status information on Q7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on
Q7 is active for approximately 100 us, then the device
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether
that sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE or CE, whichever
happens first pulse in the command sequence.
Q6:Toggle BIT I
Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
P/N:PM0742
21
MX29LV320T/B
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sectors and mode information. Refer to
Table 5 to compare outputs for Q2 and Q6.
Q5:Program/Erase Timing
Q5 will indicate if the program or erase time has exceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the
P/N:PM0742
22
MX29LV320T/B
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command
has been accepted, the system software should check
the status of Q3 prior to and following each subsequent
sector erase command. If Q3 were high on the second
status check, the command may not have been accepted.
RY/BY:READY/BUSY OUTPUT
The RY/BY is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in progress
or complete. The RY/BY status is valid after the rising
edge of the final WE pulse in the command sequence.
Since RY/BY is an open-drain output, several RY/BY pins
can be tied together in parallel with a pull-up resistor to
VCC .
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device
is ready to read array data (includ-ing during the Erase
Suspend mode), or is in the standby mode.
23
MX29LV320T/B
Table 6-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description
Address (h)
Address (h)
(Word Mode)
(Byte Mode)
10
20
0051
11
22
0052
12
24
0059
13
26
0002
14
28
0000
15
2A
0040
16
2C
0000
17
2E
0000
18
30
0000
19
32
0000
1A
34
0000
Address (h)
Address (h)
Data (h)
(Word Mode)
(Byte Mode)
1B
36
0027
1C
38
0036
1D
3A
0000
1E
3C
0000
1F
3E
0004
20
40
0000
21
42
000A
22
44
0000
23
46
0005
24
48
0000
25
4A
0004
26
4C
0000
Data (h)
Typical timeout for maximum size buffer write (2 us) (not supported)
N
P/N:PM0742
24
MX29LV320T/B
Table 6-3. CFI Mode: Device Geometry Data Values
Description
Address (h)
Address (h)
(Word Mode)
(Byte Mode)
27
4E
0016
28
50
0002
29
52
0000
2A
54
0000
2B
56
0000
2C
58
0002
2D
5A
0007
2E
5C
0000
2F
5E
0020
30
60
0000
31
62
003E
32
64
0000
33
66
0000
34
68
0001
35
6A
0000
36
6C
0000
37
6E
0000
38
70
0000
39
72
0000
3A
74
0000
3B
76
0000
3C
78
0000
P/N:PM0742
Data (h)
25
MX29LV320T/B
Table 6-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Description
Address (h)
Address (h)
(Word Mode)
(Byte Mode)
40
80
0050
41
82
0052
42
84
0049
43
86
0031
44
88
0031
45
8A
0000
46
8C
0002
47
8E
0004
48
90
0001
49
92
0004
4A
94
0000
4B
96
0000
4C
98
0000
4D
9A
00B5
4E
9C
00C5
4F
9E
000X
Data (h)
P/N:PM0742
26
MX29LV320T/B
ABSOLUTE MAXIMUM RATINGS
OPERATING RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
A9, OE, and
RESET (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns.
2. Minimum DC input voltage on pins A9, OE, and
RESET is -0.5 V. During voltage transitions, A9, OE,
and RESET may overshoot VSS to -2.0 V for periods
of up to 20 ns. Maximum DC input voltage on pin A9
is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.
3. No more than one output may be shorted to ground at
a time. Duration of the short circuit should not be
greater than one second.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect
device reliability.
P/N:PM0742
27
MX29LV320T/B
DC CHARACTERISTICS VCC=2.7V~3.6V
Para- Description
meter
ILI
Input Load Current
(Note 1)
ILIT A9 Input Load Current
ILO
ICC1
ICC2
ICC3
ICC4
ICC5
IACC
VIL
VIH
VHH
VID
VOL
VOH1
VOH2
VLKO
Test Conditions
C
TA=0
C to 70
Min Typ Max
1.0
C
TA=-40
C to 85
Min Typ Max Unit
1.0 uA
35
45
uA
1.0
1.0
uA
10
2
15
16
4
30
10
2
15
16
4
30
mA
mA
mA
0.2
15
0.2
15
uA
0.2
15
0.2
15
uA
0.2
15
0.2
15
uA
5
15
10
5
10
mA
30
15
30
mA
0.8
-0.5
0.8
V
Vcc+0.3 0.7xVcc
Vcc+0.3 V
12.5
11.5
12.5
V
12.5
11.5
0.45
2.1
12.5
0.45
0.85Vcc
Vcc-0.4
1.4
2.1
Notes:
1. On the WP/ACC pin only, the maximum input load current when WP/ACC = VIL is 5.0uA / VIH is 3.0uA.
2. Maximum ICC specifications are tested with VCC = VCC max.
3. The ICC current listed is typically is less than 2 mA/MHz, with OE at VIH. Typical specifications are for VCC = 3.0V.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep
mode current is 200 nA.
6. Not 100% tested.
P/N:PM0742
28
MX29LV320T/B
SWITCHING TEST CIRCUITS
TEST SPECIFICATIONS
DEVICE UNDER
Test Condition
Output Load
Output Load Capacitance,CL
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
Input timing measurement
reference levels
Output timing measurement
reference levels
1.6K ohm
+3.3V
TEST
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
70
90 120 Unit
1 TTL gate
30
30 100 pF
5
0.0-3.0
1.5
ns
V
V
1.5
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
3.0V
1.5V
Measurement Level
1.5V
0.0V
INPUT
OUTPUT
P/N:PM0742
29
MX29LV320T/B
AC CHARACTERISTICS
Symbol
tACC
C, VCC=2.7V~3.6V
TA=-40
C to 85
DESCRIPTION
Address to output delay
tCE
tOE
tDF
tOH
CONDITION
CE=VIL
MAX
OE=VIL
OE=VIL
MAX
MAX
MAX
MIN
70
70
90
90
120
120
Unit
ns
70
40
30
0
90
40
30
0
120
50
30
0
ns
ns
ns
ns
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
70
70
70
0
45
45
0
50
0
0
0
0
10
90
90
90
0
45
45
0
50
0
0
0
0
10
120
120
120
0
50
50
0
50
0
0
0
0
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN
MIN
MIN
MIN
MIN
MIN
MAX
MIN
MIN
TYP
TYP
TYP
0
0
45
30
45
30
90
0
0
9
11
7
0
0
45
30
45
30
90
0
0
9
11
7
0
0
50
30
50
30
90
0
0
9
11
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
TYP
MAX
0.9
50
0.9
50
0.9
50
sec
us
P/N:PM0742
30
MX29LV320T/B
Fig 1. COMMAND WRITE OPERATION
VCC
Addresses
3V
VIH
ADD Valid
VIL
tAH
tAS
WE
VIH
VIL
tOES
tWPH
tWP
tCWC
CE
VIH
VIL
tCS
OE
tCH
VIH
VIL
tDS
tDH
VIH
Data
DIN
VIL
P/N:PM0742
31
MX29LV320T/B
READ/RESET OPERATION
Fig 2. READ TIMING WAVEFORMS
tRC
VIH
ADD Valid
Addresses
VIL
tCE
VIH
CE
VIL
VIH
WE
VIL
OE
VIH
VIL
Outputs
tDF
tOE
tOEH
VOH
tACC
HIGH Z
tOH
DATA Valid
HIGH Z
VOL
P/N:PM0742
32
MX29LV320T/B
AC CHARACTERISTICS
Parameter
Description
tREADY1
MAX
20
us
MAX
500
ns
tRP1
MIN
10
us
tRP2
MIN
500
ns
tRH
MIN
70
ns
tRB1
MIN
ns
tRB2
MIN
50
ns
CE, OE
tRH
RESET
tRP2
tReady2
tReady1
RY/BY
tRB1
CE, OE
WE
tRB2
RESET
tRP1
P/N:PM0742
33
MX29LV320T/B
ERASE/PROGRAM OPERATION
Fig 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
tWC
2AAh
Address
tAS
VA
SA
555h for chip erase
VA
tAH
CE
tCH
tGHWL
OE
tWHWH2
tWP
WE
tCS
tWPH
tDS tDH
55h
In
Progress Complete
10h
Data
tBUSY
tRB
RY/BY
tVCS
VCC
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
P/N:PM0742
34
MX29LV320T/B
Fig 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Data Poll
from system
YES
No
DATA = FFh ?
YES
P/N:PM0742
35
MX29LV320T/B
Fig 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
tWC
Sector
Address 0
2AAh
Address
tAS
Sector
Address 1
Sector
Address n
VA
VA
tAH
CE
tCH
tGHWL
OE
WE
tCS
tWHWH2
tBAL
tWP
tWPH
tDS tDH
55h
30h
30h
30h
In
Progress Complete
Data
tBUSY
tRB
RY/BY
tVCS
VCC
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
P/N:PM0742
36
MX29LV320T/B
Fig 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
NO
Last Sector
to Erase ?
YES
Data Poll from System
NO
Data=FFh?
YES
P/N:PM0742
37
MX29LV320T/B
Fig 8. ERASE SUSPEND/RESUME FLOWCHART
START
NO
ERASE SUSPEND
Reading or
Programming End
NO
YES
Write Data 30H
ERASE RESUME
Continue Erase
Another
Erase Suspend ?
NO
YES
P/N:PM0742
38
MX29LV320T/B
Fig 9. AUTOMATIC PROGRAM TIMING WAVEFORMS
Program Command Sequence(last two cycle)
tWC
555h
Address
tAS
PA
PA
PA
tAH
CE
tCH
tGHWL
OE
tWHWH1
tWP
WE
tCS
tWPH
tDS
tDH
A0h
Status
PD
DOUT
Data
tBUSY
tRB
RY/BY
tVCS
VCC
NOTES:
1.PA=Program Address, PD=Program Data, DOUT is the true data the program address
(11.5V ~ 12.5V)
VHH
WP/ACC
VIL or VIH
VIL or VIH
tVHH
tVHH
P/N:PM0742
39
MX29LV320T/B
Fig 11. CE CONTROLLED WRITE TIMING WAVEFORM
PA for program
SA for sector erase
555 for chip erase
Data Polling
Address
PA
tWC
tAS
tAH
tWH
WE
tGHEL
OE
tCP
tWHWH1 or 2
CE
tCPH
tWS
tDS
tBUSY
tDH
Q7
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET
RY/BY
NOTES:
1. PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.
2. Figure indicates the last two bus cycles of the command sequence.
P/N:PM0742
40
MX29LV320T/B
Fig 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Data Poll
from system
Increment
Address
No
Verify Data OK ?
YES
No
Last Address ?
YES
P/N:PM0742
41
MX29LV320T/B
SECTOR GROUP PROTECT/CHIP UNPROTECT
Fig 13. Sector Group Protect/Chip Unprotect Waveform (RESET Control)
VID
VIH
RESET
SA, A6
A1, A0
Valid (note2)
Valid (note2)
60h
1us
60h
Valid (note2)
Verify
40h
Status
CE
WE
OE
Note:
1. If TA range during 0C to 70C, the time out timing is 15ms.
If TA range during -40C to 85C, the time out timing is 18ms.
2. For sector group protect A6=0, A1=1, A0=0 ; for chip unprotect A6=1, A1=1, A0=0
P/N:PM0742
42
MX29LV320T/B
Fig 14. SECTOR GROUP PROTECT TIMING WAVEFORM (A9, OE Control)
A1
A6
12V
3V
A9
tVLHT
Verify
12V
3V
OE
tVLHT
tVLHT
tWPP 1
WE
tOESP
CE
Data
01H
F0H
tOE
A20-A12
Sector Address
P/N:PM0742
43
MX29LV320T/B
Fig 15. SECTOR GROUP PROTECTION ALGORITHM (A9, OE Control)
START
PLSCNT=1
Activate WE Pulse
No
PLSCNT=32?
No
Data=01H?
Yes
Device Failed
Protect Another
Sector?
Yes
P/N:PM0742
44
MX29LV320T/B
Fig 16. CHIP UNPROTECT TIMING WAVEFORM (A9, OE Control)
A1
12V
3V
A9
tVLHT
A6
Verify
12V
3V
OE
tVLHT
tVLHT
tWPP 2
WE
tOESP
CE
Data
00H
F0H
tOE
P/N:PM0742
45
MX29LV320T/B
Fig 17. CHIP UNPROTECT FLOWCHART(A9, OE Control)
START
PLSCNT=1
Set OE=A9=VID
CE=VIL, A6=1
Activate WE Pulse
Increment
PLSCNT
Set OE=CE=VIL
A9=VID, A1=1, A6=A0=0
Data=00H?
Increment
Sector Addr
Yes
No
No
PLSCNT=1000?
Yes
Device Failed
Yes
Remove VID from A9
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
Note:
1. If TA range during 0C to 70C, the time out timing is 15ms.
If TA range during -40C to 85C, the time out timing is 18ms.
P/N:PM0742
46
MX29LV320T/B
Fig 18. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH RESET=VID
START
START
Protect all sectors:
The indicated portion of
the sector protect algorithm
must be performed
for all unprotected sectors
prior to issuing the first
sector unprotect address
PLSCNT=1
RESET=VID
Wait 1us
PLSCNT=1
RESET=VID
Wait 1us
Temporary Sector
Unprotect Mode
No
First Write
Cycle=60h?
First Write
Cycle=60h?
No
Temporary Sector
Unprotect Mode
Yes
Yes
All sectors
protected?
Yes
Set up first sector address
Wait 150us
Chip Unprotect:
Write 60h to sector
address with
A6=1, A1=1, A0=0
Reset
PLSCNT=1
Increment PLSCNT
Time Out Timing (note 1)
Read from
sector address
with
A6=0, A1=1, A0=0
No
Increment PLSCNT
No
PLSCNT=25?
Yes
Data=01h?
Read from
sector address
with
A6=1, A1=1, A0=0
Yes
No
Device failed
Protect another
sector?
Sector Protect
Algorithm
Reset
PLSCNT=1
Yes
No
PLSCNT=1000?
Data=00h?
No
Yes
Yes
Device failed
Last sector
verified?
Chip Unprotect
Algorithm
No
Yes
Remove VID from RESET
Note:
1. If TA range during 0C to 70C, the time out timing is 15ms.
If TA range during -40C to 85C, the time out timing is 18ms.
P/N:PM0742
47
MX29LV320T/B
Table 7. TEMPORARY SECTOR GROUP UNPROTECT
Parameter Std. Description
tVIDR
Min
500
ns
tRSP
Min
us
Note:
Not 100% tested
RESET
0 or 3V
VIL or VIH
tVIDR
tVIDR
CE
WE
tRSP
RY/BY
P/N:PM0742
48
MX29LV320T/B
Fig 20. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART
Start
P/N:PM0742
49
MX29LV320T/B
Fig 21. SILICON ID READ TIMING WAVEFORM
VCC
3V
VID
VIH
VIL
ADD
A9
ADD
A0
VIH
A1
VIH
VIL
tACC
tACC
VIL
VIH
ADD
VIL
CE
VIH
VIL
WE
VIH
tCE
VIL
OE
VIH
tOE
VIL
tDF
tOH
tOH
VIH
DATA
Q0-Q7
DATA OUT
DATA OUT
C2H
VIL
P/N:PM0742
50
MX29LV320T/B
WRITE OPERATION STATUS
Fig 22. DATA POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
tRC
Address
VA
VA
tACC
tCE
CE
tCH
tOE
OE
tOEH
tDF
WE
tOH
Q7
Status Data
Complement
True
Valid Data
Q0-Q6
Status Data
Status Data
True
Valid Data
High Z
High Z
tBUSY
RY/BY
NOTES:
VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.
P/N:PM0742
51
MX29LV320T/B
Fig 23. Data Polling Algorithm
START
Read Q7~Q0
Add. = VA (1)
Q7 = Data ?
Yes
No
No
Q5 = 1 ?
Yes
Read Q7~Q0
Add. = VA
Yes
Q7 = Data ?
(2)
No
PASS
FAIL
Notes:
1. VA=valid address for programming or erasure.
2. Q7 should be rechecked even Q5="1"because Q7 may change simultaneously with Q5.
P/N:PM0742
52
MX29LV320T/B
Fig 24. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
tRC
Address
VA
VA
VA
VA
tACC
tCE
CE
tCH
tOE
OE
tOEH
tDF
WE
tOH
Q6/Q2
Valid Status
(first read)
Valid Status
Valid Data
(second read)
(stops toggling)
Valid Data
tBUSY
RY/BY
NOTES:
VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
P/N:PM0742
53
MX29LV320T/B
Fig 25. Toggle Bit Algorithm
START
Read Q7~Q0
Read Q7~Q0
(Note 1)
NO
Toggle Bit Q6
=Toggle?
YES
NO
Q5=1?
YES
(Note 1,2)
Note:
1.Read toggle bit twice to determine whether or not it is toggling.
2.Recheck toggle bit because it may stop toggling as Q5 changes to "1".
P/N:PM0742
54
MX29LV320T/B
Fig 26. Q6 versus Q2
Enter Embedded
Erasing
Erase
Suspend
Erase
WE
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
Q6
Q2
NOTES:
The system can use OE or CE to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended
P/N:PM0742
55
MX29LV320T/B
ERASE AND PROGRAMMING PERFORMANCE(1)
LIMITS
PARAMETER
MIN.
TYP.(2)
MAX.
UNITS
0.9
15
sec
35
50
sec
300
us
11
360
us
Byte Mode
36
108
sec
Word Mode
24
72
sec
210
us
100,000
Cycles
LATCH-UP CHARACTERISTICS
MIN.
MAX.
Input Voltage with respect to GND on all pins except I/O pins
-1.0V
12.5V
-1.0V
Vcc + 1.0V
-100mA
+100mA
VCC Current
Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.
Parameter Description
Test Set
TYP
MAX
UNIT
CIN
Input Capacitance
VIN=0
7.5
pF
COUT
Output Capacitance
VOUT=0
8.5
12
pF
CIN2
VIN=0
7.5
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA=25C, f=1.0MHz
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150C
10
Years
125C
20
Years
P/N:PM0742
56
MX29LV320T/B
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO.
ACCESS TIME
Ball Pitch/
(ns)
Ball Size
MX29LV320TTC-70
70
48 Pin TSOP
MX29LV320BTC-70
70
48 Pin TSOP
MX29LV320TTI-70
70
48 Pin TSOP
MX29LV320BTI-70
70
48 Pin TSOP
MX29LV320TTC-90
90
48 Pin TSOP
MX29LV320BTC-90
90
48 Pin TSOP
MX29LV320TTI-90
90
48 Pin TSOP
MX29LV320BTI-90
90
48 Pin TSOP
MX29LV320TTI-12
120
48 Pin TSOP
MX29LV320BTI-12
120
48 Pin TSOP
MX29LV320TXBC-70
70
0.8mm/0.3mm
48-Ball CSP
MX29LV320BXBC-70
70
0.8mm/0.3mm
48-Ball CSP
MX29LV320TXEC-70
70
0.8mm/0.4mm
48-Ball CSP
MX29LV320BXEC-70
70
0.8mm/0.4mm
48-Ball CSP
MX29LV320TXBI-70
70
0.8mm/0.3mm
48-Ball CSP
MX29LV320BXBI-70
70
0.8mm/0.3mm
48-Ball CSP
MX29LV320TXEI-70
70
0.8mm/0.4mm
48-Ball CSP
MX29LV320BXEI-70
70
0.8mm/0.4mm
48-Ball CSP
MX29LV320TXBC-90
90
0.8mm/0.3mm
48-Ball CSP
MX29LV320BXBC-90
90
0.8mm/0.3mm
48-Ball CSP
MX29LV320TXEC-90
90
0.8mm/0.4mm
48-Ball CSP
MX29LV320BXEC-90
90
0.8mm/0.4mm
48-Ball CSP
MX29LV320TXBI-90
90
0.8mm/0.3mm
48-Ball CSP
MX29LV320BXBI-90
90
0.8mm/0.3mm
48-Ball CSP
MX29LV320TXEI-90
90
0.8mm/0.4mm
48-Ball CSP
MX29LV320BXEI-90
90
0.8mm/0.4mm
48-Ball CSP
MX29LV320TXBC-12
120
0.8mm/0.3mm
48-Ball CSP
MX29LV320BXBC-12
120
0.8mm/0.3mm
48-Ball CSP
MX29LV320TXEC-12
120
0.8mm/0.4mm
48-Ball CSP
MX29LV320BXEC-12
120
0.8mm/0.4mm
48-Ball CSP
MX29LV320TXBI-12
120
0.8mm/0.3mm
48-Ball CSP
MX29LV320BXBI-12
120
0.8mm/0.3mm
48-Ball CSP
MX29LV320TXEI-12
120
0.8mm/0.4mm
48-Ball CSP
MX29LV320BXEI-12
120
0.8mm/0.4mm
48-Ball CSP
P/N:PM0742
PACKAGE
Remark
57
MX29LV320T/B
PART NO.
ACCESS TIME
Ball Pitch/
PACKAGE
Remark
(ns)
Ball Size
MX29LV320TTC-70G
70
48 Pin TSOP
PB free
MX29LV320BTC-70G
70
48 Pin TSOP
PB free
MX29LV320TTI-70G
70
48 Pin TSOP
PB free
MX29LV320BTI-70G
70
48 Pin TSOP
PB free
MX29LV320TTC-90G
90
48 Pin TSOP
PB free
MX29LV320BTC-90G
90
48 Pin TSOP
PB free
MX29LV320TTI-90G
90
48 Pin TSOP
PB free
MX29LV320BTI-90G
90
48 Pin TSOP
PB free
MX29LV320TTI-12G
120
48 Pin TSOP
PB free
MX29LV320BTI-12G
120
48 Pin TSOP
PB free
MX29LV320TXBC-70G
70
0.8mm/0.3mm
48-Ball CSP
PB free
MX29LV320BXBC-70G
70
0.8mm/0.3mm
48-Ball CSP
PB free
MX29LV320TXEC-70G
70
0.8mm/0.4mm
48-Ball CSP
PB free
MX29LV320BXEC-70G
70
0.8mm/0.4mm
48-Ball CSP
PB free
MX29LV320TXBI-70G
70
0.8mm/0.3mm
48-Ball CSP
PB free
MX29LV320BXBI-70G
70
0.8mm/0.3mm
48-Ball CSP
PB free
MX29LV320TXEI-70G
70
0.8mm/0.4mm
48-Ball CSP
PB free
MX29LV320BXEI-70G
70
0.8mm/0.4mm
48-Ball CSP
PB free
MX29LV320TXBC-90G
90
0.8mm/0.3mm
48-Ball CSP
PB free
MX29LV320BXBC-90G
90
0.8mm/0.3mm
48-Ball CSP
PB free
MX29LV320TXEC-90G
90
0.8mm/0.4mm
48-Ball CSP
PB free
MX29LV320BXEC-90G
90
0.8mm/0.4mm
48-Ball CSP
PB free
MX29LV320TXBI-90G
90
0.8mm/0.3mm
48-Ball CSP
PB free
MX29LV320BXBI-90G
90
0.8mm/0.3mm
48-Ball CSP
PB free
MX29LV320TXEI-90G
90
0.8mm/0.4mm
48-Ball CSP
PB free
MX29LV320BXEI-90G
90
0.8mm/0.4mm
48-Ball CSP
PB free
MX29LV320TXBC-12G
120
0.8mm/0.3mm
48-Ball CSP
PB free
MX29LV320BXBC-12G
120
0.8mm/0.3mm
48-Ball CSP
PB free
MX29LV320TXEC-12G
120
0.8mm/0.4mm
48-Ball CSP
PB free
MX29LV320BXEC-12G
120
0.8mm/0.4mm
48-Ball CSP
PB free
MX29LV320TXBI-12G
120
0.8mm/0.3mm
48-Ball CSP
PB free
MX29LV320BXBI-12G
120
0.8mm/0.3mm
48-Ball CSP
PB free
MX29LV320TXEI-12G
120
0.8mm/0.4mm
48-Ball CSP
PB free
MX29LV320BXEI-12G
120
0.8mm/0.4mm
48-Ball CSP
PB free
P/N:PM0742
58
MX29LV320T/B
PACKAGE INFORMATION
P/N:PM0742
59
MX29LV320T/B
P/N:PM0742
60
MX29LV320T/B
P/N:PM0742
61
MX29LV320T/B
REVISION HISTORY
Revision No. Description
1.0
1. To removed "Advanced Information"
2. To modify Package Information
3. To modify sector erasy timing wavefrom and added tBAL
timing in the AC Characteristics table
1.1
1. To modify the chip erase time from typ. 112sec to
typ. 35sec/max.50sec
2. To modify the sector erase time from typ. 1.6sec to typ. 0.9sec
1.2
1. To modify ILIT parameter value from 35uA to 45uA during
TA=-40C to 85C in DC Characteristics
2. To modify the chip unprotection time out timing during
TA=-40C to 85C range from 15ms to 18ms
3. Remove 70/90R information
1.3
1. To added PB-free part no. in ordering information
1.4
1. To corrected the fast program timing from normal program speed
to ACC program speed
P/N:PM0742
Page
P1
P57~59
P30,36
Date
NOV/21/2002
P2,56
FEB/10/2003
P30,56
P28
MAR/26/2003
P42,46,47
P27~30, 57
P58
APR/23/2003
P1
JUL/04/2003
62
MX29LV320T/B
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.