Homework #1

Fall EE120
Student: Rafael Silva

ID: 010068565

1. What are the features of M3 & M4

Performance:
o Both microprocessor have three-stage pipeline, what allow them to execute
most instructions in one cycle of clock;
o Multiple bus interfaces, simultaneous instructions and data accesses;
o Two 16bits instructions can be fetched at time;
Code density:
o Thumb-2 technology permit that 32 and 16bits instructions work together
without any switch state.
o Various memory addressing;
o Support for hardware divide instructions and Multiply and Accumulate;
o Single instruction, multiple data support, only for Cortex M-4;
Low Power:
o The three-stage pipeline and high code density allow a great power saving with
good performance;
o Low power features such multiples sleep modes and integrated architectural
clock gating support, which allows sections not in use to be deactivated;
Memory systems:
o Total 4GB of addressable memory space with linear 32-bit addressing;
o Easy access to memory-mapped peripherals inside the processors;
o The pipeline AHB Lite bus interface that allows high speed, low latency transfer,
supports transfer of 32-bit, 16-bit and 8-bit data;
o Exclusive accesses for multi-processor systems designs;
o Optional memory protection unit;
Interrupt handling (Nested Vectored Interrupt Controller- NVIC):
o Supports up to 240 interrupt inputs, a Non-Maskable Interrupt (NMI), and a
number of system interrupts;
o Dynamic change of priority level;
o Vectored interruption/exception;
o Low interrupt latency;
OS support and systems level features:
o SysTick, system tick timer that can be set up to generate regular timer interrupts
for OS timekeeping;
o Stacked pointers: Main Stack Pointer (MSP) and Process Stack Pointer (PSP);
o Separation of privileged and non-privileged operation modes;
Debug support;
Compatibility:

Cortex-M3 and M4 have great compatibility with wide family of other ARM
devices;
2. What are the features of M0 & M0+
o Both are based on ARMv6-M architecture;
o Ultralow power;
o Cheapest among the Cortex-M series;
o 32-bit system instructions;
o Three-stage pipeline for Cortex-M0, while Cortex-M0+ is two-stage pipeline;
o Interrupt handling, Thumb-2 (dynamic change of priority not supported);
o Debug support;
o NVIC;
o Upward Compatible with other M series;
3. What is MPU and describe its functions
MPU is the abbreviation for Memory Protection Unity, feature available for Cortex-M3 and M4. MPU is a
programmable device that monitors the bus traffic and needs to be configured by software. If MPU in
included, applications can divide memory into a number of regions and define the access for each of them.
4. What is the difference between MSP and PSP
Main Stack Pointer (MSP): used for OS kernel and interruptions, it is the default stack pointer. MSP can be
used all the time for simple applications without OS. Process Stack Pointer (PSP): used for application
tasks, Thread Mode.
5. What is polling method? Describe its advantages and disadvantages
Polling method is used for very simple applications of program flow, according to this method the
processor can wait until there is data ready for processing, process it and then wait again. The polling
works fine for simple applications, but when the application gets more complex, the polling loop becomes
hard to maintain, other disadvantage, it is very difficult to set up priority among the tasks.
6. Briefly explain:
o NVIC functions
i. Nested Vectored Interrupt Controller has as function to handle interruptions
and exceptions, prioritizations, and interrupt masking.
o Sleep mode
i. It is a power feature which a peripheral or section can be disabled when not
used. Later it can be waked up when processor requires.
o 3-stage pipeline
i. It refers the three instructions fetch, decode and execution.
o Halt
i. Halting is one of the features of debug support, which we are able to pause the
processors work and evaluate the register values, data and instructions.
o Breakpoint
i. Breakpoint is an intentional pause set up in a program, with debug purpose,
that can halt the processor.