MMIC Design Flow Using ADS

Complete and Fully Integrated
MMIC Design Flow Solution in ADS
Integrated design flow that

starts with system specs and
ends with successful delivery
of packaged MMIC in the
shortest amount of time
Jack Sifri
MMIC Design Flow Specialist
Agilent EEsof EDA
MMIC Design Flow using ADS 2012
Complete MMIC Design Flow Solution in ADS

Start
MMIC Specs
Front End Design
Back End - Physical Design & Manufacturing

2

Start
MMIC Specs

3
Foundry Engagement A Major Focus Area

Technology
MMIC
(GaAs / GaN)
RFIC
(SiGe/CMOS)
Foundry
Scope
Front-to-Back PDK creation

DRC rule deck
EM substrate (.slm )
MMIC tool bar
Training
Joint webinar and customer visit
Front-end PDK creation

Momentum module support
Increasing back-end support (for SiGe)
GoldenGate qualification
EM Qualification

4
Foundry Partner Page: www.agilent.com/find/eesof-foundries

5
Layout MMIC Tool Bar

Available in Agilent EEsof MMIC Foundry Design Kits
Layout editing commands are easily accessible and are configured to work seamlessly
with a foundry process.

6
Design Capture - Project Management

Allows you to organize your design files in folders and sub folders
An Example
Workspace View of an LTE MMIC
power amplifier (PA) design
Top level PA design has all the
matching networks placed in a
separate sub-folder
Statistical Analysis folder has 6

subfolders. Each subfolder contains
design and data display files.
MMIC PA Layout Cell has the Layout

view and schematic view and
symbol.

7
Design Capture Component Insertion

Drag and drop components into schematic and layout windows
Easily drag and
drop components
from the ADS main
window into the
schematic window
and layout window
Drag & drop
Drag & drop

designs into the
schematic page
Drag & drop

designs into the
layout page
Drag & drop

8
Optimization
Optimization Cockpit on a low-noise amp (LNA)
Pause optimization and edit algorithm or
goals and resume optimization
Store
optimization
solutions
and recall
them at any
time
Optimized
component
values and
history
Tune
The error
contribution
on each
goal
Spec lines

9
Custom Data Display and powerful post-processing

Provide designers with better insight to circuit behavior
Phase Noise at
VCOs Output
Phase Noise at
Dividers Output
AM Noise at Dividers Output

10

Front End Design
Start
MMIC Specs

11
Design For Manufacturing (DFM)

Statistical Design Tools
Help create robust designs that are insensitive to

temperature, bias, and process variation. The end result
is first-pass success and high yield.
Yield analysis doesnt pin point the source of a low yield problem
DOE and YSH are two unique tools in ADS. They work as an X-Ray
machine on designs. They pinpoint the source of the problem
YSH detect
Sensitive components
Sensitive Specs - YSH allows
for Specs trade-off study
without having to re-perform
yield analysis
DOE detects
Sensitive components
Sensitive matching networks
Interactions problems
Pinpoint the problem & fix it
Design of Experiments (DOE)
Yield Sensitivity Histograms

12
Design for Manufacturing (DFM)
This design used the

DFM design method
Example: K-Band Up-converter Macro Cell

Both Designs on
the same wafer
Ku-band
K-band
LO
X-band
Amp1
Mixer 2
X-band
Amp2
Ku-band
Standard Design
Wafer measured Results
Standard Design
Wide, 10 dB Variation Very sensitive
K-band
LO
Mixer 1
DOE Based Design
Wafer measured Results
DOE Based Design

Results
13
Specification:
Pout > 26 dBm @ Pin = 2 dBm
DFM Analysis on LTE MMIC PA

Initial Design
Final Design
4
Nominal Results - Pass
DFM Tools helped pin point the

problem area and fixed it
3
Yield Analysis on finished design
Lumped elements: +/- 5%
Line widths: +/- .5 um

14

Front End Design
Start
MMIC Specs

15
X-Parameters
Top-Down Design Specs
Bridge Between Our Customers
Bottom-up meas-based verification

Bottom-up Sim-based verification
ESL
Non-Linear
X-Parameters
Ideal Specs
Electronic System
Level Design (ESL)
System Integrators
Share IP Protected
X-Parameters file
New Designs
NVNA
X-pars
X-Parameters
Component for ADS
X-parameters
measurement
Existing Parts
IC Design Houses /
Component Vendor
16
Case I - System Integrator Use Circuit Level Designs

Results in lengthy simulation time and has no IP protection

17
Case II - System Integrator Uses X-parameter models

Results in faster simulation and trade off analysis with IP protected designs

18
Generating X-Parameters for the PA

One Tone 50 ohms
Overlaid Results
Model (Red) Vs. Circuit (Blue)

19

Front End Design
Start
MMIC Specs

20
Verification to LTE Wireless Standards in ADS

LTE: Uplink transmitter EVM measurement
Filter
Source
Coupler
MMIC
Features
True Circuit Level Co-Simulation

Fast Co-Simulation (AVM)
CE ties the circuit with Ptolemy
Able to optimize for ACPR, EVM
Accounts for the Frame structure
Identical to the real Wireless signal
True and Accurate verification

21
Verification to LTE Wireless Standards

Design House Results
Elliptic BPF
MMIC PA
IL=1 dB
Ripple=.9 dB
Coupler
IL=.4 dB

22
Wireless Verification Results

PA + Filter + Coupler + 50 ohm (Antenna)
Move Marker (m1) to -5 dBm

23

Front End Design
Start
MMIC Specs

24
Layout MMIC Tool Bar

Available in Agilent EEsof MMIC Foundry Design Kits
Layout editing commands are easily accessible and are configured to work seamlessly
with a foundry process.

25
MMIC PA 3D View

26
Layout Layers Validation in the 3D Viewer

Validate layer connectivity using Cut Plane cross-section
view in the 3D Viewer.

27
Layout Connectivity Checker

Interactively verify physical connections using Show Physical Interconnect
Highlights all objects that are
physically connected, throughout
the hierarchy.
Example:
This shunt Capacitor is not shorted.
It is fine.
Problem Fixed.
Both capacitors
are not shorted
This series Capacitor is shorted and
needs to be fixed. It is shown by
the metallization run.

28
Three Layout / Schematic Synchronization Modes

Provides optimum flexibility in the development of MMICs
Designers are not constrained by always having schematic and
layout automatically synchronized
Ability to switch back and forth between the three different modes
Allows to efficiently and
accurately fit many
elements designs into
small areas.
Three bidirectional modes of synchronization

between layout and schematic
The result is a smaller die

size and lowered overall
cost per chip.

29
Design Synchronization
Provides optimum flexibility in the development of MMICs
Designers can start in layout and auto generate the schematic
Can also start in schematic and auto-generate the layout
Designers can synch incremental changes (both directions)
Start in layout
Auto-generate the schematic
Or auto-generate the layout

from schematic
30
Layout Look-Alike Components

Placed on the schematic page
Layout look-alike components, used in the schematic page, act as polymorphic
models and allow designers to select and simulate from various models (including
schematic, layout, momentum MW and RF, 3D FEM, data files, X-parameters, circuitlevel subnetworks, and other).
Layout look-alike symbol is automatically
generated using the EM Setup window

31

Front End Design
Start
MMIC Specs

32
Momentum Solver 5 years of (R)evolution

Release
solve
time
load
time
load
time
Solve
Storage
2003A
dense (N2)
direct (N3)
dense (N2)
2005A
dense (N2)
iterative (NpN2)
dense (N2)
2008U1
dense (N2)
direct (NlogN)1.5 sparse (NlogN)
2011
solve
time
Load
sparse (NlogN) direct (NlogN)1.5 sparse(NlogN)
Example: PDN impedance

Freq sweep 0-3 GHz
Matrix size: 17.501
load
time
2003
2005
2008
2010
* Performance will vary dependent on complexity, frequency and other factors

33
New Momentum 2nd Generation Mesher
Preprocessor
Mesher (2nd generation )
Solver
Increased accuracy, robustness

and performance
OLD
Fast floating-point interval arithmetic
Improved mesh quality

Avoids slivers
Improved handling of small and wide
shapes
New algorithm for edge mesh and
overlap extraction
NEW
triangle
NEW
quadrilateral
Reduced mesh complexity

New quadrangles
rectangle

34
New Graphical Layer Definition

Graphical, unified entry of layer and stackup data
Defines layers and properties for Layout, Momentum, and FEM
Easy drag and drop operations
Easily select and modify properties
Simpler, faster, and less error prone

35
New Streamlined EM Setup

Making EM Work for Everyone
Previous EM Setup
ADS 2011/2012
Single dialog replaces 8 Easily navigate & review the setup options
Same setup for Momentum, Momentum RF, & FEM

Easy to try different solvers on the same design
Setup is automatically saved and can be reused for other EM simulations
36

Front End Design
Start
MMIC Specs

37
Design Rule Checker (DRC) in ADS
Catches errors early by running Desktop DRC from within ADS layout
Runs Calibre and Assura to check designs prior to submitting to the foundries
Run DRC
DRC Viewer
Provides exact X,Y

co-ordinates location
of the errors
Via to Via separation

must be > 100 um

38
Desktop Design Rule Check (DRC) Results
Provides X,Y coordinates
Auto Zoom and Auto Select Features
These two Vias are

separated by < 60 um

39

Front End Design
Start
MMIC Specs

40
Layout Versus Schematic (LVS)

ADS Desktop LVS identifies components missing from schematic or layout
Catch errors early by running ADS Desktop LVS from within ADS
schematic or layout
Run Calibre LVS to check designs prior to submitting to the foundries
Keep schematics and layouts in synch using Design

Synchronization
Access ADS Desktop

LVS from the tool bar

41
Desktop Layout Vs Schematic (LVS)

Results

42

Front End Design
Start
MMIC Specs

43
MMIC PA Reticle Design
Draw Reticle

44

Front End Design
Start
MMIC Specs

45
MMIC in Package / Board

Multi Technology design in ADS allows to easily assemble and
EM simulate a whole module (with different substrates) on a
laminate or PCB board.
See next section for more details.
MMIC
Module
Board

46
MMIC PA inside the DFN Package

47
Expanded Bondwire Support

New, fast analysis of bondwires in Momentum
Automatically modeled as part of Momentum
simulation
Calculates self and mutual inductance
Set parameters
FEM provides the most accurate analysis
Bondwires work for both Momentum and FEM
Create and edit in 2D
Easily create the bondwire in Layout

Full parametric control of bondwire profile
Jedec Bondwire Follows the JEDEC standard
parameters
Shape Bondwire More flexible control of the
bondwire profile
Render in 3D
Bondwires now have edit handles

48
QFN Designer
Predict Packaged Performance in Minutes
Configure QFN package
Accurately predict real performance
Quickly synthesize complex package,

combine with IC & PCB data
Performance w/ & w/o package
49
Amkor Package Design Kit

Predict Packaged Performance in Minutes
Configure QFN package
Accurately predict real performance
Quickly synthesize complex package,

combine with IC & PCB data
Performance w/ & w/o package
50

Front End Design
Start
MMIC Specs

51
Advanced 3DEM - FEM Simulator
Powerful finite-element 3D EM simulator
Seamlessly integrated in the Advanced

Design System (ADS)
Solves a wide array of applications with

impressive accuracy and speed.
Layout geometries in ADS automatically

used in FEM simulator for 3D EM
simulation.
FEM solutions can then be reviewed

and included in a larger ADS circuit.

52
3DEM - FEM Simulator

Flip chip modeled as a dielectric brick on solder balls in
preparation for EM simulation and visualization of EM results.

53
Agilent EEsof Integrated 3D EM Flow

EMPro link with ADS
Package Designers
MMIC Designers
EMPro Platform
ADS Platform
Parameterized
3D
Components
Layout
CAD Data
FDTD Simulator
FEM Simulator
Momentum Simulator
54
Packaged LTE MMIC PA

Fully Verified and Delivered to the System House
The Ultimate Verification Test
True MMIC Design Verification prior to

Manufacturing is done by Verifying and
Co-simulating the MMIC inside the
package and with bond wires using 3D
EM simulation

55
Package Analysis using 3D EM Simulator in ADS

E and H Field visualization of DFN Package with JDEC Bond wires
The E Field at 1.9 GHz
The H Field at 1.9 GHz

56
MMIC LNA in a QFN Package

Example of a more sensitive Ku band LNA to package and bondwire effects
You can Co-Simulate and Optimize the

response in the same way as in Momentum
57

Front End Design
Start
MMIC Specs

58
MMIC in Package / Board

Multi Technology design in ADS allows to easily assemble and
EM simulate a whole module (with different substrates) on a
laminate or PCB board.
MMIC
Module
Board

59
Module Design
MMIC amp in a package and mounted on a Laminate
Mounting LO Amplifier onto a QFN package, wire bonded, and
mounted on a laminate board ready for FEM simulation

60
Multi Technology Design in ADS2011

Example: Two ICs mounted on a QFN package
You can perform circuit simulations (schematic and Layout views) and EM simulation
Ku Band Mixer followed by 2GHz PA

61
Multi Technology Design in ADS2011

Example: Two ICs mounted on a QFN package + Laminate layers
Ku Band Mixer followed by 2GHz PA
One PDK

62
Conclusion
Agilent Provides Unique and Compelling Solutions
Widest selection of PDK support in the industry

Most accurate and fastest passive modeling (Model Composer and Advanced
Model Composer)
Advanced Parameter Extraction and Device Modeling with IC-CAP
Fastest and most accurate 3D planar EM solution available
Integrated FEM and FDTD 3D EM toolsets
Comprehensible Multi-technology design solution for IC/Module/Package/Board
Full support of Agilents breakthrough technology in X-Parameter non-linear
modeling
Flexible dataset post-processing and display capability
ADS desktop DRC
ADS desktop LVS
Proven Design For Manufacturing toolset
Patented circuit verification using complex waveforms
GaAs IC and Module co-design and optimization
Integrated instrument connectivity
Lowest cost full solution in the industry

63
MMIC Applications and Examples

Complete MMIC / Module ADS Desktop Flow Solution

64

MMIC Design Flow Using ADS

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Complete and Fully Integrated

MMIC Design Flow Solution in ADS

Integrated design flow that

Complete MMIC Design Flow Solution in ADS

Front End Design

Back End - Physical Design & Manufacturing