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Special Section on Analog Circuit Techniques and Related Topics

A 410 bit, 0.41 V Power Supply, Power Scalable Asynchronous

SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range
SAR Controller
Akira SHIKATAa) , Student Member, Ryota SEKIMOTO , Kentaro YOSHIOKA , Nonmembers,
Tadahiro KURODA , and Hiroki ISHIKURO , Members

This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register
(SAR) analog-to-digital converter (ADC). The proposed dierential flipflop in SAR logic and high eciency wide range delay element extend
the flexibility of speed and resolution tradeo. The ADC fabricated in
40 nm CMOS process covers 410 bit resolution and 0.41 V power supply
range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv.
with 160 kS/sec at 0.4 V single power supply voltage. At 10 bit mode and
1 V operation, up to 10 MS/s, the FoM is below 10 fJ/conv. while keeping
ENOB of 8.7 bit.
key words: analog-to-digital converter, successive approximation, asynchronous, dierential flip-flop



Power ecient, performance scalable circuit is essential for

future applications like a wireless sensor network and medical implantable devices. Such applications require various
kinds of specifications. For example, the required specification ranges from low frequency, high resolution signal such
as temperature monitoring to high frequency and low resolution signal such as image capturing. Furthermore, to use
for energy harvesting devices, ultra-low-voltage operation is
also important. This trend is also applied to ADCs. However, designing power ecient, performance scalable ADCs
is dicult because of those complex and large structure.
Among various types of ADC architectures, SARADC is suited for low-voltage and low-power operation because of its relatively simple structure and resource reuse
operation. Low power SAR-ADCs are intensively studied and several fJ/conv. ADCs have been reported [1][4].
Especially, [2][4] operate at enough low voltage and low
power for energy harvesting powered systems. As a result,
low cost wireless sensor network system becomes feasible.
However, these previous reported works were designed for
fixed specification and cannot be used for wide variety of
Recently, wide operational range in power supply voltage and resolution SAR-ADCs have been reported [5], [6].
However, the power of ADC in [5] is still far away from best
Manuscript received June 5, 2012.
Manuscript revised September 20, 2012.

The authors are with Keio University, Yokohama-shi, 2238522 Japan.

a) E-mail:
DOI: 10.1587/transfun.E96.A.443

Fig. 1 Eciency (FoM) of past published resolution reconfigurable SAR

ADCs against eective number of bits (ENOB).

Fig. 2 Sampling Speed (Fs) against ENOB of past published resolution

reconfigurable SAR ADCs and the target of this work. The data is taken
from their performance summary tables. Reference [5] operates up to
3 MHz with 5 bit mode and 2 MHz with 8 bit mode and 10 bit mode at 1 V.

ecient ADCs in both of normal supply voltage [1] and low

voltage [3], [4]. Reference [6] achieved high eciency but
the power supply voltage is fixed at 1.1 V (Fig. 1). Their
sampling rate limitations are from 2 (5 bit mode) to 3 MS/s
(810 bit mode) at 1 V [5] and 4 MS/s (for all resolution)
at 1.1 V [6], respectively (Fig. 2). This indicates these wide
range ADCs still have lots to improve speed and resolution
In the previous works [1][10], the power eciency
was improved mainly by developed internal DAC and comparator. As a result, relative power consumption of the SAR
logic compared with DAC and comparator increases [11].
To reduce the power consumption, asynchronous SAR logic

c 2013 The Institute of Electronics, Information and Communication Engineers




with dierential dynamic flip-flop was reported [11]. However, it has potential problems of data retention error and
data write error at ultra low voltage operation.
In this study, we proposed an asynchronous SAR controller which can be used in wide frequency range with wide
power supply voltage range. By using the proposed SAR
controller, power ecient and performance scalable ADC
was developed.
In the following sections, Sect. 2 describes the proposed resolution configurable architecture, Sect. 3 explains
SAR controller problems, Sect. 4 describes the circuit implementations, Sect. 5 shows the measurement results, and
finally, in Sect. 6, we conclude this paper.

Resolution Configurable Architecture

The proposed SAR ADC adopts the asynchronous top plate

sampling architecture for wide voltage range operation. The
top plate sampling substitutes CMOS switches in DAC
which are hard to drive at low voltage to simple logical gates
such as an inverter buer.
As shown in Fig. 3(a), the proposed resolution configurable SAR-ADC consists of a bootstrapped switch [12] as
the track and hold (T/H), an internal 9-bit reconfigurable
DAC and its foreground calibration unit (DAC CAL UNIT)
[3], [4], a clocked comparator [13], 410 bit resolution configurable SAR logic, and an asynchronous clock generation
circuit. For the simplicity, T/H circuit and DAC is expressed
in single-ended circuit in Fig. 3(a). In the actual implementation, T/H circuit and charge redistribution DAC are combined together and have dierential circuits. ADC resolution, the comparator capacitive load, and the delay time in

clock generator circuit are digitally controlled to further optimize the speed and resolution tradeo. Thanks to the digital calibration technique developed in our previous work
[3], [4], a small size unit capacitor of 0.5 fF can be used for
DACs, therefore power of the other components is also important. Thus DAC capacitance does not scale with resolution like Refs. [5], [6]. For the LSB comparison in 10-bit
mode, DACs operate asymmetrically. One of the complementary DAC outputs is set 1LSB larger value to the other
output to generate a half LSB (see Fig. 3(a)) for LSB decision at 10 bit mode.
Figure 3(b) shows the basic operation of the proposed
resolution configurable ADC. Where samp is input sampling clock and CLK is internally generated comparator
clock. When CLK is high, the comparator is activated to
compare the polarity of the input signals and when CLK is
low, the comparator is reset and it waits DAC settling by
the next bit decision. After the internal clock signal goes
high the number of times equal to the number of operating
resolution, finish signal (FIN) goes high to keep CLK
low until next conversion phase. The digital selector (MUX)
chooses one of d [4:10] as FIN (Fig. 3(b)). In the conventional approach, the internal clock period does not depend on the operating resolution. However, as the operating
resolution becomes low, the required DAC settling time is
relaxed. In our ADC, the internal clock period can be reduced by controlling a delay to further increase the speed at
low resolution mode.
Tunable capacitors are connected at the output nodes
of comparator to control the oset and the capacitive load.
The oset control is used for DAC calibration [3], [4]. For
the additional power saving, the capacitive load scales according to the operating resolution of ADC [6].

Consideration of SAR Logic

Asynchronous SAR is suited to both of fast and slow operations. Because it eliminates fast external clock and signal
degradation by leakage. However internal looped circuit becomes unstable easily and it requires carefully estimation
during circuit designs.
In the asynchronous operation, both of conventional
static and dynamic logic gates can be employed. The performance characteristic of conventional static logic gates,
dynamic logic gates, and our work is summarized in Table 1. The conventional static logic gates are stable and easy
to design but consume much power because of its relative
complex structure.
On the other hand, dynamic logic gates are simple and
can be used to reduce power consumption and increase the
Table 1

Fig. 3 (a) Block diagram of the proposed SAR-ADC single-ended

example, (b) the operation of the N-bit mode SAR-ADC.

Comparison of SAR controller.



operating speed. Especially, asynchronous SAR ADC suits

with dynamic logic gates because each successive approximation (SA) step automatically proceeds internally and the
conversion finishes in certain time which is independent of
external sampling period. This avoids the problem of the fail
operation of dynamic logic gates by charge leakage at low
frequency. Additionally recent progresses of designing high
ecient analog building blocks increase the power ratio of
the digital block in SAR ADC.
However, dynamic circuits are weak to noise, leakage,
and timing error and it is dicult to operate properly at ultra
low voltage condition because the low supply voltage enhances those issues. Then we targeted to design circuits as
low power, fast speed as dynamic circuits and as stable as
conventional static circuits.
3.1 Conventional Synchronous Static SAR Logic

3.2 Conventional Asynchronous Dynamic SAR Logic

As shown in Fig. 5, the dynamic logic SAR controller which
combines the counting part with SAR part was reported [11]
to further reduce circuit size and power consumption. However, the timing control for asynchronous operation in this
circuit is very critical and it cannot be used in wide frequency and power supply range.
The SAR logic unit in Fig. 5 consists of dierential dynamic flip-flop [11] (Fig. 6(a)) and phase generator
(Fig. 6(b)) to trigger the next SAR logic unit. The timing
chart of the SAR operation is shown in Fig. 7.
From the sampling phase to the time previous stage
((k 1)-th stage) restoring the comparator output data, [k]
are low and the outputs of the flip-flop (a[k]/a [k]) are pulled
up. Therefore, [k + 1] is high and [k + 1] is low. This
state corresponds to Init phase in Fig. 7. Then, preceding

Figure 4 shows the conventional static logic gate based SAR

controller. The upper D-FF line consists of a ring counter
which controls the phase of the SAR operation. The lower
D-FF line latches the comparator signal at each phase to determine the internal DAC setting code and the ADC final
output code.
In this kind of circuit, the SAR logic uses two D-FFs
for each conversion bit. D-FF gates are relatively complex
and it increases the power and area of SAR logic.

Fig. 5

Fig. 4

Conventional synchronous SAR logic with static D-FFs.

Conventional asynchronous SAR logic overview.

Fig. 6 (a) Conventional dynamic dierential flip-flop in SAR logic unit,

and (b) internal phase generator in SAR logic unit.

Fig. 7 Conventional asynchronous controller operation, (a) the write margin is too short, (b) the write
margin is in best condition, (c) the write margin is too long. The arrow indicates the each trigger timing
in asynchronous operation.



(k 1)-th SAR unit asserts the [k] and k-th SAR unit becomes data starving (DS) state. At the rising edge of internal clock, the comparator starts the voltage comparison, and
after a while (tcomp ), the outputs of the comparator (C p /Cn )
are decided. Depending on the C p and Cn , one of the outputs (a[k] or a [k]) of the k-th flip-flop goes low (write state
W in Fig. 7) and the [k + 1] changes from high to low,
which turn o M3/4 and holds the flip-flop data. Just after
that, [k + 1] changes from low to high and brings the next
SAR logic unit into DS state.
In parallel with the above SAR logic unit operations,
the clock generator controls the comparator state. That is,
after the comparator output is determined, the clock generator starts to pull down the clock signal to reset the comparator. Because the comparator reset time is much larger
than the SAR writing time, before the C p and Cn go low,
SAR logic unit stores comparator output. The clock generator waits some time for the DAC settling and then pulls up
the clock signal to enter the next SA step.
There are two potential problems in this circuit. The
first one is the data retention of the dynamic flip-flop. If the
power supply voltage becomes low, the transistor operates in
sub-threshold region and imbalance of the leakage current
of M3/4 brings data retention error. The second problem
is the critical timing control required for proper operation.
As shown in Fig. 7(a), if the clock margin time (twait1 ) is
shorter than twrite , the flip-flop in the k-th SAR unit does
not become Hold state because the input signal (C p , Cn )
goes low before data being correctly stored. On the other
hand, if twait1 takes longer than twrite , the flip-flop in the kth SAR unit captures data (Fig. 7(b)). However if twait1 is
much longer than twrite , the data go through to the next bit
for wrong data storing (Fig. 7(c)). Since the twait1 and twrite is
determined independently, critical timing control is required
to guarantee the relation between these timing.
Moreover, in the case of low supply voltage, the comparator takes much longer time to reset. This remains the
comparator outputs (C p , Cn ) after CLK goes low to increase the eective wait time and makes wrong data storing.
These features are not suited for scalable ADC because wide
range of frequency and power supply is required.

Circuit Implementation

4.1 Proposed Fast and Stable Combined SAR Logic

(Asynchronous and Static)
To solve these problems, we propose low-power and stable asynchronous SAR controller (Fig. 8) which operates in
wide range in frequency and power supply voltage without
severe timing estimation.
As shown in Fig. 8, the OR gate monitors whether the
comparator is in comparison mode or reset mode and controls each SAR logic unit to prevent incorrect data write as
shown in Fig. 7(c)). Furthermore, the dierential flip-flop
is modified as shown in Fig. 9(a). In the proposed circuit,
M3/4 and M9/10 form cross coupled inverters, and M5/6

Fig. 8

Proposed asynchronous SAR logic overview.

Fig. 9 (a) proposed circuit schematic of SAR Logic Unit, (b) internal
phase generator of SAR Logic Unit.

Fig. 10

Proposed SAR logic operation.

are added to bypass the input transistors M1/2 in the hold

mode. This topology enables the static operation in hold
mode, which solves the problem of the data retention even
at ultra-low-voltage operation. To control the gates of M5/6,
d [k + 1] is generated by the circuit shown in Fig. 9(b). Only
after the comparator is reset and ready signal becomes
low, the d [k + 1] goes high and the next flip-flop enters into
standby (SB) mode before going data starving (DS) mode
(Fig. 10). This prevents incorrect data write into (k+1)-th
SAR logic unit. The detail operation of the proposed SAR
controller is explained in the following.
During the external sampling signal (samp) is high,
the ADC is in the sampling mode. The output of the flipflop in 0-th SAR logic unit (a[0]/a[0]) are pre-charged to
VDD and phase signal [1] and d [1] are low. This corresponds to Init state of SAR logic unit. Then [1] negates
the flip-flop in the 1-st SAR logic unit as the same way as the
0-th stage flip-flop. This flip-flop initialization propagates to



Fig. 11 Simulated shmoo plot of write wait timing margin. Conventional

asynchronous controller only work red colored area (within dashed lines),
the proposed asynchronous controller operates within blue colored area
(within solid lines).

the flip-flop in the final SAR logic unit and the FIN signal becomes low to ready for data conversion cycle. At the
same time, MSB bit (D[0]) is set to 0 and all the other bits
(D[1:8]) are set to 1 (see Fig. 5), which is the initial value
of the SAR operation [11].
When samp goes low, the ADC begins data conversion. At first, [0] and d [0] goes high, and the comparator
output (C p /Cn ) is written into the 0-th flip-flop. After the
flip-flop output (a[0]/a[0]) are determined in the write operation (twrite ), the [1] becomes high and brings the next
SAR logic unit into SB mode. At the same time, D[0] and
D[1] change and the DAC setting code is updated for next
SA step automatically. After the clock generator resets the
comparator, C p and Cn become low to pull down the ready
signal. At this moment, d [1] goes high to turn on the M5/6
in 0-th flip-flop and hold the data. At the same time, d [1]
also triggers the next flip-flop into DS mode by turning on
the M7/M8. Since the data sampling of the flip-flop starts
only after the output of comparator being reset, the incorrect
data write never occurs and guarantees the stable operation
at wide frequency and power supply voltage range (Fig. 10).
The same operation proceeds to the next SAR logic unit until the final unit are determined.
Figure 11 shows the shmoo plot of twait1 and VDD. In
the previous reported SAR controller, critical timing control
is required and it strongly depends on the supply voltage.
On the other hand, in our SAR controller, the timing margin
is greatly relaxed.
4.2 Clock Generator and Controllable Delay Element
The circuit schematic of asynchronous clock generator inspired by [11] is shown in Fig. 12. During the sampling signal (samp) is high, the output of delay element (DE) and
FIN are low. Therefore, the internal asynchronous clock
(CLK) stays low. When samp becomes low, CLK immediately goes high to start data conversion cycle. When the
first comparison finishes, one of the comparator output (C p
or Cn ) goes high and pull down the output of completion detector (CD). This falling action in the CD immediately pulls
down the CLK to start reset operation. On the other hand,

Fig. 12

Clock generator architecture.

Fig. 13 Delay element in the asynchronous clock generator, (a)

schematic of delay element (b) node waveform of the delay element. (c)
capacitive voltage divider (CVD).

this falling action is delayed in DE and keeps CD output low

by tloop1 . After it takes tloop1 , NOR gate pulls up and CD gets
ready for next comparison. Then it goes to 2nd delay loop
for the remaining DAC settling. After the delay (tloop2 ) by
DE, the output of DE is pulled up and CLK goes high then
SAR controller enters next SA step.
Here, tloop1 and tloop2 determines the asynchronous period. The asynchronous operation is automatically triggered
by the combination of the proposed SAR logic and the clock
generator as long as the delay tloop1 is longer than comparator reset time. Generally speaking, data latching time is
enough short (see Fig. 11) than the comparator reset time
because comparator has large load capacitance.
Delay element is one of the most important circuits in
asynchronous SAR ADCs. For the fast operation, the delay
in clock generator should be minimized. However, too small
delay leads to incomplete settling in DACs and degrades the
accuracy especially in high resolution mode. To obtain the
optimum delay, the delay time can be controlled during the
SAR operation [2], [14]. However, the wide tuning range of
delay element causes large power and area. Therefore we
developed delay element with small size, low power, and
wide delay control range.
Figure 13(a) shows the circuit schematic of the pro-



Fig. 14 Delay element Comparison (a) Capacitor load control, (b) proposed CVD method, (c) Delay element power eciency against the required delay amount.

posed delay element. As shown in Fig. 13(c), it has internal

two 5-bit controlled capacitive voltage dividers (CVD) to
control the gate voltage amplitude in node B and C. Those
voltages can be expressed by using capacitive coupling as
VB =



By controlling the voltage dividing ratio of CVDP , Vgs

of MP can be changed and rise time of delay element can be
changed. On the other hand, by changing the dividing ratio
of CVDn , Vgs of MN can be changed and fall time of delay
element can be changed.
Especially at low voltage operation (near sub-threshold
region), the drivability of the MOSFETs strongly depends
on the gate voltage. Therefore, by controlling the gate voltage by using CVD, the wide delay range can be eciently
obtained. The power of the delay element is almost constant
of 3 nW/MHz at 0.4 V supply voltage with all the delay time
from 12 nsec to 150 nsec in the circuit simulation. The die
area of whole clock generator (including delay element) occupies only 12 m 8 m.
Figure 14 compares the required power to realize the
delay element by using simple capacitive load and our capacitive voltage divider. If simple variable capacitive load is
used, the power consumption and area increase proportional
to the required delay amount. On the other hand, the power
consumption of our circuit is only 3 nW/MHz and does not
depend on the required delay. Another way to realize the
wide delay range is to use current starved inverter. However
the current starved inverter requires current source circuit
which is dicult to design at ultra low voltage with small
circuit area. The total capacitance of the delay element is
only 22 fF.
4.3 DAC Calibration Circuit and Method
The principle of the DAC calibration is based on capacitance
to voltage transfer [15]. Figure 15(a) shows the circuit implementation of the DAC calibration unit (DCU). The DCU

Fig. 15 (a) Circuit implementation of the DAC calibration unit (DAC

CAL in Fig. 3(a) and its operation, (b) DAC calibration operation.

is placed between SAR logic and DAC (Fig. 3(a)) to provide

DAC the calibration setting code during calibration mode
The DCU provides initial state signal (INI[0:3] in
Fig. 15(b)) and swapped state signal (SWA[0:3]). During sampling phase, DAC samples the comparator common
mode level with the digital input of INI[0:3] for example,
INI[0:3]=[0111] for MSB calibration. When samp goes
low (conversion phase), the sampling switch turns o and
after that the digital code is swapped to SWA[0:3]=[1000].
Those two digital codes are set to the same amount of capacitance ideally. Then, the DAC output should be the same. If
the DAC output becomes positive, the total capacitance of
the capacitors connected to SWA[0:3] is larger than that of
connected to INI[0:3].
The internal oset calibrated comparator detects the
voltage polarity to decide which side capacitor has larger capacitance. Then connections of sub capacitors are changed
to balance the capacitance between the capacitors connected
to INI[0:3] and SWA[0:3] through binary search algorithm.
After the capacitance becomes balanced, it moves to next
bit calibration. Then INI[0:3] is set to [0011] and SWA[0:3]
is set to [0100]. The calibration procedure is done by LSB
([0001] = [0010]). Because SAR logic outputs do not deal
with the DAC during calibration (see Fig. 15(a)), the comparator outputs can be stored to SAR logic. The stored data
read out to o chip as the same way to read out ADC output and procedure calibration by o chip in this work. After
calibration, CAL is set to 0 and the DCU works just buers.
4.4 SAR ADC Building Block Power Budget
Figure 16 shows the simulated power budget of the conventional SAR ADC (Fig. 16(a)) and the proposed SAR
ADC (Fig. 16(b)) at 10 bit mode and 0.4 V supply voltage. Only SAR logic and delay element in clock generator are the dierent between the two. The conventional
static SAR ADC (Fig. 16(a)) employed 128 fF capacitive
load delay element to achieve almost equal delay amount
(see Fig. 14). In this condition, SAR logic in [11] did not



Fig. 17

Chip photograph.

Fig. 16 (a) power budget of the conventional SAR ADC which uses
static SAR logic and capacitive load delay element, (b) power budget of
the proposed ADC which uses the proposed SAR logic and delay element.
The power is normalized with the conventional SAR ADC.

work because of too long write margin time problem (see

Fig. 7(c)). Calibration in Fig. 16 means power consumption of DCU (Fig. 3(a) and Fig. 15(a)). Therefore DAC related block consumes relative large in this ADC.
The proposed SAR logic and delay element requires
only 1/3 power and totally 25% power improvement was

Fig. 18 Measured (a) DNL and (b) INL. With sampling rate of
160 kS/sec and input frequency is around 100 kHz, measured with 16 times
averaged 4096-point input (65536 data) at 0.4 V and 10 bit mode.

Measurement Results

Figure 17 shows the microphotograph of the developed

ADC core. It has been designed and fabricated in a 40 nm
standard CMOS technology and the ADC active area occupies only 100 m 130 m. Only a single power supply is
required for the circuit operation. The covered power supply
ranges from 0.4 to 1 V.
Dierential nonlinearity (DNL) and integral nonlinearity (INL) were evaluated based on code-density measurement. With a 100 kHz sinusoidal signal at 160 kS/sec
conversion rate, the measured peak DNL and INL were
+1.67/1 LSB and to +1.43/1.79 LSB, respectively at
10 bit mode by using DAC calibration technique proposed
in [3], [4] (Fig. 18). The unit capacitance of 0.5 fF was employed and it divided to 0.4 fF main capacitor and 0.1 fF sub
capacitor. The maximum and minimum DNL/INL characteristic against the operational resolution is shown in Fig. 19.
The proposed ADC employed asymmetry DAC operation
at 10 bit mode to halve the number of unit capacitors compared to ordinary 10 bit binary weighted capacitor DAC.
This makes the calibration step size twice eectively and
makes it dicult to calibrate at 10 bit mode operation. This
directly aects the SNDR of the proposed ADC at higher bit
Figure 20 shows the measured FFT plot with a 100 kHz
sinusoidal input, and sampling rate of 160 kHz. Because
of the instrument used in this experiment, the minimum
input signal frequency is 100 kHz. Therefore higher than
Nyquist frequency (80 kHz) signal is put into the ADC.
SNDR and spurious free dynamic range (SFDR) of the ADC
are 49.8 dB and 57.5 dB, respectively.
Figure 21 shows the relation between the SNDR and

Fig. 19 Maximum and minimum DNL/INL against operation resolution.

With sampling rate of 160 kS/sec and input frequency is around 100 kHz,
measured with 16 times averaged 4096-point input (65536 data) at 0.4 V.

Fig. 20 Measured 4 times averaged 4096-point FFT plot (16384 data)

with sampling rate of 160 kS/s within under sampling rate input of around
100 kHz (under sampling) at 0.4 V supply voltage.

Fig. 21 ENOB against delay code at supply voltage of 0.4 V. The larger
delay code indicates larger delay amount in the clock generator.



Fig. 22 SNDR against Sampling Frequency with 100 kHz input (below
sampling frequency of 200 kHz) and Nyquist frequency (sampling frequency of above 200 kHz).

Fig. 25

FoM against sampling frequency at various power supply

Table 2

Performance summary.

Fig. 23 FoM against sampling frequency with 100 kHz input (below
sampling frequency of 200 kHz) and Nyquist frequency (sampling frequency of above 200 kHz).

Fig. 24

SNDR against sampling frequency at various power supply

delay setting code in the clock generator. The delay increases as the delay setting code is increased. In high resolution mode, the SNDR degrades as the delay decreases
because the DAC settling error becomes fatal compared to
the low resolution mode.
Figure 22 shows the measured SNDR against sampling
frequency at various resolution modes. The delay code is
set at optimum value which keeps good SNDR at each resolution mode. By optimizing delay time against resolution,
the sampling frequency can be increased as the operating
resolution is lowered.
Figure 23 shows the ADC figure of merit (FoM) against
sampling frequency at dierent resolution mode. At each
resolution mode, as the sampling frequency exceeds the
speed limitation, the SNDR and FoM begin to degrade. The
best FoM of 3.4 fJ/conv. was achieved at 10 bit mode with
sampling frequency of 160 kS/s.
From Figs. 18 to 23, all the measurements were carried
out at power supply voltage of 0.4 V.

The performance of the fabricated ADC was also measured at dierent power supply voltage.
The relation between the SNDR and maximum sampling frequency (Fs max) at each resolution mode is shown
in Fig. 24 with the power supply voltage of 0.4, 0.5, 0.7
and 1.0 V. Fs max is defined as the maximum sampling frequency which all the conversion cycle is completely finished
at each resolution mode. For example, at VDD of 0.4 V, it
corresponds to the envelope of all the curves in Fig. 22. If
the power supply is increased to 1.0 V, ENOB of 8.7 bit is




Fig. 26 Performance (Fs) comparison with the previous reported

scalable ADCs.

Fig. 27 Performance (FoM) comparison with the previous reported

scalable ADCs.

obtained at 10 MHz and the ADC operates at 100 MHz with

4 bit resolution mode.
Figure 25 shows the FoM against maximum sampling
frequency at VDD of 0.4 V, 0.5 V, 0.7 V, and 1.0 V. Even at
1.0 V, the ADC achieves FoM lower than 10 fJ/conv.step at
10 MHz and ENOB of 8.7 bit.
Table 2 summarized the proposed ADC performance.
Figures 26 and 27 show the performance comparison with
the previous reported wide operation range SAR ADCs [5],
[6]. In our ADC, if high speed operation is important, higher
supply voltage can be used. On the other hand, if power
eciency is emphasized, ultra-low voltage operation can be


By using modified SAR logic and wide range delay element,

the proposed ADC reduced total power by 25% at 0.4 V and
10 bit mode operation compared to the conventional SAR
logic using static logic gates and the delay element using
capacitive load.
The prototype ADC achieved high eciency of below
100 fJ/conv. in 410 bit mode at 0.40.7 V. The best eciency is achieved at 0.4 V supply and 10 bit mode operation with sampling rate of 160 kS/sec. The achieved SNDR
is 49.8 dB and the power consumption is 0.14 W resulting
FoM of 3.4-fJ/conversion step. And in the 4-bit mode and
1 V supply, the ADC operates up to 100 MHz.
This work was carried out as a part of the Extremely Low
Power (ELP) project supported by METI and NEDO.

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Akira Shikata
received B.S. and M.S.
degrees in electronics and electrical engineering from Keio University, Yokohama, Japan, in
2008 and 2010, respectively, where he is currently working toward the Ph.D. degree. His
current research interests lie in low-power and
low-voltage data converters.

Ryota Sekimoto
received B.S. degrees in
electronics and electrical engineering from Keio
University, Yokohama, Japan, in 2011, where
he is currently working toward the M.S. degree.
Since 2010, he has been working on ultra low
power ADC for wireless sensor network.

Kentaro Yoshioka
received B.S. degrees in
electronics and electrical engineering from Keio
University, Yokohama, Japan, in 2012, where
he is currently working toward the M.S. degree.
His current research interests lie in low voltage
and high speed data converters.

Tadahiro Kuroda
received the Ph.D. degree in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1999. In 1982,
he joined Toshiba Corporation, where he designed CMOS SRAMs, gate arrays and standard cells. From 1988 to 1990, he was a Visiting Scholar with the University of California,
Berkeley, where he conducted research in the
field of VLSI CAD. In 1990, he was back to
Toshiba, and engaged in the research and development of BiCMOS ASICs, ECL gate arrays,
high-speed CMOS LSIs for telecommunications, and low-power CMOS
LSIs for multimedia and mobile applications. He invented a Variable
Threshold-voltage CMOS (VTCMOS) technology to control VTH through
substrate bias, and applied it to a DCT core processor and a gate-array
in 1995. He also developed a Variable Supply-voltage scheme using an
embedded DC-DC converter, and employed it to a microprocessor core
and an MPEG-4 chip for the first time in the world in 1997. In 2000,
he moved to Keio University, Yokohama, Japan, where he has been a
professor since 2002. He was a Visiting Professor at Hiroshima University, Japan, and the University of California, Berkeley. His research interests include low-power, high-speed CMOS design for wireless and wireline communications, human computer interactions, and ubiquitous electronics. He has published more than 200 technical publications, including 60 invited papers, and 21 books/chapters, and has filed more than
100 patents. Dr. Kuroda served as the General Chairman for the Symposium on VLSI Circuits, the Vice Chairman for ASP-DAC, sub-committee
chairs for A-SSCC, ICCAD, and SSDM, and program committee members for ISSCC, the Symposium on VLSI Circuits, CICC, DAC, ASP-DAC,
ISLPED, SSDM, ISQED, and other international conferences. He is a recipient of the 2005 P&I Patent of the Year Award, the 2006 LSI IP Design
Award, the 2007 ASP-DAC Best Design Award, the 2009 IEICE Achievement Award, and the 2011 IEICE Society Award. He is an IEEE Fellow, an
elected AdCom member for the IEEE Solid-State Circuits Society and an
IEEE SSCS Distinguished Lecturer.

Hiroki Ishikuro
received the B.S., M.S.
and Ph.D. degrees in electrical engineering from
the University of Tokyo, Tokyo, Japan, in 1994,
1996, and 1999, respectively. In 1999, he
joined the System LSI Research and Development Center, Toshiba Corp., Kawasaki, Japan,
where he was involved in the development of
CMOS RF and mixed-signal circuits for wireless interface chips. In 2006, he joined the Department of Electrical Engineering at Keio University as an assistant professor and started a research on high-speed inductive-coupling links for 3-D chip integration and
non-contact connector. He is currently an associate professor of Keio University, and focuses on the mixed-signal circuit and system designs for extremely low-power interfaces. He is a member of the Technical Program
Committee for Symposium on VLSI Circuits.