2 FEBRUARY 2013
443
PAPER
SUMMARY
This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register
(SAR) analog-to-digital converter (ADC). The proposed dierential flipflop in SAR logic and high eciency wide range delay element extend
the flexibility of speed and resolution tradeo. The ADC fabricated in
40 nm CMOS process covers 410 bit resolution and 0.41 V power supply
range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv.
with 160 kS/sec at 0.4 V single power supply voltage. At 10 bit mode and
1 V operation, up to 10 MS/s, the FoM is below 10 fJ/conv. while keeping
ENOB of 8.7 bit.
key words: analog-to-digital converter, successive approximation, asynchronous, dierential flip-flop
1.
Introduction
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with dierential dynamic flip-flop was reported [11]. However, it has potential problems of data retention error and
data write error at ultra low voltage operation.
In this study, we proposed an asynchronous SAR controller which can be used in wide frequency range with wide
power supply voltage range. By using the proposed SAR
controller, power ecient and performance scalable ADC
was developed.
In the following sections, Sect. 2 describes the proposed resolution configurable architecture, Sect. 3 explains
SAR controller problems, Sect. 4 describes the circuit implementations, Sect. 5 shows the measurement results, and
finally, in Sect. 6, we conclude this paper.
2.
clock generator circuit are digitally controlled to further optimize the speed and resolution tradeo. Thanks to the digital calibration technique developed in our previous work
[3], [4], a small size unit capacitor of 0.5 fF can be used for
DACs, therefore power of the other components is also important. Thus DAC capacitance does not scale with resolution like Refs. [5], [6]. For the LSB comparison in 10-bit
mode, DACs operate asymmetrically. One of the complementary DAC outputs is set 1LSB larger value to the other
output to generate a half LSB (see Fig. 3(a)) for LSB decision at 10 bit mode.
Figure 3(b) shows the basic operation of the proposed
resolution configurable ADC. Where samp is input sampling clock and CLK is internally generated comparator
clock. When CLK is high, the comparator is activated to
compare the polarity of the input signals and when CLK is
low, the comparator is reset and it waits DAC settling by
the next bit decision. After the internal clock signal goes
high the number of times equal to the number of operating
resolution, finish signal (FIN) goes high to keep CLK
low until next conversion phase. The digital selector (MUX)
chooses one of d [4:10] as FIN (Fig. 3(b)). In the conventional approach, the internal clock period does not depend on the operating resolution. However, as the operating
resolution becomes low, the required DAC settling time is
relaxed. In our ADC, the internal clock period can be reduced by controlling a delay to further increase the speed at
low resolution mode.
Tunable capacitors are connected at the output nodes
of comparator to control the oset and the capacitive load.
The oset control is used for DAC calibration [3], [4]. For
the additional power saving, the capacitive load scales according to the operating resolution of ADC [6].
3.
Asynchronous SAR is suited to both of fast and slow operations. Because it eliminates fast external clock and signal
degradation by leakage. However internal looped circuit becomes unstable easily and it requires carefully estimation
during circuit designs.
In the asynchronous operation, both of conventional
static and dynamic logic gates can be employed. The performance characteristic of conventional static logic gates,
dynamic logic gates, and our work is summarized in Table 1. The conventional static logic gates are stable and easy
to design but consume much power because of its relative
complex structure.
On the other hand, dynamic logic gates are simple and
can be used to reduce power consumption and increase the
Table 1
SHIKATA et al.: A 410 BIT, 0.41 V POWER SUPPLY, POWER SCALABLE ASYNCHRONOUS SAR-ADC
445
Fig. 5
Fig. 4
Fig. 7 Conventional asynchronous controller operation, (a) the write margin is too short, (b) the write
margin is in best condition, (c) the write margin is too long. The arrow indicates the each trigger timing
in asynchronous operation.
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(k 1)-th SAR unit asserts the [k] and k-th SAR unit becomes data starving (DS) state. At the rising edge of internal clock, the comparator starts the voltage comparison, and
after a while (tcomp ), the outputs of the comparator (C p /Cn )
are decided. Depending on the C p and Cn , one of the outputs (a[k] or a [k]) of the k-th flip-flop goes low (write state
W in Fig. 7) and the [k + 1] changes from high to low,
which turn o M3/4 and holds the flip-flop data. Just after
that, [k + 1] changes from low to high and brings the next
SAR logic unit into DS state.
In parallel with the above SAR logic unit operations,
the clock generator controls the comparator state. That is,
after the comparator output is determined, the clock generator starts to pull down the clock signal to reset the comparator. Because the comparator reset time is much larger
than the SAR writing time, before the C p and Cn go low,
SAR logic unit stores comparator output. The clock generator waits some time for the DAC settling and then pulls up
the clock signal to enter the next SA step.
There are two potential problems in this circuit. The
first one is the data retention of the dynamic flip-flop. If the
power supply voltage becomes low, the transistor operates in
sub-threshold region and imbalance of the leakage current
of M3/4 brings data retention error. The second problem
is the critical timing control required for proper operation.
As shown in Fig. 7(a), if the clock margin time (twait1 ) is
shorter than twrite , the flip-flop in the k-th SAR unit does
not become Hold state because the input signal (C p , Cn )
goes low before data being correctly stored. On the other
hand, if twait1 takes longer than twrite , the flip-flop in the kth SAR unit captures data (Fig. 7(b)). However if twait1 is
much longer than twrite , the data go through to the next bit
for wrong data storing (Fig. 7(c)). Since the twait1 and twrite is
determined independently, critical timing control is required
to guarantee the relation between these timing.
Moreover, in the case of low supply voltage, the comparator takes much longer time to reset. This remains the
comparator outputs (C p , Cn ) after CLK goes low to increase the eective wait time and makes wrong data storing.
These features are not suited for scalable ADC because wide
range of frequency and power supply is required.
4.
Circuit Implementation
Fig. 8
Fig. 9 (a) proposed circuit schematic of SAR Logic Unit, (b) internal
phase generator of SAR Logic Unit.
Fig. 10
SHIKATA et al.: A 410 BIT, 0.41 V POWER SUPPLY, POWER SCALABLE ASYNCHRONOUS SAR-ADC
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the flip-flop in the final SAR logic unit and the FIN signal becomes low to ready for data conversion cycle. At the
same time, MSB bit (D[0]) is set to 0 and all the other bits
(D[1:8]) are set to 1 (see Fig. 5), which is the initial value
of the SAR operation [11].
When samp goes low, the ADC begins data conversion. At first, [0] and d [0] goes high, and the comparator
output (C p /Cn ) is written into the 0-th flip-flop. After the
flip-flop output (a[0]/a[0]) are determined in the write operation (twrite ), the [1] becomes high and brings the next
SAR logic unit into SB mode. At the same time, D[0] and
D[1] change and the DAC setting code is updated for next
SA step automatically. After the clock generator resets the
comparator, C p and Cn become low to pull down the ready
signal. At this moment, d [1] goes high to turn on the M5/6
in 0-th flip-flop and hold the data. At the same time, d [1]
also triggers the next flip-flop into DS mode by turning on
the M7/M8. Since the data sampling of the flip-flop starts
only after the output of comparator being reset, the incorrect
data write never occurs and guarantees the stable operation
at wide frequency and power supply voltage range (Fig. 10).
The same operation proceeds to the next SAR logic unit until the final unit are determined.
Figure 11 shows the shmoo plot of twait1 and VDD. In
the previous reported SAR controller, critical timing control
is required and it strongly depends on the supply voltage.
On the other hand, in our SAR controller, the timing margin
is greatly relaxed.
4.2 Clock Generator and Controllable Delay Element
The circuit schematic of asynchronous clock generator inspired by [11] is shown in Fig. 12. During the sampling signal (samp) is high, the output of delay element (DE) and
FIN are low. Therefore, the internal asynchronous clock
(CLK) stays low. When samp becomes low, CLK immediately goes high to start data conversion cycle. When the
first comparison finishes, one of the comparator output (C p
or Cn ) goes high and pull down the output of completion detector (CD). This falling action in the CD immediately pulls
down the CLK to start reset operation. On the other hand,
Fig. 12
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Fig. 14 Delay element Comparison (a) Capacitor load control, (b) proposed CVD method, (c) Delay element power eciency against the required delay amount.
CA
VDD
CA + CB
(1)
SHIKATA et al.: A 410 BIT, 0.41 V POWER SUPPLY, POWER SCALABLE ASYNCHRONOUS SAR-ADC
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Fig. 17
Chip photograph.
Fig. 16 (a) power budget of the conventional SAR ADC which uses
static SAR logic and capacitive load delay element, (b) power budget of
the proposed ADC which uses the proposed SAR logic and delay element.
The power is normalized with the conventional SAR ADC.
Fig. 18 Measured (a) DNL and (b) INL. With sampling rate of
160 kS/sec and input frequency is around 100 kHz, measured with 16 times
averaged 4096-point input (65536 data) at 0.4 V and 10 bit mode.
Measurement Results
Fig. 21 ENOB against delay code at supply voltage of 0.4 V. The larger
delay code indicates larger delay amount in the clock generator.
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Fig. 22 SNDR against Sampling Frequency with 100 kHz input (below
sampling frequency of 200 kHz) and Nyquist frequency (sampling frequency of above 200 kHz).
Fig. 25
voltage.
Table 2
Performance summary.
Fig. 23 FoM against sampling frequency with 100 kHz input (below
sampling frequency of 200 kHz) and Nyquist frequency (sampling frequency of above 200 kHz).
Fig. 24
voltage.
delay setting code in the clock generator. The delay increases as the delay setting code is increased. In high resolution mode, the SNDR degrades as the delay decreases
because the DAC settling error becomes fatal compared to
the low resolution mode.
Figure 22 shows the measured SNDR against sampling
frequency at various resolution modes. The delay code is
set at optimum value which keeps good SNDR at each resolution mode. By optimizing delay time against resolution,
the sampling frequency can be increased as the operating
resolution is lowered.
Figure 23 shows the ADC figure of merit (FoM) against
sampling frequency at dierent resolution mode. At each
resolution mode, as the sampling frequency exceeds the
speed limitation, the SNDR and FoM begin to degrade. The
best FoM of 3.4 fJ/conv. was achieved at 10 bit mode with
sampling frequency of 160 kS/s.
From Figs. 18 to 23, all the measurements were carried
out at power supply voltage of 0.4 V.
The performance of the fabricated ADC was also measured at dierent power supply voltage.
The relation between the SNDR and maximum sampling frequency (Fs max) at each resolution mode is shown
in Fig. 24 with the power supply voltage of 0.4, 0.5, 0.7
and 1.0 V. Fs max is defined as the maximum sampling frequency which all the conversion cycle is completely finished
at each resolution mode. For example, at VDD of 0.4 V, it
corresponds to the envelope of all the curves in Fig. 22. If
the power supply is increased to 1.0 V, ENOB of 8.7 bit is
SHIKATA et al.: A 410 BIT, 0.41 V POWER SUPPLY, POWER SCALABLE ASYNCHRONOUS SAR-ADC
451
References
Conclusion
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Akira Shikata
received B.S. and M.S.
degrees in electronics and electrical engineering from Keio University, Yokohama, Japan, in
2008 and 2010, respectively, where he is currently working toward the Ph.D. degree. His
current research interests lie in low-power and
low-voltage data converters.
Ryota Sekimoto
received B.S. degrees in
electronics and electrical engineering from Keio
University, Yokohama, Japan, in 2011, where
he is currently working toward the M.S. degree.
Since 2010, he has been working on ultra low
power ADC for wireless sensor network.
Kentaro Yoshioka
received B.S. degrees in
electronics and electrical engineering from Keio
University, Yokohama, Japan, in 2012, where
he is currently working toward the M.S. degree.
His current research interests lie in low voltage
and high speed data converters.
Tadahiro Kuroda
received the Ph.D. degree in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1999. In 1982,
he joined Toshiba Corporation, where he designed CMOS SRAMs, gate arrays and standard cells. From 1988 to 1990, he was a Visiting Scholar with the University of California,
Berkeley, where he conducted research in the
field of VLSI CAD. In 1990, he was back to
Toshiba, and engaged in the research and development of BiCMOS ASICs, ECL gate arrays,
high-speed CMOS LSIs for telecommunications, and low-power CMOS
LSIs for multimedia and mobile applications. He invented a Variable
Threshold-voltage CMOS (VTCMOS) technology to control VTH through
substrate bias, and applied it to a DCT core processor and a gate-array
in 1995. He also developed a Variable Supply-voltage scheme using an
embedded DC-DC converter, and employed it to a microprocessor core
and an MPEG-4 chip for the first time in the world in 1997. In 2000,
he moved to Keio University, Yokohama, Japan, where he has been a
professor since 2002. He was a Visiting Professor at Hiroshima University, Japan, and the University of California, Berkeley. His research interests include low-power, high-speed CMOS design for wireless and wireline communications, human computer interactions, and ubiquitous electronics. He has published more than 200 technical publications, including 60 invited papers, and 21 books/chapters, and has filed more than
100 patents. Dr. Kuroda served as the General Chairman for the Symposium on VLSI Circuits, the Vice Chairman for ASP-DAC, sub-committee
chairs for A-SSCC, ICCAD, and SSDM, and program committee members for ISSCC, the Symposium on VLSI Circuits, CICC, DAC, ASP-DAC,
ISLPED, SSDM, ISQED, and other international conferences. He is a recipient of the 2005 P&I Patent of the Year Award, the 2006 LSI IP Design
Award, the 2007 ASP-DAC Best Design Award, the 2009 IEICE Achievement Award, and the 2011 IEICE Society Award. He is an IEEE Fellow, an
elected AdCom member for the IEEE Solid-State Circuits Society and an
IEEE SSCS Distinguished Lecturer.
Hiroki Ishikuro
received the B.S., M.S.
and Ph.D. degrees in electrical engineering from
the University of Tokyo, Tokyo, Japan, in 1994,
1996, and 1999, respectively. In 1999, he
joined the System LSI Research and Development Center, Toshiba Corp., Kawasaki, Japan,
where he was involved in the development of
CMOS RF and mixed-signal circuits for wireless interface chips. In 2006, he joined the Department of Electrical Engineering at Keio University as an assistant professor and started a research on high-speed inductive-coupling links for 3-D chip integration and
non-contact connector. He is currently an associate professor of Keio University, and focuses on the mixed-signal circuit and system designs for extremely low-power interfaces. He is a member of the Technical Program
Committee for Symposium on VLSI Circuits.