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SIMULATION OF DOUBLE GATE TUNNEL

FIELD EFFECT TRANSISTOR

REQUIREMENT FOR THE AWARD OF THE AWARD OF THE DEGREE OF


Bechelore of Technology
in
Electronics and Communication Engineering

Rasika Gupta
Beena Kothari
Jyotsana Rawat
Parvati Bhandari

2012
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
G B PANT ENGINEERING COLLEGE
PAURI GARHWAL (UTARAKHAND)-246194

Contents

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
Certificate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ix

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Acknowlegement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xi

1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1
1.2
1.3

MOTIVATION FOR THE PRESENT RESEARCH . . . . . .


NATURE OF THE PROBLEM . . . . . . . . . . . . . . . . . .
RECENT RESEARCH RELEVANT TO THE PROBLEM .

1
3
3

1.4

RESEARCH PROBLEM STATEMENT . . . . . . . . . . . . .

2. DEVICE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 SEMICONDUCTOR PHYSICS . . . . . . . . . . . . . . . . . .
2.1.1 SILICON CRYSTAL STRUCTURE . . . . . . . . . . . .

6
6
6

2.1.2
2.1.3

ENERGY BAND THEORY . . . . . . . . . . . . . . . . .


ELECTRONS AND HOLES . . . . . . . . . . . . . . . .

6
7

2.1.4 DOPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOSFET AND ITS CHARACTERISTICS . . . . . . . . . . .
2.2.1 OPERATING MODES . . . . . . . . . . . . . . . . . . . .

7
9
10

2.3

CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 SCALING AND POWER DENSITY . . . . . . . . . . .

13
14

2.4

BAND-TO-BAND TUNNELING TRANSISTOR . . . . . . .

14

2.2

Contents

iii

2.4.1 PRINCILPLE OF OPERATION . . . . . . . . . . . . . .


ADVANTAGES OF PIN TFET OVER MOSFET . . . . . . .
DEVICE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . .

15
16
17

2.6.1
2.6.2

STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . .
DEVICE PARAMETERS . . . . . . . . . . . . . . . . . .

17
18

2.6.3
2.6.4
2.6.5

WORKING . . . . . . . . . . . . . . . . . . . . . . . . . . .
BAND TO BAND TUNNELING TRANSMISSION .
SUB-THRESHOLD SWING IN TUNNEL FETS . . .

18
19
22

2.6.6

TUNNEL FET TEMPERATURE CHARACTERIS . .

25

3. DEVICE SIMULATION . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 SILVACOS ATLAS DEVICE SIMULATOR . . . . . . . . . . .

27
27

2.5
2.6

3.1.1
3.1.2
3.1.3

ATLAS INPUTS AND OUTPUTS . . . . . . . . . . . .


MODES OF OPERATION . . . . . . . . . . . . . . . . .
ORDER OF COMMANDS . . . . . . . . . . . . . . . . .

27
27
28

Comparison between MOSFET and DGTFET Transfer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


DGTFET PARAMETERS OPTIMIZATION . . . . . . . . . .

34
35

3.3.1
3.3.2

DIELECTRIC CONSTANT OF GATE DIELECTRIC


THICKNESS OF SILICON BODY . . . . . . . . . . . .

35
37

3.3.3
3.3.4
3.3.5

CHANNEL LENGTH . . . . . . . . . . . . . . . . . . . .
GATE WORK FUNCTION . . . . . . . . . . . . . . . . .
GATE DI-ELECTRIC THICKNESS . . . . . . . . . . .

38
38
40

RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 STRUCTURE AND PARAMETERS . . . . . . . . . . .

40
40

3.4.2
3.4.3
3.4.4

ON-CURRENT OF DGTFET . . . . . . . . . . . . . . .
TRANS-CONDUCTANCE VS VGS CURVE . . . . .
ENERGY BAND DIAGRAMS . . . . . . . . . . . . . . .

41
41
41

3.4.5
3.4.6

ELECTRIC FIELD . . . . . . . . . . . . . . . . . . . . . .
POTENTIAL . . . . . . . . . . . . . . . . . . . . . . . . . .

41
45

3.4.7

CURRENT FLOWLINES . . . . . . . . . . . . . . . . . .

45

4. CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 FUTURE SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . .

47
48

A. DECKBUILD CODING FOR ATLAS . . . . . . . . . . . . . . . . . . . .


A.1 Code for ON-current comparison between DGTFET before optimiza-

52

3.2
3.3

3.4

tion and after optimization

. . . . . . . . . . . . . . . . . . . . . . .

52

Contents

iv

A.2 Code for contour plots comparison between DGTFET before optimization and after optimization . . . . . . . . . . . . . . . . . . . . . . . .

55

List of Figures

2.1
2.2

A simple diagram of an isolated si atom and si crystal structure . . .


A basic energy diagram at 0K . . . . . . . . . . . . . . . . . . . . . .

8
8

2.3
2.4
2.5

A basic energy diagram at room temperature . . . . . . . . . . . . . .


crystal lattice structure doped with a Boron impurity . . . . . . . . .
Structure of a MOSFET . . . . . . . . . . . . . . . . . . . . . . . . .

8
9
10

2.6
2.7

crossection of MOSFET operating in linear region . . . . . . . . . . .


crossection of MOSFET operating in saturation . . . . . . . . . . . .

11
12

2.8
2.9

Structure of a CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . .
(a) Active power consumption has been increasing with shrinking technology nodes (b)Standby leakage power also increasing with shrinking

13

technology nodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Left: Structure of a n-i-p Tunnel FET with external voltage sources.

14

Right: Band profile of the Tunnel FET in the off-state without applied
VDS. The bandgap blocks any current flow between source and drain.
The Fermi-distributions in source and drain are plotted in gray . . . .
2.11 n-FETs. (a) Single-gate. (b) DG. SiO2 and high- gate dielectrics . . .
2.12 : Energy band diagrams taken horizontally across the body of a Tun-

15
18

nel FET in (a) the off-state where the only current comes from p-i-n
leakage, (b) the on-state with a negative bias on the gate leading to
pFET-type behaviour, and (c) the on-state with a positive bias on the
gate leading to nFET-type behavior. . . . . . . . . . . . . . . . . . .

19

List of Figures

vi

2.13 : Band-to-band tunneling can be calculated by approximating the


energy barrier width by a triangular potential energy barrier, where
the electrons must tunnel through the widest distance at the base of
the triangle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14 Energy band cross section of a Tunnel FET showing the triangular
barrier approximation within the bands, , the screening length , and
the filtering behavior of the device in the on-state . . . . . . . . . . .
2.15 Dependence of the Tunnel FET subthreshold slope on gate voltage for

20

22

different dielectric constants . . . . . . . . . . . . . . . . . . . . . . . 24


2.16 comparison of IDS-VGS for a conventional MOSFET and a Tunnel FET 24
2.17 Visual definitions of point swing, taken at the steepest point of the
IDS-VGS curve, and average swing, taken as the average from turn-on
to threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24

2.18 Simulated IDS-VGS characteristics for various temperatures for a doublegate Tunnel FET with dielectric = 21. VDS = 1 V. As temperature
increases, Ioff increases, but Ion changes very little. Inset: Subthreshold swing at specific VGS values, vs. temperature in Kelvin. The
swing is only slightly affected by changes in temperature. . . . . . . .

25

3.1
3.2

ATLAS Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . .


Comparison of mesh grids when using a multiplier of 5 and 1 . . . . .

30
30

3.3
3.4
3.5

ATLAS Mesh and Region Boundaries for a DGTFET . . . . . . . . .


ATLAS Doping Profile of DGTFET . . . . . . . . . . . . . . . . . . .
Some of the mobility models available in ATLAS . . . . . . . . . . .

30
31
32

3.6
3.7

DGTFET Transfer Characteristics for various Gate Dielectric . . . .


Characteristics of a simplified single-gate NMOSFET for various gate
dielectrics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

34

3.8
3.9

34

DGTFET Transfer Characteristics for various Gate Dielectric . . . .


DGTFET Trans-conductance (gm) vs VGS Curve for various Dielectrics

36

(VDS=1V, L=50 nm, tox=3 nm, tsi=10 nm) . . . . . . . . . . . . . .


3.10 DGTFET Transfer Characteristics for various tsi . . . . . . . . . . .
3.11 DGTFET Trans-conductance (gm) vs VGS Curve for various tsi . . .

36
37
37

3.12 DGTFET Transfer Characteristics for various channel lengths, L . . .


3.13 DGTFET Trans-conductance (gm) vs VGS Curve for various L (Other

38

parameters are same as for Fig.6.1) . . . . . . . . . . . . . . . . . . .


3.14 DGTFET Transfer Characteristics for various gate work function . .

38
39

List of Figures

vii

3.15 DGTFET Trans-conductance (gm) vs VGS Curve for various gate


work function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16 DGTFET Transfer Characteristics for various gate dielectric thickness

39
40

3.17 DGTFET Trans-conductance (gm) vs VGS Curve for various gate dielectric thickness . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

42

3.18 Optimized structure of DGTFET . . . . . . . . . . . . . . . . . . . .


3.19 Comparison of ON-Current for optimized DGTFET and DGTFET
before optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . .

42
42

3.20 Comparison of transconductance vs VGS curve for optimized DGTFET and DGTFET before optimization . . . . . . . . . . . . . . . .

43

3.21 Energy Band Diagram of DGTFET before Optimization . . . . . . .


3.22 Energy Band Diagram of DGTFET after Optimization . . . . . . . .
3.23 Contour plot of Electric Field across DGTFET before optimization .

43
43
44

3.24 Contour plot of Electric Field across DGTFET after optimization . .


3.25 Contour plot of potential across DGTFET before optimization . . . .

44
45

3.26 Contour plot of potential across DGTFET after optimization . . . . .


3.27 Contour plot of current flowlines in DGTFET before optimization . .
3.28 Contour plot of current flowlines in DGTFET after optimization . . .

45
46
46

Abstract

The down-scaling of conventional MOSFETs has led to an impending power crisis,


in which static power consumption is becoming too high. In order to improve the
energy-efficiency of electronic circuits, small swing switches are interesting candidates
to replace or complement the MOSFETs used today. Tunnel FETs, which are gated
p-i-n diodes whose on-current arises from band-to-band tunneling, are attractive new
devices for low-power applications due to their low off-current and their potential for
a small subthreshold swing.
The numerical simulations presented in this thesis have been carried out using
a non-local band-to-band tunneling model in Silvaco Atlas. Numerical simulations
based on correct underlying models are important for emerging devices, since they
can provide insights about optimization before fabrication is carried out, can aid the
understanding of device physics through 1D and 2D cross sections, and can be the
basis for the formation of an accurate compact model.

Certificate

This is to certify that the project entitled SIMULATION OF DUAL GATE


TUNNEL fIELD EFFECT TRANSISTOR being submitted by RASIKA GUPTA,
BEENA KOTHARI,JYOTSANA RAWAT AND PARVATI BHANDARI to Department of Electronics and Communication Engineering, G B Pant Engineering College,
Pauri Garhwal (Uttarakhand) for the award of Bachelor of Technology in Electronics and Communication Engineering, is a bonafide work carried out by them under
my guidance and supervision. The results embodied in the report have not been
submitted for the award of any other degree.
I wish them all success in their future endeavours.
Date: 2 June 2012
Place: GBPEC, Pauri
Mr.Balraj Singh
Assistant Professor
Deptt of Electrical & Electronics Engg
G.B. Pant Engineering College
Pauri Garhwal (UK)-246194

Preface

One goal of this thesis is to stay within the framework of what is possible in standard
industrial nano-electronics clean-rooms today, without requiring processes whose
mastery lies many years in the future. For this reason, the focus of this thesis is
on all-silicon devices
The optimization of the static characteristics of a Tunnel FET is carried out,
looking at dielectric constant of gate dielectric (ox), silicon body thickness (tsi),
Channel Length (L), gate work function () and gate dielectric thickness (tox).
Numerical simulations have proven to be an effective means to investigate Tunnel FET behaviour and the dependence of its static characteristics on changes in
dimensions, doping, and other parameters. The work presented here can be useful to
other researchers who will be designing and fabricating Tunnel FETs, and developing
analytical and compact models for these devices.

Acknowlegement

This little work of creation would not have been possible without the kind help,
coordination and extended support of some people. Thanks first and foremost to Mr.
Balraj Singh, Asst Professor, the project guide who helped us find this interesting
thesis topic.
We would like to thank Dr. Y. Singh (H. O. D.), ECE Department, for his
guidance, intelligent instructions in the details of semiconductor device operations
and for sharing his knowledge and working with us on several Tunnel FET studies
and publications. His constructive criticism and timely review on the project has
resulted in several improvements in the project. We would like to thank again to
Dr. Y. Singh (H.O.D.) and Dr. A. K. Gautam, Associate Professor, GBPEC for
providing us the facilities and making us strive for the best possible output under
their ardent observations.
Last but not the least we would like to thank our institute G.B.P.E.C, Pauri, for
including such type of curriculum that helped us improves our knowledge.
RASIKA GUPTA
BEENA KOTHARI
JYOTSANA RAWAT
PARVATI BHANDARI

CHAPTER

INTRODUCTION

1.1

MOTIVATION FOR THE PRESENT RESEARCH

At present there is a power crisis currently faced by conventional MOSFETs, due


to their ever increasing static power consumption. The reason behind this is that
in previous simulations MOSFET was scaled by keeping the electric fields inside it
unchanged . For this all device dimensions were scaled by 1/, while the doping of the
source and drain regions was increased by a factor of . Applied voltages were scaled
by 1/.
But this scaling [8] rule no longer worked well as due to scaling 1.4 m node changes
to the 65 nm node and supply voltage VDD decreased to about 20
The most important consequence of VDD reducing during device scaling while
VT reduces significantly less, is that the gate overdrive, also goes down. When
gate overdrive decreases, on-current decreases, which negatively affects device performance, the Ion/ Ioff ratio and dynamic speed (Cg VDD/Ion). There are two
possible solutions to this problem of needing a high gate overdrive: either VDD can
stay higher than it should with constant field scaling [?], or VT can be scaled down
more aggressively.
In order to maintain acceptable levels of gate overdrive, VDD scaling has slowed
down drastically. When the supply voltage decreases along with device dimensions,
then the power density remains constant, which means that the energy needed to
drive the chip, and the heat produced by the chip, remain constant. If VDD does not
decrease, and yet device dimensions decrease, and more devices are added to a chip

Chapter 1. INTRODUCTION

such that chip size is not significantly reduced, then it can be expected that power
consumption will rise considerably.
Second option for keeping a high gate overdrive: scaling down VT. Is to decrease
sub threshold swing S = dV GS/d(log IDS) and if we want to shift VT by 60 mV,
then the price to pay is an increase of one dynamic, static power and off current. If we
want to decrease VT by shifting the curve left, we pay a price in leakage current [9].
Over the last decades, the continuous down-scaling of metal-oxide-semiconductor
field-effect transistors (MOSFETs) [22] enabled faster and more complex chips while
at the same time the space and power-consumption [23] was kept under control. Since
logic devices operate at a given on/off-current-ratio, the limited sub threshold swing
will prevent further reduction of the operation voltage, which is the main parameter
to reduce the power consumption.
Our report started with the history of transistors that use band-to-band tunneling [20] current in their on-state, starting from 1978 and continuing to the present
day (2010), showing that the Tunnel FET is still an emerging device with much
unexplored potential.
The basics of semiconductor materials ,then the structure , working and characteristics of MOSFET, tunnel MOSFET and double gate tunnel MOSFET [26] are
discussed.
At this time we would like our computers, appliances, and gadgets to use less
power [22] because its better for the environment. On a more personal level, its
less expensive to use less electricity. On a practical level, its more convenient for
battery-operated gadgets because their batteries will last longer before needing to be
charged. And on a comfort level, it is better when laptops and hand-held gadgets
have a lower power density and therefore produce less heat.
This too has a limit, since we would like our appliances, computers, and gadgets
to stay the same size or shrink, not get larger in order to accommodate a large heat
sink required by the power-hungry chip inside. This give motivation order to circuit
engineers to design circuit that respond to the power crisis, a handful of currentlyused circuit-level solutions will be presented in this section. One efficient solution for
reducing leakage is to cut off the power supply to idle circuit blocks by using sleep
transistors.
Second solution for power crisis is to design conventional MOSFETs with S
60mV/decade [34] at room temperature. Example of small swing device is IMOS
which is a gated p-i-n junction whose gate is offset from one of the junctions such a
very high electric field exists in the non-gated portion of the i-region when the device
is on, leading to avalanche breakdown. The impact ionization [32] process means

Chapter 1. INTRODUCTION

that the IMOS can have a very small sub threshold swing and high on-current.
Further researched examples are shown MEM and NEM switches, then Tunnel
Fet and finally double gate Tunnel Fet.
Therefore in our current project we worked on previously designed dual gate
tunnel Fet and then optimized its parameters for better performance .

1.2

NATURE OF THE PROBLEM

Numerical simulations of DG Tunnel FETs [10] such as the ones presented in this
thesis allow the investigation of the device physics, with the possibility to see inside
a device through cross sections in 2D to obtain optimal DGTFET structure for low
power application [30].

1.3

RECENT RESEARCH RELEVANT TO THE PROBLEM

Quinn et al. at Brown University were the first to propose the gated p-i-n structure of a Tunnel FET [32] in 1978, and suggested the usefulness of this device for
spectroscopy.
In 1995, Reddick and Amaratunga at Cambridge, seemingly unaware of all the
previously mentioned work, published measured characteristics of silicon Surface Tunnel Transistors [24]. They were motivated by the desire for devices that would be
faster than conventional MOSFETs, as tunneling devices are, and that could be scaled
down more easily without running into problems such as punch-through. They are
sometimes erroneously given credit for being the first to make silicon Tunnel FETs [7].
In 1997, Koga and Toriumi at Toshiba proposed a post-CMOS three-terminal
silicon tunneling device [15] with the same structure as a Tunnel FET, though the
experimental results which were presented showed a device that was forward-biased.In
2000, Hansch et al. at the University of the German Federal Armed Forces in Munich
showed experimental results from a reverse-biased vertical silicon tunneling transistor
[32], with a highly-doped boron delta-layer [17] to create an abrupt tunnel junction,
and noted the saturation behaviour in the ID-VG characteristics.
In 2004, band-to-band tunneling was demonstrated in carbon nanotube (CNT)
FETs [14] by Appenzelleret al. In order to create the energy bands necessary for
tunneling, a back gate and a top gate were used. The researchers claimed that the
one-dimensionality of the CNTs led to extremely different band bending conditions

Chapter 1. INTRODUCTION

than those in 3D semiconductors. A subthreshold swing [16] smaller than the 60


mV/dec limit of conventional MOSFETs was reported for the first time.
In 2006, Zhang et al. at Notre Dame remarked once again what others before
them had noticed that theoretically, it is indeed possible for Tunnel FETs to have
a sub-threshold swing lower than 60mV/dec [33]. The structure they studied was
a gated p-n diode, but the general equations they put forth, and the band-to-band
tunneling behaviour, would be the same as for a gated p-i-n structure.
In 2007, Verhulst et al. at IMEC showed by simulation that shortening Tunnel
FET gate length [29], so that the gate covers the source-side junction where tunneling
takes place, but does not cover the majority of the intrinsic region, has the benefits of
decreasing off-current (tunneling through the drain-side junction) and reducing speed,
with a small or no reduction in the on-current, depending on the device design. In
the same year, Toh at the National University of Singapore published a study of
double-gate Tunnel FET silicon body thickness optimization, in which he showed an
optimal device thickness for maximum on-current.
There were also some fabricated Tunnel FET results in 2009. Sandow et al.
from Forschungszentrum Jlich published experimental data for p-type Tunnel FETs
on SOI [9] [21], showing the effects of varying source and drain doping levels, gate
dielectric thickness, and device length.
Luisier et al. at Purdue University did an atomistic study of InAs Tunnel FETs
[16], in which they found that subthreshold swings of less than 60 mV/decade at room
temperature could only be attained if single-gate body thicknesses were less than 4
nm, and double-gate body thicknesses [1] were less than 7 nm, or for nanowires
[31]of less than approximately 10 nm diameter. Looking at more exotic material
systems, Tunnel FETs could one day be fabricated on grapheme nanoribbons [31],
which are basically unrolled single-walled carbon nanotubes [14]. The simulated
transfer characteristics presented in represent the extremely optimistic upper bounds
of possible device performance and reach a simulated subthreshold swing of 0.19
mV/dec.
In 2010, Kathy Boucart and Adrian Mihai Ionescu, Member, IEEE proposed and
validated a novel design for a double-gate tunnel field-effect transistor (DG Tunnel
FET) [5], for which the simulations show significant improvements compared with
single-gate devices using an SiO2 gate dielectric. Showing an ON-current as high as
0.23 mA for a gate voltage of 1.8 V, an OFF-current of less than 1 fA (neglecting gate
leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum
point slope of 11 mV/dec.

Chapter 1. INTRODUCTION

1.4

RESEARCH PROBLEM STATEMENT

The work accomplished in this dissertation has been carried out in terms of the
following intermediate stages as follows: 1. Simulation of Dual Gate TFET device
structure. 2. Optimization of device parameters to improve sub-threshold swing and
ON-current.

CHAPTER

DEVICE DESCRIPTION

2.1

SEMICONDUCTOR PHYSICS

When discussing basic electrical properties, materials can be broken into three basic
categories: insulator, conductor and semiconductor. Semiconductors are the most
intriguing type of material and have lead the way for the many of the advancements
of technology in society. The most basic intrinsic semiconductor is silicon and it will
be used to demonstrate basic semiconductor physics and operation [2].

2.1.1

SILICON CRYSTAL STRUCTURE

The Periodic Table shows that Silicon (Si) is a Group IV element. By being a Group
IV element when isolated it has 4 electrons in its outer most shell [11].
These electrons are called valance electrons and when perfect pure Silicon crystal structure occurs these electrons are shared between atoms next to each other
producing a bonded diamond structure. This bonded pure intrinsic Silicon is an
ideal structure at zero Kelvin with no impurities or crystal defects. To understand
what happens when temperature increases or impurities are added knowledge of band
theory is required [11].

2.1.2

ENERGY BAND THEORY

Energy band theory is an important concept in explaining how electrons react to


different conditions within a crystal structure. The spread of energies of electrons can

Chapter 2. DEVICE DESCRIPTION

Fig. 2.1: A simple diagram of an isolated si atom and si crystal structure


be described by a set of allowed states that are called energy bands [Ref.fig2.2]. These
energy bands consist of a lower band of energy states called the valence band, an
upper band of energy states called the conduction band and the energy gap between
these states, which is called the bandgap [Ref.fig2.2]. Electrons must either exist
in the Conduction Band or the Valence Band. Different elements have different
value bandgaps and these different bandgaps greatly affect these elements electrical
properties. The Fermi level (EF) is also used in the band diagram and it denotes the
average energy level for electrons. In an intrinsic semiconductor EF is usually placed
in the center of the bandgap. Elements with larger bandgaps are insulators, with no
bandgaps or negative band gaps are conductors and semiconductors fall in between
the two . For a material to conduct electricity it must have electrons in the conduction
band or holes in the valance band. Electrons naturally gravitate towards lower energy
levels and when an element is at zero Kelvin the valance band is completely full of
electrons and the conduction band is completely void of electronics [2].

Fig. 2.2: A basic energy diagram at 0K

Chapter 2. DEVICE DESCRIPTION

Electrons in the conduction band are called free electrons. These electrons are
free to move and allow electricity to conduct through the material. Semiconductors,
like silicon, at room temperature have a limited population of free electrons that
can be artificially increased or decreased to change the materials ability to conduct
electricity.At room temperature the free electrons in the conduction band at equilibrium are caused by thermal generation. Thermal generation is the lattice vibrations
that apply enough energy for electrons to jump the bandgap and become free in the
conduction band [11].

Fig. 2.3: A basic energy diagram at room temperature

2.1.3

ELECTRONS AND HOLES

When an electron is excited and moves from the valance band to the conduction band
the absences of the electron in the bond is called a hole. These electrons and holes
provide a method of current flow through a semiconductor. When a hole is created a
free electron will move and fill it. When the electron moves to fill the hole it leaves a
hole behind. This gives the appearance of a hole moving in the opposite direction of
the electron. This apparent movement is called hole flow. When an electric field is
applied to a semiconductor the electrons will move towards the negative side of the
field and the holes will move towards the positive side [11].

2.1.4

DOPING

The electrical properties of pure Si can be greatly changed by introducing small


amounts of impurities. Since Si is a Group IV, and has 4 valance electrons, it forms
strong covalent bonds with the other Si atoms in the diamond lattice. During a
covalent bond two atoms supply electrons to fill each others valance band. This

Chapter 2. DEVICE DESCRIPTION

forms a strong bond because both atoms treat the shared electrons as there own .
If a Group III atom, such as Boron (B), is added as a dopant to a pure Si lattice
it will change the electrical properties of the semiconductor. Boron only has three
electrons in its valance shell when it bonds with four Si atoms in the lattice one of
the covalent bonds will be missing an electron which will be a hole. Nearby electrons
can tunnel into this hole and this will make a hole away from the original B impurity.
This action is repeated until a free hole is created. Since the B atom creates this hole
that will accept an electron therefore it is called an acceptor. This doping produces
a p-type extrinsic semiconductor [11].

Fig. 2.4: crystal lattice structure doped with a Boron impurity


Intrinsic Silicon can also be doped with a Group V element such as Arsenic
(As).Since As has five valance band electrons when it bonds with four Si atoms in
the lattice structure there is one extra electron which is not used in the covalent
bonds. This extra electron continues to orbit the As within the Si lattice structure.
It takes very little energy to free the extra electron and it is usually freed by the
thermal energy of atomic vibrations at room temperature. Since As donates an
electron to the conduction band it is called a donor. This type of doping produces
an n-type material.

2.2

MOSFET AND ITS CHARACTERISTICS

A MOSFET is based on the modulation of charge concentration caused by a MOS


capacitance. The structure of a MOSFET is shown in Figure 3.5. The MOSFET has
two terminals, called source and drain, which are connected to highly doped regions
which are separated by a region called the channel. These regions are either p- or ntype, but they must both be of the same type. The highly doped regions are denoted

Chapter 2. DEVICE DESCRIPTION

10

by a + following the type of doping as shown in the Figure5 and are separated by a
doped region of opposite type, known as the body or substrate. This region is not so
highly doped. The third electrode in the MOSFET, called the gate, is located above
the body and insulated from all of the other regions by an oxide (usually an oxide of
Si) [2].

Fig. 2.5: Structure of a MOSFET


The source is so named because it is the origin of the charge carriers (electrons
for n-channel, holes for p-channel) that flow through the channel; similarly, the drain
is where the charge carriers leave the channel. The MOSFET can be of n-channel or
p-channel depending on the doping material in the source and drain of the MOSFET.
The MOSFET can be of two types; Depletion MOSFET and Enhancement MOSFET.
In the case of depletion type of MOSFET the channel is lightly doped with the same
material as that of source and drain to reduce the threshold voltage. The operation of
both types of MOSFETs is similar and is used depending on the applications. Since
the enhancement MOSFET is common, the operation discussed here are based on
enhancement MOSFET only. The different modes of operation of an enhancement
type MOSFET are discussed below.

2.2.1

OPERATING MODES

In the case of n-channel MOSFET, when there is no voltage applied to the gate there
is no channel formation between source and drain and hence there is no current flow
between them. However, when a positive gate-source voltage is applied, it creates a
channel at the surface of the p- region which is negatively charged, under the oxide.
When a negative voltage is applied between gate and source, the channel disappears
and no current can flow between the source and the drain.

Chapter 2. DEVICE DESCRIPTION

11

If the MOSFET is a p-channel or p-MOSFET, then the source and drain are P+
regions and the body is an n- region. When a negative gate-source voltage is applied,
it creates a channel which is positively charged at the surface of the nregion, just
below the oxide. The operation of a MOSFET can be divided into three different
regions, depending upon the voltages at the terminals. The three regions of operation
are cutoff, linear and saturation which are explained below [2]
1 Cut-off or subthreshold mode (WhenV GS < V th ) where Vth is the threshold
voltage of the device and VGS is the gate to source voltage)Under these operating
conditions the transistor is turned off, and there is minimal conduction between the
drain and source. However, the Boltzmann distribution of electron energies allows
some energetic electrons at the source to enter the channel and flow to the drain
creating a diffusion current. This subthreshold current is an exponential function of
the gate to source voltage. The current between the drain and source should ideally
be zero when the transistor is being used as a turned-off switch; the weakinversion
current, sometimes called subthreshold leakage is very critical in low power digital
circuit]. However, the subthreshold current or weak inversion region is an efficient
region of operation in some analogue circuits.
2 Triode or linear region ( When V GS > V th and V DS < V GSV T H ) In the
linear region where the gate to source voltage VGS is greater than the threshold
voltage Vth the transistor is turned on, and a channel has been created which allows
current to flow between the drain and source. This condition is depicted in Figure
3.6. The MOSFET operates like a resistor, controlled by the gate voltage relative to
both the source and drain voltages.

Fig. 2.6: crossection of MOSFET operating in linear region

Chapter 2. DEVICE DESCRIPTION

12

The drain current is given by the relation


Id = n

CoxW
V ds2
((V gs V th)V ds
)
L
2

Where n is the charge-carrier mobility, W is the gate width, L is the gate length
and Cox is the gate oxide capacitance per unit area.
Saturation (WhenV GS < V DS and V DS < V GS V T H ) In this case when

the drain voltage is increased, a channel has been created, which allows current to
flow between the drain and source. Since the drain voltage is higher than the gate
voltage, a portion of the channel is turned off. The onset of this region is also known
as pinch-off. In this region the drain current is now relatively independent of the
drain voltage and the current is controlled by only the gate to source voltage. This
operating condition is shown in Figure 3.7

Fig. 2.7: crossection of MOSFET operating in saturation


The equation for the current in this region is given by
Id = n

CoxW
(V gs V th)2
2L

For larger drain biases, the length of the inverted drain region decreases with
increase in drain bias leading to channel length modulation which is discussed later
in this chapter. Channel length modulation leads to an increase of current in the
channel with drain bias and hence a lower output resistance for the MOSFET .
above Equation can be multiplied by (1 + VDS) to take account of the channel
length modulation effect; where is the channel length modulation parameter.

Chapter 2. DEVICE DESCRIPTION

2.3

13

CMOS

A balance of low power and high throughput are the main goals which the microelectronics industry must address in satisfying the demand for more advanced
applications in the consumer market sector for portable equipment in the modern
world. The designer can make optimizations at all levels of the design space, which
have a cumulative effect on the overall system power reduction. Much work has been
concentrated on architecture, algorithm, and system-level power minimization. The
technology for IC manufacturing is the only level that the designer has limited control to meet the constraints. Complimentary Metal Oxide Semiconductors (CMOS)
circuits were invented in 1963 by Frank Wanlass at Fairchild Semiconductor as a lowpower alternative to Transistor Transistor Logic (TTL). The first CMOS integrated
circuits were made by Radio Corporation of America (RCA) in 1968 by a group
led by Albert Medwin . CMOS found applications in the watch industry and in
other fields where battery standby capability was more important than speed. After
around twenty-five years, CMOS has become the predominant technology in digital
integrated circuits and still maintains this position. The main advantages of CMOS
over TTL are its energy efficiency, smaller area occupation, comparable operating
speed and manufacturing costs . CMOS benefits from the geometric scaling of dimensions that comes with every new technology node associated with semiconductor
processing. Besides all these advantages, low-power dissipation and larger integration
densities, compared to bipolar junction transistors, has made it the mainstay of the
microelectronics world. CMOS uses a combination of p-type and n-type MOSFETs
on the same substrate to implement logic gates and other digital circuits found in
computers, telecommunications and signal processing equipment. Figure 3.8 shows
the structure of a CMOS [23].

Fig. 2.8: Structure of a CMOS

Chapter 2. DEVICE DESCRIPTION

2.3.1

14

SCALING AND POWER DENSITY

Generations of CMOS technologies have thrived from scaling transistor dimensions.


While scaling primarily drives cheaper and denser integrated circuits because of the
reduced area, it also drives faster circuits. The increase in circuit density and functionality yields higher computing power at the cost of increased power consumption
per chip. As the number of transistors per unit area increases the rising power density
leads to severe packaging/thermal management concerns. There is also the issue of
increased leakage power and its impact on the battery life of electronic equipment [4].

Fig. 2.9: (a) Active power consumption has been increasing with shrinking technology nodes (b)Standby leakage power also increasing with shrinking
technology nodes.
Figure 3.9(a) and 3.9(b) illustrate the increase in active power consumption and
standby leakage (subthreshold leakage) power consumption for various CMOS technology nodes . The active and standby power is seen to increase steadily with scaling
transistor dimensions. As shown by the equations embedded in the figures both active and standby power scale with the operation voltage (Vdd) and can therefore be
reduced by scaling Vdd. Figure 3.10 shows that Vdd scaling has however remained
stagnant at 1V for several technology generations now.

2.4

BAND-TO-BAND TUNNELING TRANSISTOR

Although the principle of band-to-band tunneling [8] was already discovered in 1957
by L. Esaki and the first gated p-i-n structure was proposed in 1978 , the interest in
the first results on TFETs was limited. This changed rapidly after W. Hansch and I.
Eisele et al. started to investigate the TFET in 2000 and J. Appenzeller et al. found
in 2004 that the TFET might provide a means to overcome the 60 mV/dec switching

Chapter 2. DEVICE DESCRIPTION

15

limit of the classical MOSFET. Following these initial results, several groups started
to study the theoretical aspects of TFET operation. Among those were the impact
of the channel dimensionality , power consumption , phonon scattering [18], temperature dependence, gate overlap , threshold voltage , performance comparison to
CMOS, heterostructure TFETs, strain and general modeling. While Appenzellers
results were obtained with carbon-nanotube FETs [14], the adoption of the operating principle to silicon FETs seems to be more attractive because the mature silicon
technology

Fig. 2.10: Left: Structure of a n-i-p Tunnel FET with external voltage sources.
Right: Band profile of the Tunnel FET in the off-state without applied
VDS. The bandgap blocks any current flow between source and drain.
The Fermi-distributions in source and drain are plotted in gray

2.4.1

PRINCILPLE OF OPERATION

The device structure of the TFET resembles that of the MOSFET with one exception.
While in the MOSFET, source and drain are doped with the same type of dopant,
in the TFET, source and drain are of opposite doping types. The device structure
and band profile in equilibrium are drawn in Figure 2.10. In equilibrium, the built-in
potentials of the p-i and n-i junctions result in a staircase-like band-profile. If a small
VDS is applied to the equilibrium state [12], electron and hole currents are blocked by
the built-in potential barriers. This is the off-state of the TFET. Now, if a negative
gate-bias is applied, the bands in the channel move up. For negative VDS, charge
carriers can tunnel through the bandgap at the source/channel junction as soon as
the valence band in the channel is lifted above the conduction band in the source.
This operating mode is the p-channel on-state of the TFET because holes accumulate
in the channel. The n-channel on-state can be created by applying a positive VGS

Chapter 2. DEVICE DESCRIPTION

16

and negative VDS. In this case, the bands in the channel move down and tunneling
occurs at the channel-drain junction as soon as the conduction band in the channel
is pushed below the valence band in the drain [6].

2.5

ADVANTAGES OF PIN TFET OVER MOSFET

With the continual miniaturization of the MOSFET transistors, power dissipation


in integrated circuits has become a major roadblock to performance scaling [19] .
For more than 30 years, numerous breakthroughs in device and material design have
sustained an exponential increase in system performance. The recent introduction
of high-k gate oxides into semiconductor technology has also allowed much needed
reduction in gate leakage and improved the scalability of future devices. Nevertheless, the physical operational principles of conventional MOSFETs, based on the
thermionic emission of carriers over a channel barrier, have imposed fundamental
limits on voltage scaling and the reduction of energy dissipation. The subthreshold
swing (S) of a conventional MOSFET, which determines the ability to turn off the
transistor with the gate gate (VGS), has a fundamental limit of ()2.3BkTq where
kB, T, and q are the Boltzmann constant, temperature, and the electron charge, respectively (S = 60mV/decade at room temperature) [4]. Therefore, the requirement
of achieving a large on-state current (ION), while maintaining a small off-state leakage (IOFF), has hindered the scaling of the power supply voltage (VDD) in recent
years . Consequently, a device with S below the aforementioned conventional limit
is desirable for continued voltage scaling, and thereby reducing power dissipation in
circuits.
Field-effect transistors based on the band-to-band tunneling (BTBT) [20] phenomenon are being actively investigated due to their potential for low standby leakage
. It has been predicted through detailed device simulations that BTBT FETs could
produce subthreshold swings below the thermal limit in conventional semiconductor
materials such as silicon , as well as in carbon nanotube (CNT) based transistors .
Indeed, this has been experimentally demonstrated in CNTs and more recently with
a silicon based BTBT FET . BTBT occurs in two different transistor geometries; a
popular p-i-n geometry (hereafter called the TFET), and the conventional MOSFET
. In the case of CNT-MOSFETs it has been established that BTBT is dominated by
phonon assisted inelastic tunneling that severely deteriorates the device characteristics . On the other hand, phonon scattering has a less dramatic effect on TFETs,
and useful device properties are preserved under practical biasing conditions . The
important task of a comprehensive comparison of device performance between the

Chapter 2. DEVICE DESCRIPTION

17

p-i-n TFET and the conventional n-i-n MOSFET geometries. Here, we use CNTs
as the model channel material due to many benefits of that system. CNTs [14]
allow one-dimensional carrier transport without depletion capacitance effects, and
high performance transistors that operate near the ballistic limit have already been
demonstrated . They also have a direct energy bandgap and small carrier effective
masses that are favorable for BTBT devices . Furthermore, a detailed simulation
framework has been developed for modeling carrier transport through CNT transistors , and benchmarked against experiments. Therefore, many realistic aspects, such
as the effect of phonon scattering on device performance, have been comprehensively
explored in the case of CNT based MOSFETs as well as TFETs . Previous work has
also compared CNT transistor performance to that of silicon transistors and to that
based on silicon nanowires . Here we use similar device metrics to compare the performance between TFETs and MOSFETs using a uniform simulation environment
for both the devices.

2.6

DEVICE DESCRIPTION

Tunnel FETs, also referred to as TFETs, Surface Tunnel Transistors (STTs) or


Tunneling FETs, are promising devices to complement or even replace conventional
MOSFETs for low-power applications. They offer the potential for a very low offcurrent and a small subthreshold swing [16]. Tunnel FETs are interesting as lowpower devices because of their quantum tunneling barrier. When the devices are
turned on, the carriers must tunnel through the barrier in order for current to flow
from source to drain. When the devices are off, the presence of the barrier keeps the
off-current extremely low, several orders of magnitude lower than the off-current of
a conventional MOSFET.

2.6.1

STRUCTURE

Tunnel FETs are gated p-i-n diodes [19], or less commonly, gated p-n diodes. To
switch the device on, the diode is reverse biased, and a voltage is applied to the
gate. In order to be consistent with MOSFET technology, the names of the device
terminals are chosen such that voltages are applied in a similar way for Tunnel FET
operation. Since a reverse bias is needed across the p-i-n structure in order to create
tunneling, and since an NMOS operates when positive voltages are applied to the
drain and gate, the n-region of a Tunnel FET is referred to as its drain, and the p+
region as its source for an ntype device.

Chapter 2. DEVICE DESCRIPTION

18

Fig.5.1 shows the basic device structure for a typical p-i-n Tunnel FET. The
structure shown is an n-type device, with a p+ source and an n+ drain. In a p-type
Tunnel FET, the source would be doped n+ and the drain would be doped p+.

Fig. 2.11: n-FETs. (a) Single-gate. (b) DG. SiO2 and high- gate dielectrics

2.6.2

DEVICE PARAMETERS

The double-gate n-type Tunnel FETs investigated here have been simulated with
Silvaco Atlas, version 5.11.24.C. In all simulations, junctions were quasi-perfectly
abrupt (junction width 0.5 nm), and the p-type source, intrinsic region, and n-type
drain were doped at 1x1020, 1x1017, and 5x1018 atoms/cm3 respectively. The silicon
body thickness is 10 nm.
The gate dielectric covers the drain, intrinsic region, and source in all simulations.
Three different gate stacks were studied. The first uses 3 nm of SiO2 as a gate
dielectric ( = 3.9). The second employs 3 nm of a high-k dielectric [6] ( = 25),
which could be HfO2 or ZrO2. The third incorporates a gate dielectric with two
components: a 1 nm interfacial layer of oxynitride ( = 5.7) and 2 nm of a high-k
dielectric ( = 25), corresponding to a more realistic fabrication process. All Tunnel
FETs simulated here use a midgap (metal) gate work function of 4.5 eV.

2.6.3

WORKING

When a Tunnel FET is OFF, only p-i-n diode leakage current flows between the source
and drain, and this current can be extremely low (less than a fA/m). Fig.5.2(a) shows
the energy bands horizontally across the body of a Tunnel FET in the off-state [10],
with a reverse bias applied across the p-i-n junction, but no voltage applied to the
gate. When a Tunnel FET is designed with symmetry between the n- and p-sides

Chapter 2. DEVICE DESCRIPTION

19

(similar doping levels, similar gate alignment, etc.), the device exhibits ambipolar
behavior, whereby the transfer characteristics resemble those of a pFET when a
negative voltage is applied to the gate, and those of an nFET when a positive voltage
is applied to the gate.
Fig.5.2(b)shows the energy bands with a reverse bias applied across the device,
and a negative voltage applied to the gate [10]. The energy bands in the intrinsic
region under the gate are lifted, and the energy barrier is now small enough for bandto-band tunneling to take place between the valence band of the intrinsic region and
the conduction band of the n+-region.
When a positive voltage is applied to the gate, on the other hand, the energy
bands in the intrinsic region are pushed down, as in Fig. 5.2(c), and tunneling takes
place between the valence band of the p+-region and the conduction band of the
intrinsic region [10]. The energy barrier width for band-to-band tunneling is the
single most important factor that determines the amount of drain current through a
Tunnel FET.

Fig. 2.12: : Energy band diagrams taken horizontally across the body of a Tunnel
FET in (a) the off-state where the only current comes from p-i-n leakage,
(b) the on-state with a negative bias on the gate leading to pFET-type
behaviour, and (c) the on-state with a positive bias on the gate leading
to nFET-type behavior.

2.6.4

BAND TO BAND TUNNELING TRANSMISSION

An expression for the band-to-band tunneling [20] current in Tunnel FETs can be
found by using the WKB approximation and taking the tunnel barrier as a triangularly [28] shaped potential barrier as shown in Fig.5.3 With the WKB approximation,
the band-to-band tunneling transmission is given by

Chapter 2. DEVICE DESCRIPTION

Tt exp

20

x2

x1

|k(x)| dx

(2.1)

where k(x) is the quantum wave vector of the electron inside the barrier. Inside
a triangular barrier, the wave vector is
r

2m
(P E E)
(2.2)
h2
Here, PE is the potential energy, and E is the energy of the incoming electron.
When the triangular barrier is drawn at the coordinates shown in Fig.5.3, with the
k(x) =

electron at the energy of the widest part of the triangle (at E=0), then the E term
goes away, and PE can be replaced by the equation for the triangle: Eg/2-qFx, where
Eg is the band gap of the semiconductor material at the tunnel junction, and F is
the electric field. Then,

Fig. 2.13: : Band-to-band tunneling can be calculated by approximating the energy


barrier width by a triangular potential energy barrier, where the electrons
must tunnel through the widest distance at the base of the triangle.

k(x) =

2m Eg
(
qF x)
h 2

(2.3)

Plugging this into Eq.1 gives


Tt exp(2

x2

x1

2m Eg
(
qF x) dx)
h2 2

(2.4)

The next step is to carry out the integration

3
4 2m 3
( qF x) 2 )
Tt exp(
3qh 2

(2.5)

Chapter 2. DEVICE DESCRIPTION

21

Looking back at the triangular barrier, we know that at x = x2, (Eg/2 qFx) =
0, and that at x = -x1, (Eg/2 qFx) = Eg, so

3
4 2m Eg 2
)
Tt exp(
3qhF

(2.6)

Eq.6 is a general expression for band-to-band tunneling transmission. This equation can be improved slightly by making it more specific to tunneling transistors.
Now referring to Fig.5.4, the dimensions of the shaded triangular barrier [27] are a
height of + Eg, and a width of . The magnitude of the electric field corresponds to
the slope of the energy bands, so we can replace the electric field F by y/x = ( +
Eg)/. Since electric field is measured in V/m, and the new term has the units eV/m,
we must also cancel out an electron charge, which gives
IBT B

4 2m Eg 23
)
Tt exp(
3h( + Eg)

(2.7)

is the energy range over which tunneling can take place, Eg is the band gap at
the tunnel junction, is a screening length, and m* is the tunneling mass. There
are four important conditions in order for band-to-band tunneling to take place:
available states to tunnel from, available states to tunnel to, an energy barrier that
is sufficiently narrow for tunneling to take place, and conservation of momentum
. In order for band-to-band tunneling to take place in materials with an indirect
band gap such as silicon, crystal phonons [18] are necessary in order to conserve
momentum, and Eg in the numerator of Eq.7 is replaced by Eg-Ep, where Ep is
the phonon energy. The effective mass m* must then change to mrx*, which is the
reduced effective mass in the tunneling direction. If these changes are not made to
Eq.7, band-to-band tunneling current is overestimated for indirect materials.
The parameter deserves a bit more explanation. It has several different names,
including screening length, natural length, and Debye length, and refers to the spatial extent of the electric field, or the length over which an electric charge has an
influence before being screened out by the opposite charges around it . It can be expressed in terms of the dielectric constants and thicknesses of the gate dielectric and
semiconductor body of a device, and depends upon gate geometry. The expression
for a double-gate device is
=

si tsi tox
2ox

(2.8)

where Si and tSi are the dielectric permittivity and thickness of the silicon (or
whatever semiconductor material is used to make the device), and ox and tox are the

Chapter 2. DEVICE DESCRIPTION

22

dielectric permittivity and thickness of the gate dielectric. For a single-gate device,
the factor of (1/2)0.5 must be removed from the expression, and for a wrap-around
gate, the expression becomes more complicated . These equations for were created to
describe conventional MOSFET behavior, but have also been used for Tunnel FETs.
Fig.5.4 shows how the band-to-band tunneling behavior [7] of the Tunnel FET
acts as a band pass filter that cuts off the low-energy and high-energy tails of the
Fermi distribution of the n+-type source. The Fermi-Dirac distribution and Fermi
level for the source are first drawn at the left within the source, and the low-energy
tail of the distribution is crossed out because no carriers can exist at energies inside
the band gap. Then on the channel side, the source Fermi-Dirac distribution is shown
again, and this time the high-energy tail is crossed out since those energy levels cant
exist inside the band gap of the channel. The result is the version of the distribution
shown at the far right, in which only the electrons in the source within the energy
range are available for tunneling.

Fig. 2.14: Energy band cross section of a Tunnel FET showing the triangular barrier
approximation within the bands, , the screening length , and the filtering
behavior of the device in the on-state

2.6.5

SUB-THRESHOLD SWING IN TUNNEL FETS

The dependence of swing on gate voltage up to the threshold voltage (taken at IDS
= 10-7 A/m) is shown in Fig.5.5, demonstrating two important things. First, the
subthreshold swing of Tunnel FETs is not constant, but rather is a function of gate
voltage. And second, at low gate voltages, it is possible for Tunnel FETs to have a
subthreshold swing less than the 60 mV/decade MOSFET limit at room temperature.
In order to derive an expression for the subthreshold swing of a band-to-band
tunneling device, we can start with the expression given by Sze for the tunneling

Chapter 2. DEVICE DESCRIPTION

23

current through a reverse-biased p-n junction:


I = aV ef f F exp(

b
)
F

(2.9)

where
Aq 3
a=

rq

2m
Eg

4 2 h2

(2.10)

and

3
4 m Eg 2
b=
3qh

(2.11)

Veff is the bias at the tunnel junction and F is the electric field at the tunnel
junction. When the subthreshold swing is calculated as S = dVGS/d(log IDS), the
result is:
S = ln[

F +b
1
dV ef f /dV GS +
dF/dV GS]1
V ef f
F2

(2.12)

Several conclusions can be drawn from this equation. First, as already illustrated
in Fig 5.6, it should be noted that in sharp contrast with a conventional MOSFET,
the subthreshold swing is a function of VGS. This means that the subthreshold region
does not appear as a straight line when IDS-VGS is plotted on a log-lin scale, and
the swing does not have one unique value [24]. Swing is smallest at the lowest VGS,
and increases as VGS increases. Fig.5.7 shows a comparison of the IDSVGS curves
for a typical conventional MOSFET, and for a typical Tunnel FET.
Due to the changing values of swing along the IDS-VGS curve, it is useful to define
two different types of swing, point swing (Spt) and average swing (Savg). These are
illustrated in Fig. 5.7. Point swing is the smallest value of the subthreshold swing
anywhere on the IDS-VGS curve, typically found right as the device leaves the offstate and tunneling current starts to flow. Average swing is taken from the point
where the device starts to turn on, up to threshold, often defined using the constant
current technique. Average swing is the more useful value for circuit designers,
though in order to truly utilize the average slope as shown in Fig.5.7, the gate work
function would need to be adjusted in order for the turn-on point to fall right at VGS
=0V

Chapter 2. DEVICE DESCRIPTION

24

Fig. 2.15: Dependence of the Tunnel FET subthreshold slope on gate voltage for
different dielectric constants

Fig. 2.16: comparison of IDS-VGS for a conventional MOSFET and a Tunnel FET

Fig. 2.17: Visual definitions of point swing, taken at the steepest point of the IDSVGS curve, and average swing, taken as the average from turn-on to
threshold.

Chapter 2. DEVICE DESCRIPTION

2.6.6

25

TUNNEL FET TEMPERATURE CHARACTERIS

The temperature dependence [4] of silicon Tunnel FETs with an SiO2 gate dielectric has been reported in and. Simulations of Tunnel FETs with a high-k dielectric
show the same general trends: the off-current, caused by the generation of carriers in
a reverse-biased junction, increases with temperature, while the on-current, coming
from band-to-band tunneling, changes only slightly, as shown in Fig.5.8. The inset
of Fig. 5.8 shows that the subthreshold swing of the Tunnel FET for fixed values of
VGS is nearly constant as temperature increases, unlike that of a MOSFET, which
degrades proportionally to the increase in temperature, as can be seen in Eq. 5.
Due to rising offcurrent, the average subthreshold swing of Tunnel FETs will significantly degrade with increasing temperature, but beyond the leakage level, the current
characteristics remain nearly unchanged.

Fig. 2.18: Simulated IDS-VGS characteristics for various temperatures for a doublegate Tunnel FET with dielectric = 21. VDS = 1 V. As temperature
increases, Ioff increases, but Ion changes very little. Inset: Subthreshold
swing at specific VGS values, vs. temperature in Kelvin. The swing is
only slightly affected by changes in temperature.
The use of a high-k dielectric rather than SiO2 leads to a decrease in the threshold
voltage shift caused by temperature. This is to be expected with the constant current
method of VT extraction, since with a higher dielectric constant, VT falls on a
steeper part [13] of the IDS-VGS curve. While VT/ T is in the range of 1-2 mV/K
for Si/SiO2 Tunnel FETs and MOSFETs, we find that VT/T is 0.2-0.3 mV/K for
Tunnel FETs with a gate dielectric constant of 21. Although subthreshold swing
doesnt degrade with increased temperature, when taken at a fixed value of VGS, it
must be kept in mind that circuit designers dont care about swing at a fixed value of
gate voltage. They would be more interested in average swing, taken from turn-on

Chapter 2. DEVICE DESCRIPTION

26

up to threshold. Since an increase in temperature has a strong effect on Ioff, as seen


in Fig.5.8, the steepest part of the curve is lost as temperature goes up, and so Savg
will be significantly degraded.

CHAPTER

DEVICE SIMULATION

3.1

SILVACOS ATLAS DEVICE SIMULATOR

ATLAS is a physically-based two and three dimensional device simulator [1]. It


predicts the electrical behaviour of specified semiconductor structures and provides
insight into the internal physical mechanisms associated with device operation.
The primary method of interfacing with the ATLAS simulator is using Silvacos
Deckbuild operating environment. Majority of the work in this thesis uses Deckbuild
to create the device to run in ATLAS so that will be the main focus of explanation.

3.1.1

ATLAS INPUTS AND OUTPUTS

ATLAS produces three types of output files: 1.Run-time output file: This file gives
progress and error and warning messages as the simulation proceeds. 2.Log file: This
file stores all terminal voltages and current from the device analysis. 3.Output file:
This file is the solution file, which stores 2D and 3D data relating to the values of
solution variables within the device at a given bias point [1].

3.1.2

MODES OF OPERATION

All simulations in this thesis were run using Deckbuild to provide the device structure
information to the device simulator ATLAS [1]. ATLAS has the ability to run in
several different modes that are with Deckbuild including Interactive Mode, Batch
Mode, No Windows Batch Mode and inside Deckbuild. Inside Deckbuild is the

Chapter 3. DEVICE SIMULATION

28

recommended method by Silvaco and will be the only way ATLAS is run during
this thesis. Each time the designer wants to run ATLAS inside Deckbuild the first
programming line should be:
go atlas
This input will start ATLAS simulator and allow it to input the rest of the
conditions stated in the code in Deckbuild.

3.1.3

ORDER OF COMMANDS

The order in which commands are entered into Deckbuild are very important to
ensure that ATLAS runs the program correctly. ATLAS needs to have the commands
in the proper order or it will give an error message. Silvaco breaks the commands
into five groups and each group will have several statements in that group. The
statements in each group in most cases must be run in order. Fig.4.2 shows the
groups and the order in which they should be inputted into Deckbuild [1].

GROUPS

STATEMENTS

Structure Specification

Mesh, Region, Electrode, Doping

Material Model Specification

Materials, Models, Contacts, Interface

Numerical Method Selection

Method

Solution Specification

Log, Solve, Load, Save

Result Analysis

Extract, Tonyplot

This thesis will use ATLAS five command groups to describe how to use ATLAS
to build and simulate a DGTFET.
Structure Specification
Structures of devices to be simulated are entered in plain text into the Deckbuild
input deck. To properly build a device in Deckbuild a designer must define several key
parameters to get an accurate result. The key parameters in the structure command
group include the following; a two or three dimensional grid, called the mesh, the
mesh must be divided into regions, electrode locations and materials must be defined,
doping levels and dopants must be defined. When programming in Deckbuild the
is used to indicate that the line is only a programmers note and not part of the
program [1].
The mesh is the two or three dimensional grid used as the frame work to build
your device. In this thesis all the device designs will be using a two dimensional grid.

Chapter 3. DEVICE SIMULATION

29

The mesh statement will define the boundaries of the device you are building and
the resolution of detail. The first mesh command must be the mesh space multiplier
Command.
meshspace.mult =< value >
This command will tell ATLAS the scaling factor of the mesh. The mesh will be
less dense for a large number and denser for a smaller number. The value for this
is normally set to equal 1. Fig. 4.3 shows an example of a mesh with a space.mult
value of 5 compared to a mesh with a value of 1.
The next step to defining the mesh is to specify the actual grid make up. Mesh
statements are entered in as vertical and horizontal lines in microns and as distance
from the center line. ATLAS will automatically adjust the grids to represent the
desired resolution the user has entered. ATLAS divides the grid using a triangle
format. The user can use a higher resolution over areas of the device that the user
wants more detail. Typically a high grid resolution is used at junctions and material
boundaries. This can be seen in Fig.4.4 which shows the ATLAS mesh and the mesh
statements of a DGTFET. Notice the tighter grid along the junction in the middle
of the device.
After the designer has defined the device mesh, they will next have to define the
regions of the device. The regions will be used to assign materials and properties to
the device. The regions must be defined along the mesh lines and the statements
will be similar to those used for the mesh states. ATLAS allows the user to define
up to 200 different regions for one device. If the designer overlaps any of the two
regions ATLAS will assign the material type to the last region that was defined. The
entire two dimensional mesh area must be defined into regions or ATLAS will not run
successfully. The designer will list the material type when defining a region but to
define the material properties of the material type the design must wait until second
command group. Regions can be defined using cylindrical coordinates but this type
of region definition is not used in this research so it will not be addressed. Fig. 4.4
shows also the ATLAS regions for a DGTFET.
For ATLAS to find the electrical properties of the structure the designer must
define the location of the electrodes. The designer must specify the electrode name
and where it is located. ATLAS requires a minimum of one electrode and has a
maximum limit of 50 electrodes for one device. The electrodes can be specified as
a certain material or you can leave them undefined and ATLAS will use an ideal
conductor.

Chapter 3. DEVICE SIMULATION

Fig. 3.1: ATLAS Inputs and Outputs

Fig. 3.2: Comparison of mesh grids when using a multiplier of 5 and 1

Fig. 3.3: ATLAS Mesh and Region Boundaries for a DGTFET

30

Chapter 3. DEVICE SIMULATION

31

The next action, doping, is one of the most important actions a designer does
to affect the electrical properties of the structure they are designing. Silvaco allow
the designer to specify the type of dopant and the concentration. It also allows the
designer to specify the distribution of the doping material. ATLAS has the ability to
distribute the dopants in a uniform or Gaussian profile. The uniform doping profile
has an easy set of commands to dope the material exactly how the design wishes
it. Fig. 4.5 shows the doping concentration of a DGTFET; notice how the impurity
concentrations change in the junction region

Fig. 3.4: ATLAS Doping Profile of DGTFET

Material Models Specification


Once the designer has defined the structure and the geometry of the device being
designed they can now change the default material properties and choose which
models ATLAS will use to solve the devices electrical characteristics. The first of all
properties investigated will be the contact command. This command is used to tell
ATLAS how to treat the electrode. In the default condition an electrode in contact
is assumed to be ohmic. If the designer wants the electrode to be treated like a
Sckottky contact the design must use the workfunction.
An example of this would be: contact name=gate workfunction=4.8 This command would treat the contact as Sckottky contact and set the contact named gate to
4.8eV. The designer can also use the contact command to change an electrode from
being voltage controlled and make it current controlled.
An example of this would be: contact name=drain current
This would make the contact named drain a current controlled contact. ATLAS
also has the ability to float contacts, short two contacts together, and make an open
circuit contact.

Chapter 3. DEVICE SIMULATION

32

Since none of these features were used in this research these are not discussed in
detail. The next step in the ATLAS design process is to designate material properties
for the regions that are being used. ATLAS has an extensive library of different
elements, compounds and alloys with their properties already defined. Silvaco allows
the designer to edit these allows or create completely new materials. Some of the
properties defined are bandgaps, mobility and absorption coefficients. An example
of a way to use the material statement to improve the simulation is as follows:
Material Material=Silicon EG300=1.12 mun=1100 This command would set the
bandgap and low field electron mobility for all the silicon in the device. The next
statement to investigate is the models statement. ATLAS has over seventy models
that a designer can choose to use to improve the accuracy of the structure they are
trying to simulate. These models would change the parameters of the device using
the following command statements: models, mobility, impact, and material. Fig. 4.6
shows an example of some of the mobility models available.

Fig. 3.5: Some of the mobility models available in ATLAS

Numerical Method Selection


ATLAS allows several different methods for calculating the solution for semiconductor
device problems. For each model type there are various types of solution techniques
such as Newton and Gummel [1]. The designer should look and see what type
of method the model they are using. Using the wrong method can lead to nonconvergence or incorrect results.

Chapter 3. DEVICE SIMULATION

33

Solution Specifications
ATLAS will calculate AC, DC, small signal and transient solutions. Obtaining a
solution is similar to setting up a test device. Once the command has been made
the user will typically save the results using a log or save command. An example of
solving a DC solution is given below:
solve vcathode=1.0
This will solves a single bias point with 1 volt on the cathode. The designer can
also solve a sweeping bias using the following commands:
solve vcathode=0
solve vanode=-5 vfinal=5 vstep=0.1 name=anode
This will solve the circuit parameters by holding cathode voltage at 0 and sweeping
the anode voltage from -5 to 5 with 0.1 voltage steps. If no solve voltage is designated
Silvaco will put a default of 0. The results can be saved to a log file by using the
following command:
log outfile=simplesidiode-iv.log
This will save a log output file of the results from the voltage sweep in them.
Results Analysis
The primary method when working with ATLAS to view the results of a simulation
is using Tonyplot. Tonyplot is viewing program for ATLAS that allows the designer
to view the structure and log files that are created by ATLAS. The structure files
allow you to view the mesh diagram, doping concentrations, current densities, and
other parameters. The log files allow you to view the results of ATLASs electrical
analysis in a graph format. It can show both log and linear scaling. It can also
produce cylindrical graphs. Tonyplot [1] has the ability to do cutlines to look at a
specific slice of the device and see what is electrical occurring at the slice point or
plane.
All simulations were done in Silvacos ATLAS, version 5.16.3.R, which uses a
nonlocal Hurkx band-to-band tunneling model [1]. The currently used nonlocal model
works by calculating the tunnelling probability from the energy-band diagrams across
the device. The simulations use a very fine mesh across the region where the tunneling
takes place, from which energy band profiles and the energies for which band-to-band
tunneling is permitted, are determined.
All simulations carried out in Silvacos ATLAS are 2-D, and it is informative
to look at vertical cross sections of the energy bands of the Tunnel FET, as well as
contour plots in two dimensions, in order to understand the functioning of the device.

Chapter 3. DEVICE SIMULATION

3.2

34

Comparison between MOSFET and DGTFET Transfer


Characteristics

It can be observed from the following fig. that, the ON-current does not increase
merely proportionally to the increase in the gate capacitance, as it would for a MOSFET. A simplified MOSFET 2-D structure has been designed for numerical simulation in order to show the difference between the two. For Tunnel FETs, as we saw in,
the improved coupling between the gate and the tunneling barrier has an exponential
effect rather than a linear one. The ON-current of a Tunnel FET depends on the
width of the energy barrier between the intrinsic and p+ regions, and the current
increases exponentially with a reduction in this barrier width.

Fig. 3.6: DGTFET Transfer Characteristics for various Gate Dielectric

Fig. 3.7: Characteristics of a simplified single-gate NMOSFET for various gate dielectrics.

Chapter 3. DEVICE SIMULATION

3.3

35

DGTFET PARAMETERS OPTIMIZATION

Before investigating the unique properties of Tunnel FETs or looking in detail at


their behaviour, it is important to carefully choose all device parameters such that
characteristics are optimized [3], and to show why each choice was made as it was.
In this chapter, Tunnel FET optimization is explored, considering the following parameters:
1.Dielectric Constant of Gate Dielectric, ox
2.Silicon Body Thickness, tsi
3.Channel Length, L
4.Gate Work Function,
5.Gate Dielectric Thickness, tox

3.3.1

DIELECTRIC CONSTANT OF GATE DIELECTRIC

An improved on-current and decreased sub-threshold swing can be obtained by the


careful choice of a gate dielectric. As shown in Fig.6.1, current increases as the gate
dielectric constant increases. Here, Si3N4 and two high-k dielectrics with dielectric
constants of 21 and 29 are compared with SiO2, all with a physical thickness of 3
nm. In addition to improved Ion, both the point and average sub-threshold swing
improve as the result of the better gate coupling given by a high-k dielectric [6]. The
off-current is less than 1 fA for all materials.
As shown in Fig.6.2, trans-conductance (gm) also increases as gate dielectric
constant increases. The off-current is less than 1fA for all materials.
The above statements are in full agreement to the equation of band-to-band
tunnelling current.

4 2m Eg 23
)
(3.1)
IBT B Tt exp(
3h( + Eg)
where
=

tsi tox
2ox

(3.2)

These two figures Fig. 6.1 and 6.2 show that the optimized value for dielectric
constant of gate material can be chosen as 29.

Chapter 3. DEVICE SIMULATION

36

Fig. 3.8: DGTFET Transfer Characteristics for various Gate Dielectric

Fig. 3.9: DGTFET Trans-conductance (gm) vs VGS Curve for various Dielectrics
(VDS=1V, L=50 nm, tox=3 nm, tsi=10 nm)

Chapter 3. DEVICE SIMULATION

3.3.2

37

THICKNESS OF SILICON BODY

Tunnel FETS are sensitive to the thickness of silicon body, tsi , which influences the
shape of its IDS-VGS curve as shown in Fig.6.3

Fig. 3.10: DGTFET Transfer Characteristics for various tsi

Fig. 3.11: DGTFET Trans-conductance (gm) vs VGS Curve for various tsi
Several trends can be seen in this figure. First, the off-currents are practically
independent of the thickness. As the film gets thinner than 7 nm, on-current starts
to drop possibly due to the reduced cross-sectional area available for current flow.
Fig. 6.4 showing gm vs VGS curve shows that among all these values of silicon
body thickness maximum trans-conductance is obtained for silicon body thickness
equal to 15 nm and thus is the optimized value of tsi for DGTFET.

Chapter 3. DEVICE SIMULATION

3.3.3

38

CHANNEL LENGTH

A detailed study of the length scaling [25] of Tunnel FETs is conducted, in which
all other parameters stayed constant. It is shown that Tunnel FETs ON-current is
immune to the effects of length scaling as shown in Fig.6.5 . But Fig.6.6 shows that
the trans-conductance value is maximized for channel length of 70 nm.

Fig. 3.12: DGTFET Transfer Characteristics for various channel lengths, L

Fig. 3.13: DGTFET Trans-conductance (gm) vs VGS Curve for various L (Other
parameters are same as for Fig.6.1)
Thus channel length is optimized to length of 70 nm.

3.3.4

GATE WORK FUNCTION

When the impact of the work function of the gate, on the ION in a DMG-DGTFET
is analyzed, it is observed that with the reduction in , the band overlap increases,

Chapter 3. DEVICE SIMULATION

39

Fig. 3.14: DGTFET Transfer Characteristics for various gate work function

Fig. 3.15: DGTFET Trans-conductance (gm) vs VGS Curve for various gate work
function

Chapter 3. DEVICE SIMULATION

40

and the tunneling width decreases, leading to a significant increase in the tunneling
probability and hence the ON-current is increased as shown in Fig.6.7.
Since, in general, DGTFET suffers from a low ION and high VT , it is desirable
to adjust the device parameters to obtain a maximum ION and a minimum VT .
Therefore, we choose to be the lowest possible value, i.e., 4.4 eV.

3.3.5

GATE DI-ELECTRIC THICKNESS

Tunnel FETs show high sensitivity to changes in gate dielectric thickness. The gate
leakage increases exponentially as the oxide thickness is reduced. This limits the
downscaling [22] thickness to about 3.4 nm 3.5 nm. But to further decrease the
effective oxide thickness alternative high dielectric constant material can be used.
On the other hand, a thin gate oxide reduces the short channel effect and improves
the driving capabilities of a MOS transistor [12].
However a trade off between this benefits and gate leakage is necessary. So optimum value of gate dielectric thickness is chosen as 3 nm as Fig.6.10 shows maximized
value of ON-current and gm for this value of thickness.

Fig. 3.16: DGTFET Transfer Characteristics for various gate dielectric thickness

3.4
3.4.1

RESULTS
STRUCTURE AND PARAMETERS

The following table shows the parameters of the proposed device, Dual Gate TFET
with their optimized values for better performance in terms of low sub-threshold
swing and high ON-current.

Chapter 3. DEVICE SIMULATION

41

PARAMETER
Silicon Body Thickness

15 nm

Gate Dielectric Thickness

3 nm

Gate Dielectric Constant

29

Drain Doping(N+)

5 1018 /cm3

Source Doping(P+)
Intrinsic Region(N)
Channel Length

1 1020 /cm3
1 1017 /cm3

Gate Work function

70 nm

4.4 eV

The following figure shows the optimized structure of DGTFET with ON-current
as high as 0.13 mA for gate voltage of 1.8V and an improved average sub-threshold
swing of 57 mV/dec.

3.4.2

ON-CURRENT OF DGTFET

The following figure shows that the device, DGTFET proposed by us has better
performance in terms of high ON-current. ON-current value for optimized device is
0.13mA which is higher than its value, 0.09mA for the device before optimization.

3.4.3

TRANS-CONDUCTANCE VS VGS CURVE

The following figure shows considerable improvement in terms of trans-conductance


of DGTFET. Before optimization of parameters its value was 1.25e-6 A/V which is
raised to 2.1e-6 A/V by optimizing the already discussed parameters.

3.4.4

ENERGY BAND DIAGRAMS

The following two figures show that the optimized DGTFET has better probability of
band-to-band tunneling as compared to that before optimization due to the reduction
in barrier width after optimization.

3.4.5

ELECTRIC FIELD

Looking first at the x direction component of the electric field across a device which
is ON, we see that the electric field is close to zero nearly everywhere. Between
the intrinsic and p+ regions, where the tunnelling takes place, we see a maximum
positive field throughout the depth of the device.

Chapter 3. DEVICE SIMULATION

42

Fig. 3.17: DGTFET Trans-conductance (gm) vs VGS Curve for various gate dielectric thickness

Fig. 3.18: Optimized structure of DGTFET

Fig. 3.19: Comparison of ON-Current for optimized DGTFET and DGTFET before optimization

Chapter 3. DEVICE SIMULATION

43

Fig. 3.20: Comparison of transconductance vs VGS curve for optimized DGTFET


and DGTFET before optimization

Fig. 3.21: Energy Band Diagram of DGTFET before Optimization

Fig. 3.22: Energy Band Diagram of DGTFET after Optimization

Chapter 3. DEVICE SIMULATION

Fig. 3.23: Contour plot of Electric Field across DGTFET before optimization

Fig. 3.24: Contour plot of Electric Field across DGTFET after optimization

44

Chapter 3. DEVICE SIMULATION

3.4.6

45

POTENTIAL

In the potential contour plot for this same device in the same state , we see that the
potential drops abruptly at the tunnel junction, and once again, this holds true for
the entire device depth, not just at the surface.

Fig. 3.25: Contour plot of potential across DGTFET before optimization

Fig. 3.26: Contour plot of potential across DGTFET after optimization

3.4.7

CURRENT FLOWLINES

In the diagrams of current flow lines, shown at the threshold voltage, it is clear that
the current does not stay close to the gate dielectric as in a MOSFET. As the electrons
move from right to left (source to drain) in the Tunnel FET, they move parallel to the
interface through most of the source, then move away from the dielectric interface at
about the location of the tunnel junction and, then, attracted by the positive voltage
on the gate, flow closer to the interface before spreading back out and passing through

Chapter 3. DEVICE SIMULATION

46

the drain parallel to the interface, as they were in the source (electrical contacts are
on the sides of the source and drain).

Fig. 3.27: Contour plot of current flowlines in DGTFET before optimization

Fig. 3.28: Contour plot of current flowlines in DGTFET after optimization

CHAPTER

CONCLUSION

Numerical simulations have proven to be an effective means to investigate Tunnel


FET behavior and the dependence of its static characteristics on changes in dimensions, doping, and other parameters.
The work presented here can be useful to other researchers who will be designing
and fabricating Tunnel FETs, and developing analytical and compact models for
these devices.The main accomplishments of this work can be summarized as follows:
The optimization of the static characteristics of Tunnel FETs by the variation
of gate structure (single or double), source, drain, and intrinsic region doping levels,
gate dielectric material, and silicon body thickness was carried out.
The proposed device had a double gate, a high source doping and lower drain
doping to suppress ambipolar behavior, a high-k dielectric of 29, silicon body thickness of 15 nm ,work function of 4.4 eV, oxide thickness of 3 nm and channel length
of 70 nm.
1.Dielectric permittivity constant was investigated and by increasing its value there
was a significant change in on current and trans-conductance.
2.The optimization of work function shows that the increasing value of work function
decreases the threshold voltage significantly.
3.Channel length variation doesnt show much change in Ion current but by increasing
channel length breakdown improves significantly.
4.Oxide thickness reduction increases leakage current so in our proposed device we
had not reduce its value .

Chapter 4. CONCLUSION

48

Our proposed Tunnel FET showed improved characteristics including higher ONcurrent, .higher trans-conductance and a lower sub-threshold swing after the modifications in the design of previously proposed device.
The Tunnel FETs promising behaviour makes it a strong candidate to complement
or replace MOSFET technology, particularly for low power applications.

4.1

FUTURE SCOPE

Since the beginning of this thesis work in early 2005, the progress made with Tunnel
FETs has come a long way. Referring back to the Recent research relevant to the
problem in chapter 1, it can be seen that the majority of Tunnel FET work has been
done in the past few years. but there is still much progress to be made in terms of
optimization to achieve superior device characteristics.
The biggest future challenge is to successfully design and fabricate fully-optimized
Tunnel FETs of both n-type and p-type, that show low off-currents beyond what is
possible for conventional MOSFETs, high on-currents, and average sub-threshold
swings of less than 60 mV/decade at room temperature.
Further work will also be necessary in order to develop accurate analytical and
compact models for Tunnel FETs. Although some work has been done in these areas,
the theoretical framework which will allow experimental data to be fitted has not yet
been developed. More calibration and tuning of the models is required, and will
become possible once more experimental data is available.
Finally, one last important point is the current state of device simulators. For
novel devices such as Tunnel FETs, it would be extremely advantageous to have a
close interaction between the developers of the simulation tools, and the researchers
producing the experimental data. Then it will become possible for the simulators
to go beyond predicting trends, and give accurate estimations of on-current and
other important device characteristics. I am optimistic that these devices, or some
variation upon them, will bring lower power consumption and better energy-efficiency
to computers, appliances, and devices everywhere.

References

[1] Atlas users manual. May 2006.


[2] Donald A.Neame. Semiconductor Physics and Devices. Mc Graw Hill, 2003.
[3] T. Baba. april 1992.
[4] M. Born and K. Bhuwalka. tunnel fet: A cmos device for high temperature
applications. Microelectron devices, pages 124127, 2006.
[5] Kathy Boucart and Adrian M. Ionescu. Threshold voltage in tunnel fets: physical definition, extraction, scaling and impact on ic design. IEEE, pages 299302,
2007.
[6] Kathy Boucart and Adrian Mihai Ionescu. Double-gate tunnel fet with high-k
gate dielectric. IEEE Transactions on Electron Devices, 54(7), July 2010.
[7] Anupama Bowonder. low power band to bandd tunnel transistors. Electrical
Engg and Computer Sciences University of California, (154), Dec 2010.
[8] L. T. Yang C. Shen and E. H. Toh.
[9] Anurag Chaudhry and M. jagadesh Kumar, Sept.
[10] E. J. Tan et al. Observation of tunneling fet operation in mosfet. IEEE Electronic
Device Letters, 29(902), August 2008.
[11] Ben G.Streetman. Solid State Electronic Devices. PHI Learning Pvt.Ltd, 2009.

References

50

[12] G. Hurkx and D. Klaassen. A new recombination model for device simulation
including tunneling. volume 39, pages 331338, Feb 1992.
[13] G. Kawamoto J. Quinn and B.McCombe. Sub band spectroscopy by surface
channel tunneling. 73:190196, May 1978.
[14] y. M. Lin J.Appenzeller and P. Avouris. Band to band tunneling in carbon nano
tube field effect transistors. Electron. Letter, 93(19):19680511968054, Nov
2004.
[15] J.Koga and A. Toriumi. Three terminal silicon surface junction tunneling device
for room temperature operation. Electron. Letter, 20(10):529531, Oct 1999.
[16] Saptarshi Das Joshua T. Smith and Joerg Appenzeller. Broken-gap tunnel mosfet: A constant-slope sub-60-mv/decade transistor. IEEE Electron Device Letters, 32(10), Oct 2011.
[17] J. Schulzze K. Bhuwalka and I. Eisele. performance enhancement of vertical
tunnel field effect transistor with sige in the delta p+ layer. pages 909917, May
2005.
[18] Siyuranga O. Koswatta and Mark S. Lundstrom. Influence on phonon scattering
on the performance of pin band to band tunneling transistors. 2007.
[19] Siyuranga O. Koswatta and Mark S. Lundstrom. Performance comparison between pin tunneling transistors and conventional mosfets. 2008.
[20] Anne S. Verhulst Kuohsing Kao and W. G. Vandenberghe. Direct and indirect
band to band tunneling in silicon based tfets. pages 110, 2011.
[21] J. McPherson and A. Shanware. Thermo chemical description of dielectric breakdown in high dielectric constant material. volume 82, pages 21212123, Mar
2003.
[22] T. Nirschn and J. Einfeld. Scaling properties of tfet: Devices and circuits.
volume 50, pages 4451, Jan 2006.
[23] M. Oswald P.F. Wang and C. Stepper. Complementary tunneling transistor for
low power application. volume 48, pages 22812286, Dec 2004.
[24] W. Reddick and G. Amaranatunga. Silicon suface tunnel transistor. IEEE trans.
on semiconductor devices, 67(4):494496, July 1995.

References

51

[25] G. Venkateshwar Reddy and M. Jagadesh kumar. new dual material double gate
nano scale soi mosfet 2-d analytical modelling and simulation. volume 4, pages
260268, 2005 2005.
[26] Brain Doyle Robert Chau and Jack Kavalieros. Advanced depleted substrate
tranistor: Single gate, double gate and tri gate, 2002.
[27] Sneh Saurabh and M. Jagadesh Kumar. Sep 2010.
[28] F. Valestra and M. Benachir. Double gate soi transistor with volume inversion.
Number 9, pages 410412, September 1987.
[29] Verhulst and A. Shanware. Tunnel fet:shortening of gate length. volume 86,
pages 212215, Mar 2007.
[30] A. S. Verhulst and W. G. Vandenberghe. Silicon based tunnel fet for low power
nanoelectronics. IEEE, 2011.
[31] Anne S. Verhulst and W. G. Vandenderghe.
[32] C. Fink W. Hansch and I. Eisele. A vertical mos gated esaki tunneling transistor
in silicon. IEEE trans. on thin solid films, 369(1), july 2000.
[33] M. Born Zhang and T. Sulima. gated pn diode: subthreshold swing less than
60mv/dec. IEEE Transactions on electron devices, 45(4), April 2006.
[34] Q. Zhang and W. Zhao. Analytic expression and approach for low sub threshold
swing tunnel transistors. Electronics Letters, pages 161162, Jun 2005.

APPENDIX

DECKBUILD CODING FOR ATLAS

Given in the following appendix is the coding used to do the simulations that are
performed during this thesis

A.1

Code for ON-current comparison between DGTFET before


optimization and after optimization

go atlas
mesh space.mult=1.0
x.mesh loc=0e-3 spac=2e-3
x.mesh loc=1e-3 spac=5e-4
x.mesh loc=51e-3 spac=2e-3
x.mesh loc=101e-3 spac=5e-4
x.mesh loc=126e-3 spac=2e-3
x.mesh loc=151e-3 spac=5e-4
x.mesh loc=201e-3 spac=2e-3
x.mesh loc=251e-3 spac=5e-4
x.mesh loc=252e-3 spac=2e-3
y.mesh loc=0.0 spac=2e-3
y.mesh loc=1e-3 spac=5e-4
y.mesh loc=2.5e-3 spac=2e-3
y.mesh loc=4e-3 spac=5e-4
y.mesh loc=9e-3 spac=2e-3

Appendix A. DECKBUILD CODING FOR ATLAS

53

y.mesh loc=14e-3 spac=5e-4


y.mesh loc=15.5e-3 spac=2e-4
y.mesh loc=17e-3 spac=5e-4
y.mesh loc=18e-3 spac=2e-3
region num=1 silicon x.min=1e-3 x.max=251e-3 y.min=4e-3 y.max=14e-3
region num=2 oxide x.min=1e-3 x.max=251e-3 y.min=1e-3 y.max=4e-3
region num=3 oxide x.min=1e-3 x.max=251e-3 y.min=14e-3 y.max=17e-3
region num=4 oxide x.min=0e-3 x.max=101e-3 y.min=0 y.max=1e-3
region num=5 oxide x.min=0 x.max=101e-3 y.min=17e-3 y.max=18e-3
region num=6 oxide x.min=151e-3 x.max=252e-3 y.min=0e-3 y.max=1e-3
region num=7 oxide x.min=151e-3 x.max=252e-3 y.min=17e-3 y.max=18e-3
region num=8 oxide x.min=0 x.max=1e-3 y.min=1e-3 y.max=17e-3
region num=9 oxide x.min=251e-3 x.max=252e-3 y.min=1e-3 y.max=17e-3
region num=10 oxide x.min=101e-3 x.max=151e-3 y.min=0e-3 y.max=1e-3
region num=11 oxide x.min=101e-3 x.max=151e-3 y.min=17e-3 y.max=18e-3
electr name=drain x.min=0 x.max=1e-3 y.min=1e-3 y.max=17e-3
electr name=source x.min=251e-3 x.max=252e-3 y.min=1e-3 y.max=17e-3
electr name=gate x.min=101e-3 x.max=151e-3 y.min=0e-3 y.max=1e-3
electr name=gate x.min=101e-3 x.max=151e-3 y.min=17e-3 y.max=18e-3
doping uniform n.type conc=5e18 x.min=1e-3 x.max=101e-3 y.min=4e-3 y.max=14e3
doping uniform n.type conc=1e17 x.min=101e-3 x.max=151e-3 y.min=4e-3 y.max=14e3
doping uniform p.type conc=1e20 x.min=151e-3 x.max=251e-3 y.min=4e-3 y.max=14e3
material material=silicon EG300=1.12
material material=oxide permittivity=29
save outf=DG.str
tonyplot DG.str
contact name=gate workf=4.5
models mos print
models cvt bbt.kl boltzman print temperature=300
models bbt.kl bgn.klassen trap.tunnel
method newton gummel
solve init
log outfile=simulated.log
solve vdrain=1.0

Appendix A. DECKBUILD CODING FOR ATLAS

solve vgate=-0.5 vstep=0.5 vfinal=10 name=gate


log off
mesh space.mult=1.0
x.mesh loc=0e-3 spac=2e-3
x.mesh loc=1e-3 spac=5e-4
x.mesh loc=46e-3 spac=2e-3
x.mesh loc=91e-3 spac=5e-4
x.mesh loc=126e-3 spac=2e-3
x.mesh loc=161e-3 spac=5e-4
x.mesh loc=206e-3 spac=2e-3
x.mesh loc=251e-3 spac=5e-4
x.mesh loc=252e-3 spac=2e-3
y.mesh loc=0.0 spac=2e-3
y.mesh loc=1e-3 spac=5e-4
y.mesh loc=2.5e-3 spac=2e-3
y.mesh loc=4e-3 spac=5e-4
y.mesh loc=11.5e-3 spac=2e-3
y.mesh loc=19e-3 spac=5e-4
y.mesh loc=20.5e-3 spac=2e-4
y.mesh loc=22e-3 spac=5e-4
y.mesh loc=23e-3 spac=2e-3
region num=1 silicon x.min=1e-3 x.max=251e-3 y.min=4e-3 y.max=19e-3
region num=2 oxide x.min=1e-3 x.max=251e-3 y.min=1e-3 y.max=4e-3
region num=3 oxide x.min=1e-3 x.max=251e-3 y.min=19e-3 y.max=22e-3
region num=4 oxide x.min=0e-3 x.max=91e-3 y.min=0 y.max=1e-3
region num=5 oxide x.min=0 x.max=91e-3 y.min=22e-3 y.max=23e-3
region num=6 oxide x.min=161e-3 x.max=252e-3 y.min=0e-3 y.max=1e-3
region num=7 oxide x.min=161e-3 x.max=252e-3 y.min=22e-3 y.max=23e-3
region num=8 oxide x.min=0 x.max=1e-3 y.min=1e-3 y.max=22e-3
region num=9 oxide x.min=251e-3 x.max=252e-3 y.min=1e-3 y.max=22e-3
region num=10 oxide x.min=91e-3 x.max=161e-3 y.min=0e-3 y.max=1e-3
region num=11 oxide x.min=91e-3 x.max=161e-3 y.min=22e-3 y.max=23e-3
electr name=drain x.min=0 x.max=1e-3 y.min=1e-3 y.max=22e-3
electr name=source x.min=251e-3 x.max=252e-3 y.min=1e-3 y.max=22e-3
electr name=gate x.min=91e-3 x.max=161e-3 y.min=0e-3 y.max=1e-3
electr name=gate x.min=91e-3 x.max=161e-3 y.min=22e-3 y.max=23e-3

54

Appendix A. DECKBUILD CODING FOR ATLAS

55

doping uniform n.type conc=5e18 x.min=1e-3 x.max=91e-3 y.min=4e-3 y.max=19e3


doping uniform n.type conc=1e17 x.min=91e-3 x.max=161e-3 y.min=4e-3 y.max=19e3
doping uniform p.type conc=5e21 x.min=161e-3 x.max=251e-3 y.min=4e-3 y.max=19e3
material material=silicon EG300=1.12
material material=oxide permittivity=29
save outf=DG.str
tonyplot DG.str
contact name=gate workf=4.4
models mos print
models cvt bbt.kl boltzman print temperature=300
models bbt.kl bgn.klassen trap.tunnel
method newton gummel
solve init
log outfile=optimized.log
solve vdrain=1.0
solve vgate=-0.5 vstep=0.5 vfinal=10 name=gate
tonyplot -overlay simulated.log optimized.log

A.2

Code for contour plots comparison between DGTFET before


optimization and after optimization

go atlas
mesh space.mult=1.0
x.mesh loc=0e-3 spac=2e-3
x.mesh loc=1e-3 spac=5e-4
x.mesh loc=51e-3 spac=2e-3
x.mesh loc=101e-3 spac=5e-4
x.mesh loc=126e-3 spac=2e-3
x.mesh loc=151e-3 spac=5e-4
x.mesh loc=201e-3 spac=2e-3
x.mesh loc=251e-3 spac=5e-4
x.mesh loc=252e-3 spac=2e-3
y.mesh loc=0.0 spac=2e-3
y.mesh loc=1e-3 spac=5e-4

Appendix A. DECKBUILD CODING FOR ATLAS

56

y.mesh loc=2.5e-3 spac=2e-3


y.mesh loc=4e-3 spac=5e-4
y.mesh loc=9e-3 spac=2e-3
y.mesh loc=14e-3 spac=5e-4
y.mesh loc=15.5e-3 spac=2e-4
y.mesh loc=17e-3 spac=5e-4
y.mesh loc=18e-3 spac=2e-3
region num=1 silicon x.min=1e-3 x.max=251e-3 y.min=4e-3 y.max=14e-3
region num=2 oxide x.min=1e-3 x.max=251e-3 y.min=1e-3 y.max=4e-3
region num=3 oxide x.min=1e-3 x.max=251e-3 y.min=14e-3 y.max=17e-3
region num=4 oxide x.min=0e-3 x.max=101e-3 y.min=0 y.max=1e-3
region num=5 oxide x.min=0 x.max=101e-3 y.min=17e-3 y.max=18e-3
region num=6 oxide x.min=151e-3 x.max=252e-3 y.min=0e-3 y.max=1e-3
region num=7 oxide x.min=151e-3 x.max=252e-3 y.min=17e-3 y.max=18e-3
region num=8 oxide x.min=0 x.max=1e-3 y.min=1e-3 y.max=17e-3
region num=9 oxide x.min=251e-3 x.max=252e-3 y.min=1e-3 y.max=17e-3
region num=10 oxide x.min=101e-3 x.max=151e-3 y.min=0e-3 y.max=1e-3
region num=11 oxide x.min=101e-3 x.max=151e-3 y.min=17e-3 y.max=18e-3
electr name=drain x.min=0 x.max=1e-3 y.min=1e-3 y.max=17e-3
electr name=source x.min=251e-3 x.max=252e-3 y.min=1e-3 y.max=17e-3
electr name=gate x.min=101e-3 x.max=151e-3 y.min=0e-3 y.max=1e-3
electr name=gate x.min=101e-3 x.max=151e-3 y.min=17e-3 y.max=18e-3
doping uniform n.type conc=5e18 x.min=1e-3 x.max=101e-3 y.min=4e-3 y.max=14e3
doping uniform n.type conc=1e17 x.min=101e-3 x.max=151e-3 y.min=4e-3 y.max=14e3
doping uniform p.type conc=1e20 x.min=151e-3 x.max=251e-3 y.min=4e-3 y.max=14e3
material material=silicon EG300=1.12
material material=oxide permittivity=29
contact name=gate workf=4.5
models mos print
models cvt bbt.kl boltzman print temperature=300
models bbt.kl bgn.klassen trap.tunnel
method newton gummel
solve init
log outfile=simulated.log

Appendix A. DECKBUILD CODING FOR ATLAS

solve vdrain=1.0
solve vgate=0.0
output qfp qfn con.band val.band flowlines
struct outfile=simulated.str
tonyplot simulated.str
go atlas
mesh space.mult=1.0
x.mesh loc=0e-3 spac=2e-3
x.mesh loc=1e-3 spac=5e-4
x.mesh loc=46e-3 spac=2e-3
x.mesh loc=91e-3 spac=5e-4
x.mesh loc=126e-3 spac=2e-3
x.mesh loc=161e-3 spac=5e-4
x.mesh loc=206e-3 spac=2e-3
x.mesh loc=251e-3 spac=5e-4
x.mesh loc=252e-3 spac=2e-3
y.mesh loc=0.0 spac=2e-3
y.mesh loc=1e-3 spac=5e-4
y.mesh loc=2.5e-3 spac=2e-3
y.mesh loc=4e-3 spac=5e-4
y.mesh loc=11.5e-3 spac=2e-3
y.mesh loc=19e-3 spac=5e-4
y.mesh loc=20.5e-3 spac=2e-4
y.mesh loc=22e-3 spac=5e-4
y.mesh loc=23e-3 spac=2e-3
region num=1 silicon x.min=1e-3 x.max=251e-3 y.min=4e-3 y.max=19e-3
region num=2 oxide x.min=1e-3 x.max=251e-3 y.min=1e-3 y.max=4e-3
region num=3 oxide x.min=1e-3 x.max=251e-3 y.min=19e-3 y.max=22e-3
region num=4 oxide x.min=0e-3 x.max=91e-3 y.min=0 y.max=1e-3
region num=5 oxide x.min=0 x.max=91e-3 y.min=22e-3 y.max=23e-3
region num=6 oxide x.min=161e-3 x.max=252e-3 y.min=0e-3 y.max=1e-3
region num=7 oxide x.min=161e-3 x.max=252e-3 y.min=22e-3 y.max=23e-3
region num=8 oxide x.min=0 x.max=1e-3 y.min=1e-3 y.max=22e-3
region num=9 oxide x.min=251e-3 x.max=252e-3 y.min=1e-3 y.max=22e-3
region num=10 oxide x.min=91e-3 x.max=161e-3 y.min=0e-3 y.max=1e-3
region num=11 oxide x.min=91e-3 x.max=161e-3 y.min=22e-3 y.max=23e-3
electr name=drain x.min=0 x.max=1e-3 y.min=1e-3 y.max=22e-3

57

Appendix A. DECKBUILD CODING FOR ATLAS

58

electr name=source x.min=251e-3 x.max=252e-3 y.min=1e-3 y.max=22e-3


electr name=gate x.min=91e-3 x.max=161e-3 y.min=0e-3 y.max=1e-3
electr name=gate x.min=91e-3 x.max=161e-3 y.min=22e-3 y.max=23e-3
doping uniform n.type conc=5e18 x.min=1e-3 x.max=91e-3 y.min=4e-3 y.max=19e3
doping uniform n.type conc=1e17 x.min=91e-3 x.max=161e-3 y.min=4e-3 y.max=19e3
doping uniform p.type conc=1e20 x.min=161e-3 x.max=251e-3 y.min=4e-3 y.max=19e3
material material=silicon EG300=1.12
material material=oxide permittivity=29
contact name=gate workf=4.4
models mos print
models cvt bbt.kl boltzman print temperature=300
models bbt.kl bgn.klassen trap.tunnel
method newton gummel
solve init
log outfile=optimized.log
solve vdrain=1.0
solve vgate=0.0
output qfp qfn con.band val.band flowlines
struct outfile=optimized.str
tonyplot optimized.str