QIS COLLEGE OF ENGINEERING & TECHNOLOGY ::

ONGOLE
(An ISO 9001:2008 Certified Institution & Accredited by NBA)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Class & Section: M.Tech Duration: 2:00
Max. Marks:
Semester: I
VLSI&ES
hours
40
Date: 24-03Sub: CPLD and FPGA Architectures and
II Mid Term Examination
Applications
2015
Answer all Questions &each question carries 10 marks

1
2
3
4

Explain in detail the top down design flow of FPGA.

(a) Give the detailed architecture of ACTEL ACT1 and explain its operation.
(b) Write few comparisons of ACTEL ACT1, ACT2 and ACT3 FPGAs.
Designing Adders & Accumulators with the ACT Architecture.
Write brief notes on any two.
(a) Floor plan 5M
(b) Optimized reconfigurable cell array. 5M
(c) Speed performance of different CPLDs. 5M
Prepared by

Mr.P.PRAVEEN KUMAR

QIS COLLEGE OF ENGINEERING & TECHNOLOGY :: ONGOLE

(An ISO 9001:2008 Certified Institution & Accredited by NBA)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Class & Section: M.Tech Duration: 2:00
Semester: I
Max. Marks: 40
VLSI&ES
hours
Date: 24-03Sub: CPLD and FPGA Architectures and
II Mid Term Examination
Applications
2015
Answer all Questions &each question carries 10 marks

1
2
3
4

Explain in detail the top down design flow of FPGA.

(a) Give the detailed architecture of ACTEL ACT1 and explain its operation.
(b) Write few comparisons of ACTEL ACT1, ACT2 and ACT3 FPGAs.
Designing Adders & Accumulators with the ACT Architecture.
Write brief notes on any two.
(a) Floor plan 5M
(b) Optimized reconfigurable cell array. 5M
(c) Speed performance of different CPLDs. 5M
Prepared by

Mr.P.PRAVEEN KUMAR

QIS COLLEGE OF ENGINEERING & TECHNOLOGY :: ONGOLE

(An ISO 9001:2008 Certified Institution & Accredited by NBA)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Class & Section: M.Tech Duration: 2:00
Semester: I
Max. Marks: 40
VLSI&ES
hours
Date: 24-03Sub: CPLD and FPGA Architectures and
II Mid Term Examination
Applications
2015
Answer all Questions &each question carries 10 marks

1
2
3
4

Explain in detail the top down design flow of FPGA.

(a) Give the detailed architecture of ACTEL ACT1 and explain its operation.
(b) Write few comparisons of ACTEL ACT1, ACT2 and ACT3 FPGAs.
Designing Adders & Accumulators with the ACT Architecture.
Write brief notes on any two.
(a) Floor plan 5M
(b) Optimized reconfigurable cell array. 5M
(c) Speed performance of different CPLDs. 5M

QIS COLLEGE OF ENGINEERING & TECHNOLOGY ::

ONGOLE
(An ISO 9001:2008 Certified Institution & Accredited by NBA)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Class & Section: M.Tech Duration: 2:00
Max. Marks:
Semester: I
VLSI&ES
hours
40
Date: 24-03Sub: CPLD and FPGA Architectures and
II Mid Term Examination
Applications
2015
Answer all Questions &each question carries 10 marks

Prepared by
Mr.P.PRAVEEN KUMAR