CMOS2 3 4 4A June13

CMOS VLSI Design, Lecture #2
Diploma in VLSI Design - June 2013 PUNE
An Introduction
to
CMOS VLSI Design

LECTURE 2
Presented By:
Yogindra S. Abhyankar
Associate Director & HOD (RC)
Hardware Technology Development Group
2013 Centre for Development of Advanced Computing
Agenda: Lecture 2_4

IC Design Cycle
Fabrication Process
PMOS
CMOS
Cross-Section of CMOS Technology

Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
A
GND
VDD
SiO2
n+ diffusion
n+
n+
p+
p+
n well
p substrate
nMOS transistor
p+ diffusion
polysilicon
metal1
pMOS transistor
IC Design Cycle
Mask house
System Requirements
Fabrication house
Design house
Architecture & Logic Design

Circuit Design
Layout
Insulator (Sio2)
Semiconductor (diffusion)
Layout (Layer Description)
Conducting material
Circuit & Layout Simulation
(metal, polysilicon)
Design-Fabrication Interface
Design Tools
Design Rules
Design Tools: Enables designers to deal with
designs at a level that does not involve
details of fabrication process/parameters
Design Rules: Make it possible for the Circuit
to work properly (electrically) after
fabrication using an area, as small as
possible
Design Tools
MAGIC/ Micro Magic
Developed at the University of California, Berkeley
Virtuoso
Cadence Tools
Mentor CAD Tools

Tanner Tools
Spice: Powerful Circuit Simulator
IRSIM: Switch level Simulator
esim: Event driven switch level Simulator
Crystal: VLSI timing analyzer
peg: A finite state machine compiler
MAGIC
An interactive Layout tool for creating and
modifying VLSI circuits
Popular in the Universities
Built-in knowledge of layout rules
Knows about connectivity and transistors
MOS transistor Layouts

D
PMOS Enhancement
D
G
NMOS Enhancement
CMOS Process Layers

Layer
Color
Representation
Well (p,n)
Yellow
Well
n diffusion
Green
Source, Drain, (signal wires)
p diffusion
Brown
Source, Drain, (signal wires)
Polysilicon
Red
Transistor gates, signal wires
Metal1
Blue
Power & signal Wires
Metal2
Magenta
Power Wires
Contacts
Black
Signal connection
Via
Insulator
Function
Connection between metal layers

none
Insulates two layers
Layout example
P-transistor
L=2
W=4
Positions relative to silicon surface

Metal-Diffusion
Contact
10
MAGIC: Design Style
Manhattan Style
Diagonal Style
MAGIC permits only Manhattan Designs

Micro Magic permits both styles
11
Layout Design Rules

To ensure that design works even when small fab
errors (within some tolerance) occur
Interface between designer and process engineer
Guidelines for constructing process masks
Rules: spacing between wells, contacts sizes, minimum distance
between poly and metal etc
Two approaches for Layout rules:

Scalable design rules: Lambda () parameter
popularized by Mead & Conway
Simple, portable
Absolute dimensions (micron rules)

Can give 50 % reduction in area over rule
12
Why Have Design Rules?
To be able to tolerate some level of fabrication

errors such as
1. Mask misalignment
2. Dust
3. Process parameters
(e.g., lateral diffusion)
4. Rough surfaces
13
What is ?
It is a scalable parameter that describes the minimum resolution

of the fabrication process.
Usually = 1/2 Transistor length
For a 2 process, minimum W, L = 2
=> = 1
Minimum device Length

Meta Rules:
1. 1 error should not be fatal deviation from the expected performance
2. 2 error may be fatal; certainly degraded performance
14
Intra-Layer Design Rules

Same Potential
Different Potential
0
or
6
Well
10
ndiff
2
Polysilicon
pdiff
Metal1
3
3
Contact
or Via
Hole
2
2
Metal2
15
Design Rule: example 1

Deviation by
Poly of minimum width
Conducts with 2 x Resistance
Conducts with lowered

Resistance
16
17

Deviation by 2
Poly of minimum width
No more a conductor
Deviation by 2 produces a short!

Effect on Transistors:
Diffusion
Polysilicon
Drain Diffusion
Source
0
Source Diffusion
Transistor must satisfy the 2

minimum length rule !
18
Layout Design Rules

TECHNOLOGY RELATED CAD ISSUES
Two basic checks must be completed to ensure the mask database
developed in Layout can be turned into a working Chip:
To verify specified Design Rules have been obeyed

(DESIGN RULE CHECK or DRC)
To verify that the masks produce, correct interconnected
set of circuit elements
(MASK CIRCUIT-EXTRACTION)
19
20
Layout description formats CIF,EDIF,GDS
Mask house
Layout description is
expressed into
standard interchange
formats:
1. Caltech Intermediate
Form (CIF)
2. Electronic Data
Interchange Format
(EDIF)
Formats are useful for
3. Calma GDS providing masks
Design Cycle:Mask house
MASK
Design house
Preprocess
software
Mask house
Set of Control Commands
Fabrication house
Opaque area
Electron Beam Pattern Generator

Laser Beam
Mask / films are set of images

Transparent area
21
22
Mask Making Steps

Develop
Defects
Etch
Repair
Design Cycle: Fabrication house

Fabrication house Printing of Masks on silicon wafer
IC
Feature Size
Gate oxide thickness
Fabrication Process
Number of interconnection levels
Type of Substrate material

nmos
pmos
CMOS
Choice of Gate material

Type of transistor used
23
Fabrication house
VLSI FABRICATION REQUIRES
AN EXPENSIVE CAPITAL
INVESTMENT
Wafer Fabrication
(Diffusion, oxidation,
photomasking, ion implant,
thin film deposition)
Final Tests
Packaging
(encapsulation)
Wafer Probe Tests
Visual
inspection
Chip
Seperation
24
Substrate Wafer Fabrication
Temp: ~ 1500 0 C
Ingot formation: Pure molten silicon
Czochralski Method
Mirror Polishing
25
26
Mask and Its Use in Semiconductor Lithography

/ Laser)
=193 nm (ArF) -> 157 nm (F)
(DUV)
27
28
Why is Lithography So Difficult?

Three
lithography knobs to twist
- Exposure wavelength ( ) the smaller the better.. = >>13.4nm (EUVL since 2007)
Lens size (Numerical Aperture) the larger the better
Process complexity factor (k1 )

Feature size = k 1 . Wavelength / lens size
A measure of lithography aggressiveness
Smaller means the ability to print smaller features

Wavelength
scaling has not kept up with the rate of feature size scaling
Time and cost to engineer new lasers and exposure systems
Lens size can grow upto limit Size and cost of Lenses; maximum lens size: NA = 1
Making k1 smaller has been the area of primary effort
The burden of doing this falls primarily on the mask maker!
Printing Features with Low-K1

Lithography
Wavelengths > or comparable to feature size causes distortion in patterns exposed
29
Image on mask VS on Wafer

Resolution Enhancement Techniques (RETs) are required
Must be resolved
on the Mask
Image on the
Wafer
30
31
CMOS Fabrication Process

S
Oxide
N+
nwell
pwell (Historical)
Twin tub
Silicon on insulator
Triple-well process
N+
P
100
P+
P+
n well
nwell- Fabrication Steps

Start with blank wafer
Form the n-well
Cover wafer with protective layer of SiO2 (oxide)

Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
p substrate
32
Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
33
Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
Photoresist
SiO2
p substrate
34
Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
Photoresist
SiO2
p substrate
35
Etch
Etch oxide with hydrofluoric acid (HF)
Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
36
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesnt melt in next step
SiO2
p substrate
37
38
Formation of n-well
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2; only enter exposed Si
SiO2
n well
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
n well
p substrate
39
40
Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer

Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
Polysilicon Patterning
Use same lithography process to pattern
polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
41
Self-Aligned Process
Use oxide and masking to expose where n+
dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and
n-well contact
n well
p substrate
42
N-diffusion
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesnt melt during later processing
n+ Diffusion
n well
p substrate
43
N-diffusion
contd..
Historically dopants were diffused

Usually ion implantation today
But regions are still called diffusion
n+
n+
n+
n well
p substrate
44
N-diffusion
contd..
Strip off oxide to complete patterning step
n+
n+
n+
n well
p substrate
45
P-Diffusion
Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+
p+
p+
n well
p substrate
n+
46
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contact
Thick field oxide

p+
n+
n+
p+
p+
n well
p substrate
n+
47
Metalization
Sputter aluminum over whole wafer
Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+
n+
n+
p+
p+
n well
p substrate
n+
48
49

S
Oxide
P+
pwell Process
Start with n-type substrate (wafer)
Create p-well for n-type transistor
Build p-type transistor in n-substrate
P+
N
100
N+
N+
P well
50

n well
P well
P+
P+
N+
N+
100
pwell
Produces balanced performance of p
and n transistors
nwell
1. n-channel transistors are faster
1. Reduces latch-up
2. Transistor created in a well has less

speed compared to one in a substrate
Reduces sensitivity to particle

2. Low cost
3. Improved n-channel performance

Twin-Tub
Process
Start with an undoped wafer; add both n- and p-tubs
Allows Separate control over n-type and p-type transistors

- Threshold Voltage
- Gain
Epi => Growing single crystal film on Si surface
51

Silicon on insulator (SOI)
Uses Insulating substrate
instead of Silicon
Thin Silicon layer
-Absence of wells
Closer packing of p & n transistors
-Low S/D to substrate capacitance

possibility of faster circuits
-Low leakage currents
Sapphire or silicon Oxide
-No latchup due to isolation of

n and p transistors
52
Latchup
Formation of Parasitic Transistor/SCR
VD D
npnp
SCR
p
V DD
p
n-well
R nw ell
p-source
R n well
R psu bs
n-source
p-substrate
(a) Origin of latchup
(b) Equivalent circuit
Firing of SCR results in heavy current, damaging the IC (VDD & GND short)
R psub s
53
54
How to avoid undesirable Parasitic

transistors ?
Solution:
(1) Minimize, Substrate/Well resistances => use Guard Rings/Channel Stops!! :
These are additional heavy diffusion regions made with same type of
material as that of the substrate/well
Connect p+ to the lowest dc potential (GND)

Connect n+ to the highest dc potential (Vcc)
Guard Rings
V DD
(2) Reduce gain of the parasitic transistors

Add thin epitaxial layer over substrate
p+
n+
p+
p+
n-well
(3) Use SOI processes

- npn & pnp are electrically isolated
n+
R psu bs
p-substrate
n+
R n well
International Technology Roadmap for Semiconductors : ITRS

Goal: Predict semiconductor scaling for next 15 years
Convert Moores law into detailed projections
Identify technical roadblocks
Result of a worldwide consensus

USA, Europe, Japan, Korea, and Taiwan
Since 1994
Initially every three years
Now significant yearly updates
Types of chip technologies discussed

Logic: high speed transistor, lots of metal layers
High performance microprocessors
Low power microprocessors
DRAM, Flash
55
Lithography Technology Requirements
56
Introduction to Magic
57
Layers
58
Layers
59
MAGIC : Basic commands

Grid
Displays a grid over layout
:grid [spacing]
or ^g
It is a toggle command (on-off)
:grid off
60

Zoom
:Zoom factor
Example
:zoom 2
Will display twice units across
the screen as there used to be
61

Operations on Selection
Move
It picks up both the box and the selection

and moves them
:move [direction [distance]] or macro "t"
Example
:move up 10
Direction can be, left,south,down etc.
62

Copy
It is similar to move, except the copy of

the selection is left behind at the
original position.
:copy or macro "c"
63

Upsidedown
:upsidedown
Sideways
:sideways
Clockwise
:clockwise [degrees]
64

Label (first select area)
:label [text [position [layer]]]
Position tells where the text to be

put relative to the point of label.
North,south,east,west,top,bottom,
left,right,up,down,center etc.
Erase a label (first select area)

:erase label
65

Save layout
:save or :save filename
It saves with .mag/.max extension
Quit
:quit
To quit magic
66
Design Rule Check (DRC)

You can check if there is an error and the
reason in any area. First put a box on the area
you want to check and issue the command:
White dots indicate violation of

design rules
67
MAGIC : Cell hierarchy

After you designed the layout
for a typical component,
you can use it as a cell to
build other.
Example using two inverters
use subcell.
1. Open magic to edit a new
file called top.mag:
2. In Magic, issue the

command below twice:
:getcell inverter
68
MAGIC : Cell hierarchy

3. Then put these two inverters
together, select them and

issue command to see the
structure of inverter:
:expand or macro "x"
Unexpand the cell with

command:
:unexpand or macro "X
Show /Hide
69
Chip Layout
Cell View
Expanded View
70
Micro Magic Design Suite
71
Micro Magic : SUE

SUE is a graphical Design Manager/environment
Allows users to enter, visualize, and control large, complex chip
designs
First tool to combine HDL-based functional designs with structural
design
SUE understands everything from Verilog down to the operation and
physical placement of transistors and wires
Drive Third party simulation tools
72
Micro Magic: Layout Editor - Max

Message area
73
Micro Magic: Layout Editor - Max
74
Max Layers
Metals (5) and Vias/contacts between interconnect layers
-m5 connects only to m4, m4 only to m3, etc. and

m1 only to poly, ndiff and pdiff
Active active areas on substrate

- Poly gates, transistor channels (nfet, pfet),
source & drain diffusions (ndif, pdif) and
well contacts (nwc, pwc)
Wells (nw) and other areas
75
76
Max Features
Continuous DRC feedback during layout with hierarchical and incremental DRC
Interactive connectivity tracing
Interactive wiring tool with flylines to show connections not yet completed
Layout generator for gates (using MAX-LS)
Generators for large regular structures such as SRAMS, ROMs, PLA's, and
DRAM's (with the optional MegaCell Compiler)
Interfaces to other tools, including schematic capture (for example SUE), and
batch DRC and LVS (for example Dracula or Calibre).
Smart palette for easy control and feedback on layers
Full customization and extension via Tcl/Tk scripting language and API
Technology independence via technology description files

Optimized for large databases
Very Fast Redisplay for Whole Chip Viewing and Inspection
Reads/writes GDSII
Runs on Solaris and Linux operating systems.
Micro Magic: Max-LS

This tool has all the capabilities of the standard
MAX layout editor, plus it has a schematic viewer and
Layout generator
It features true schematic-driven layout design,
offering the ability to interactively generate a
layout that is DRC- and LVS-correct with devices
automatically sized
77
Inverter Layout :
P-transistor
F=A
A Out
0
L=2
W=4
VCC
Out
In
Metal-Diffusion
Contact
GND
78
NAND gate Layout

A
B
A.B = A + B
Layout ?
(W/L)p
(W/L)p
(W/L)n
(W/L)n
79
NAND gate Layout 2

A
B
A.B = A + B
Using Parallel Transistors
(W/L)p
(W/L)p
(W/L)n
(W/L)n
80
Conclusion
Continuing Research in Device, fabrication
& tool Technology fulfilling the future needs
of Industry
Sub-micron processes use multiple levels of

polysilicon/metal interconnects for higher
circuit densities, Strained silicon transistors,
3D Transistors, 22nm process, 300->450mm
wafer!
http://www.fabtech.org
81

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CMOS VLSI Design, Lecture #2

Diploma in VLSI Design - June 2013 PUNE

CMOS VLSI Design

Diploma in VLSI Design - June 2013 PUNE

CMOS VLSI Design, Lecture #2

Agenda: Lecture 2_4

2013 Centre for Development of Advanced Computing

CMOS VLSI Design, Lecture #2

Diploma in VLSI Design - June 2013 PUNE

Cross-Section of CMOS Technology

2013 Centre for Development of Advanced Computing

CMOS VLSI Design, Lecture #2

Diploma in VLSI Design - June 2013 PUNE

Architecture & Logic Design

Layout (Layer Description)

Circuit & Layout Simulation

2013 Centre for Development of Advanced Computing

Diploma in VLSI Design - June 2013 PUNE

CMOS VLSI Design, Lecture #2

Diploma in VLSI Design - June 2013 PUNE

CMOS VLSI Design, Lecture #2

Mentor CAD Tools

CMOS VLSI Design, Lecture #2

Diploma in VLSI Design - June 2013 PUNE

2013 Centre for Development of Advanced Computing

CMOS VLSI Design, Lecture #2

Diploma in VLSI Design - June 2013 PUNE

MOS transistor Layouts

CMOS VLSI Design, Lecture #2

Diploma in VLSI Design - June 2013 PUNE

CMOS Process Layers

Source, Drain, (signal wires)

Source, Drain, (signal wires)

Transistor gates, signal wires

Power & signal Wires

Connection between metal layers

2013 Centre for Development of Advanced Computing

Insulates two layers

CMOS VLSI Design, Lecture #2

Diploma in VLSI Design - June 2013 PUNE

Positions relative to silicon surface

2013 Centre for Development of Advanced Computing

Diploma in VLSI Design - June 2013 PUNE

CMOS VLSI Design, Lecture #2

MAGIC: Design Style

MAGIC permits only Manhattan Designs

Diploma in VLSI Design - June 2013 PUNE

CMOS VLSI Design, Lecture #2

Layout Design Rules

Two approaches for Layout rules:

Absolute dimensions (micron rules)

Diploma in VLSI Design - June 2013 PUNE

CMOS VLSI Design, Lecture #2

Why Have Design Rules?

To be able to tolerate some level of fabrication

Diploma in VLSI Design - June 2013 PUNE

CMOS VLSI Design, Lecture #2

It is a scalable parameter that describes the minimum resolution

Minimum device Length

CMOS VLSI Design, Lecture #2

Diploma in VLSI Design - June 2013 PUNE

Intra-Layer Design Rules