Department of Electrical and Electronic Engineering, Imperial College London

Single Slope ADC with Serial Output

Erasnita, Arditto Trianggada (00890769)
Department of Electrical and Electronic Engineering, Imperial College London
arditto.erasnita13@imperial.ac.uk

Abstract- Rapid development of digital electronic

technology demand a robust ADC design which links the
sensed signal by transducers in the form of analog into
digital signal so that complex computation can be
productively processed. Digital signal also has an advantage
of less susceptible to the noise compared with analog signal.
However, ADC design process often has trade-offs (e.g.,
speed, resolution, accuracy and cost) which have to be
considered depend on the purpose of design.

when ramp signal reach the same level as input signal,

comparator output will be active and trigger the digital stage
to generate digital conversion result. Digital operation stage
consists of three circuits such as control logic, binary
counter and PISO (Parallel Input Serial Output). Binary
counter counts number for every clock cycle to measure the
time needed until comparator switched on. Output of
counter then processed in PISO to output digital number in
sequentially serial with MSB comes first. Those operation
within digital stage is controlled by control logic circuit.
At the beginning, START input signal initiates ADC to
start conversion process. It reset integrator and counter to
their initial condition. On the next rising edge after START
switches low, integrator and counter will start operating
(integrator start generating positive slope ramp and counter
start counting to zero. Fig 2 shows how single slope ADC
operates with waveform simulation. The comparator output,
which will be active whenever VRAMP reach the voltage
level of VIN, control SO output to produce conversion result
by process within control logic function.

In this paper, the writer describes design methodology of

one of commonly used type of ADC that is Single Slope
ADC. It has advantages in terms of its accuracy and highresolution. However, it usually performs in slower speed if
compared with other types like flash ADC, pipeline ADC,
etc.
Keyword: single slope, resolution, hysteresis
I.

INTRODUCTION

In the basic, single slope ADC performs its conversion

process by comparing the input signal with a reference
voltage signal until the comparison process indicates that
those two voltages are equal. The process itself is
implemented in a circuit called comparator. On the other
hand, single slope contains a digital binary counter that
counts in every clock cycle. The comparator hence decide the
time when the counter's output can be considered as ADC's
conversion result (i.e., digital representation of input signal).

Fig. 1: Block Diagram of Single Slope ADC

Main characteristic of single slope ADC described in this

paper is that digital output is produced in serial sequence.
Therefore, the system has to posses a reliable digital circuit
which can handle an operation to generate a serial conversion
output without disturbing analog operation within the system.
It is also commonly known that digital usually consume more
power and amount of transistors, therefore, design efficiency
is important.
II.

Fig. 2: Timing Diagram of Single Slope ADC

III.

SYSTEM OVERVIEW

CIRCUIT IMPLEMENTATION

The first analog function in single slope ADC is an

integrator. In this paper, the writer represents integrator
opamp with switched-capacitor topology to implement the
resistor. It generates a ramp signal whose slope is adjusted
by voltage reference, gain of the opamp and capacitors in
the circuit. Opamp design should consider some

Single slope ADC in this paper comprises three stages

such as integration stage, comparator stage and digital
operation stage. Integration stage function to generate a
ramp signal as a reference voltage. In the comparator stage,
ramp signal is then compared to the input signal to
determine digital representation of input signal. By the time
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Department of Electrical and Electronic Engineering, Imperial College London

characterization such as gain (adjust the slope of ramp),
bandwidth (speed of integrator) and phase margin
(reliability of integrator to get stable quickly). Opamp which
being used in single slope ADC is a two-stage topology
opamp[2] (shown in Fig. 3) with voltage bias source is
implemented by using CMOS voltage divider topology (Fig.
4). This opamp has a specification of 87 dB gain, 2 kHz
bandwidth and 53 phase margin (Fig. 5). The opamp then
used in integrator to implement integrator circuit with
switched-capacitor topology. Its schematic and waveform
simulation is shown in Fig. 6 and Fig. 7.
Fig. 6: Integrator Circuit Schematic

Fig. 3: Opamp Circuit Shematic

Fig. 7: Waveform Simulation Result of Integrator

hysteresis circuit to shift the operating point hence the speed
is improved. Complete comparator schematic is shown in
Fig. 8 with the same voltage bias implementation as opamp
previously. Simulation which presents the comparator's
performance of speed and input range is shown in Fig. 9 and
Fig. 10.

Fig. 4: Voltage Bias Generator

Fig. 8: Comparator Circuit Schematic

Fig. 5: Opamp Specification

Comparator design in single slope ADC has its most
important consideration in its input range operation and
speed. Comparator has to be able to operate in the desired
input voltage range (i.e., between 0.4 - 1.4 V in this single
slope ADC) and also has an acceptable speed to make sure
that SO can produce a correct conversion result. A threestage comparator topology[1] is implemented which can
handle comparison operation in the input range and also
featured by

Fig. 9: Gain Characteristic of Comparator

Digital part of single slope ADC (shown in Fig. 11) play a
role to operate computations to obtain digital representation

Department of Electrical and Electronic Engineering, Imperial College London

is used to remove an unexpected trouble when START
active, i.e., ADC is reset, and the input signal VIN is in its
minimum level or very close to 400 mV. If mux is removed
from the circuit and VRAMP is directly connected to V+ of
comparator, the comparator output VCOMP will exhibit an
invalid logic value because of unbalance hysteresis stage of
the comparator.

Fig. 10: Waveform Simulation Result of Comparator

of input signal. Control logic function (Fig. 12) control the
READY signal which will activate PISO to output serial
sequence of digital conversion result into SO. Binary
counter in here is using series of TFF and synchronized
START as a reset signal (Fig. 13). Output of the counter,
which represents a result of conversion when comparator
output goes high, then processed within PISO (Fig. 14) to
output conversion in serial.

Fig. 15: Schematic of Single Slope ADC

IV.

SIMULATED RESULT

The single slope ADC design is tested to verify its

performance in term of accuracy, sample rate, power
consumption and silicon area. First, testbench ciruit as in
Fig. 16 is built to verify its result of data conversion. As a
sample, VIN 1.1V is used with 100 MHz clock frequency.
START signal is set active for one clock cycle duration in
every one over 30 kHz (i.e., 33 s). Waveform simulation
result is presented in Fig. 17. After that, another input
voltage values is used to test relative error of the ADC
(simulation result table in Fig. 18).

Fig. 11: Schematic of Digital Block

Fig. 16: Single Slope ADC Testbench Circuit

Fig. 12: Schematic of Control Logic Function

Fig. 13: Schematic of Digital Counter

Fig. 14: Schematic of Parallel Input Serial Output (PISO)

The complete schematic of single slope ADC circuit is
shown in Fig. 15. Mux in between integrator and comparator
Fig. 17: Waveform Simulation of Single Slope ADC
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REFERENCE

Fig. 18: Error Check Result of Single Slope ADC

Final step of the design is to design the layout. The result
of layout design is shown in Fig. 19 which successfully
passed DRC and LVC check in Cadence Virtuoso software.
Overall technical specification of the single slope ADC
discussed in this paper is shown in Fig. 20

RJ Baker, CMOS: Circuit Design, Layout, and Simulation, WileyIEEE Press (3rd Edition), 2011

[2]

PE Allen and DR Holberg, CMOS Analog Circuit Design, Oxford

University Press (2nd Edition), 2002

[3]

A Hastings, The Art of Analog Layout, Prentice Hall (2nd Edition),

2006

[4]

A Sedra and K Smith, Microelectronic Circuits, Oxford University

Press (6th Edition), 2011

[5]

PR Gray and RG Meyer, MOS Operational Amplifier Design A

Tutorial Overview, IEEE Journal of Solid-State Circuits SC-17, No
6, 1982

[6]

S Brown and Z Vranesic, Fundamentals of Digital Logic with VHDL

Design, McGraw-Hill 2nd ed, 2005
S Franco, Design with Operational Amplifiers and Analog Integrated
Circuits, McGraw-Hill 3rd ed,

[7]

Fig. 19: Layout of Single Slope ADC

Fig. 20: Achieved Technical Specification of Single Slope

ADC
V.

[1]

CONCLUSION

The single slope ADC in this paper can operate to convert

analog signal into digital accurately in most all of input
ranges even though there are one bit error cases in some
points. This occurs because integrator circuit within the
system is impelemented by using switched-capacitor
topology which relatively non-linear in small scale of
voltage. It can be minimized by replacing switchedcapacitor based resistor with polysilicon resistor. However,
it will consume larger silicon area.
If we consider area and powerconsumption of the circuit,
digital is usually weaker than analog. Better performance of
ADC can be achieved when digital circuit within our system
is minimized as simple as possible. Therefore, digital
operation in the single slope ADC can also be modified to
minimize usage of flip-flops circuits. It can be done by
combining digital counter and PISO, hence, both those two
blocks share their flip-flops together then the amount of flipflops used is reduced by half.