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Computer

Architecture (CS 493)

Name: Enanko Basak


Roll Number: 1351047
Computer Science And
nd
Engineering 2 Year

DAY 1:
15 .01.2015
Data Flow Architecture for Basic Gates
AND GATE
Code:
entity and_gate is
Port ( a : in std_logic;
b : in std_logic;
x : out std_logic);
end and_gate;
architecture DataFlow of and_gate is
begin
x <= a and b;
end DataFlow;
Schematic Diagram:

Truth Table:

Waveform:

OR Gate
Code:
entity or_gate is
Port ( a : in std_logic;
b : in std_logic;
x : out std_logic);
end or_gate;
architecture dataflow of or_gate is
begin
x <= a or b;
end dataflow;
Schematic Diagram:

Truth Table:

Waveform:

XOR Gate
Code:
entity xor_gate is
Port ( a : in std_logic;
b : in std_logic;
x : out std_logic);
end xor_gate;
architecture DataFlow of xor_gate is
begin
x <= a xor b;
end DataFlow;

Schematic Diagram:

Truth Table:

Waveform:

NOT Gate
Code:
entity not_gate is
Port ( a : in std_logic;
x : out std_logic);
end notgt;
architecture dataflow of not_gate is
begin
x <= not a;
end dataflow;

Schematic Diagram:

Waveform:

NAND Gate
Code:
entity nand_gate is
Port ( a : in std_logic;
b : in std_logic;
x : out std_logic);
end nand_gate;
architecture DataFlow of nand_gate is
begin
x <= a nand b;
end DataFlow;

Schematic Diagram:

Truth Table:

Waveform:

NOR Gate
Code:
entity nor_gate is
Port ( a : in std_logic;
b : in std_logic;
y : out std_logic);
end nor_gate;
architecture DataFlow of nor_gate is
begin
y <= a nor b;
end DataFlow;
Schematic Diagram:

Truth Table:

Waveform:

DAY 2: 22.01.2015
DataFlow Architecture for Basic Gates using Universal Gates.
AND GATE using NAND Gates
Code:
entity And_Nand is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end And_Nand;
architecture DataFlow of And_Nand is
begin
X <= (A nand B) nand (A nand B);
end DataFlow;
Schematic Diagram:

Truth Table:

Waveform:

OR GATE using NAND Gates


Code:
entity Or_Nor is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end Or_Nor;
architecture DataFlow of Or_Nor is
begin
X <= (A nand A) nand (B nand B);
end DataFlow;

Schematic Diagram:

Truth Table:

Waveform:

NOT GATE using NAND Gates


Code:
entity Not_nand is
Port ( A : in std_logic;
X : out std_logic);
end Not_nand;
architecture DataFlow of Not_nand is
begin
X <= (A nand A);
end DataFlow;

Schematic Diagram:

Waveform:

10

AND GATE using NOR Gates


Code:
entity ANo1 is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end ANo1;
architecture DataFlow of ANo1 is
begin
X <= (A nor A) nor (B nor B);
end DataFlow;

Schematic Diagram:

Truth Table:

Waveform:

11

OR GATE using NOR Gates


Code:
entity Or_nor is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end Or_nor;
architecture DataFlow of Or_nor is
begin
X <= (A nor B) nor (A nor B);
end DataFlow;

Schematic Diagram:

Truth Table:

Waveform:

12

NOT GATE using NOR Gates


Code:
entity not_or is
Port ( A : in std_logic;
X : out std_logic);
end not_or;
architecture DataFlow of not_or is
begin
X <= (A nor A);
end DataFlow;

Schematic Diagram:

Waveform:

13

Half Adder:
Code:
entity Half_Adder is
Port ( A : in std_logic;
B : in std_logic;
S : out std_logic;
C : out std_logic);
end Half_Adder;
architecture DataFlow of Half_Adder is
begin
S <= A and B;
C <= A xor B;
end DataFlow;
Schematic Diagram:
Carry:

Sum :

14

Truth Table:

Sum:

Carry :

Waveform:

15

Full Adder
Code:
entity full_adder is
Port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
Sum : out std_logic;
Cout : out std_logic);
end full_adder;
architecture DataFlow of full_adder is
begin
Sum <= (A xor B) xor Cin;
Cout <= (A and B) or (B and Cin) or (A and Cin);
end DataFlow;
Schematic Diagram:

Carry:

16

Sum:

Truth Table:
Sum:

Carry:

Waveform:

17

DAY 3: 29.01.2015
Behavioral Architecture of Basic Gates
AND Gate:
Code:
entity and is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end and;
architecture Behavioral of and is
begin
process(A,B)
begin
if(A='0') then
X <='0';
elsif (B='0') then
X <= '0';
else
X<='1';
end if;
end process;
end Behavioral;
Schematic Diagram:

Truth Table:

Waveform:

18

OR Gate
Code:
Entity or is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end or;
architecture Behavioral of or is
begin
process(A,B)
begin
if(A='1')then
X<='1';
elsif(B='1')then
X<='1';
else
X<='0';
end if;
end process;
end Behavioral;
Schematic Diagram:

Truth Table:

Waveform:

19

NOT Gate
Code:
entity not is
Port ( A : in std_logic;
X : out std_logic);
end behavnot;
architecture Behavioral of not is
begin
process(A)
begin
if(A='0')then
X<='1';
else
X <='0';
end if;
end process;

end Behavioral;
Schematic Diagram:

Waveform:

20

NAND Gate
Code:
entity nand is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end nand;
architecture Behavioral of nand is
begin
process(A,B)
begin
if(A='0')then
X<='1';
elsif(B='0')then
X<='1';
else
X<='0';
end if;
end process;
end Behavioral;
Schematic Diagram:

Truth Table:

Waveform:

21

NOR Gate
Code:
entity nor is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end nor;
architecture Behavioral of nor is
begin
process(A,B)
begin
if(A='1')then
X<='0';
elsif(B='1')then
X<='0';
else
X<='1';
end if;
end process;
end Behavioral;
Schematic Diagram:

Truth Table:

Waveform:

22

XOR Gate
Code:
entity xor is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end xor;
architecture Behavioral of xor is
begin
process(A,B)
begin
if(A=B)then
X<='0';
else
X<='1';
end if;
end process;
end Behavioral;
Schematic Diagram:

Truth Table:

Waveform:

23

Half Adder: Behavioral Model


Code:
entity Half_Adder is
Port ( A : in std_logic;
B : in std_logic;
C : out std_logic;
S : out std_logic);
end Half_Adder;
architecture Behavioral of Half_Adder is
begin
process(A,B)
begin
if(A=B)then
S<='0';
else
S<='1';
end if;
if(A='0')then
C <='0';
elsif(B='0')then
C <= '0';
else
C<='1';
end if;
end process;
end Behavioral;

Waveform:

24

Full Adder: Behavioral Model


Code:
entity Full_Adder is
Port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
Cout : out std_logic;
Sum : out std_logic);
end Full_Adder;
architecture Behavioral of Full_Adder is
begin
process(A,B,Cin)
begin
if(A='0')then
if(B=Cin) then
Sum<='0';
else
Sum<='1';
end if;
else
if(B=Cin)then
Sum<='1';
else
Sum<='0';
end if;
end if;
if(A='0')then
if(B='0')then
Cout<='0';
elsif(Cin='0')then
Cout<='0';
else
Cout<='1';
end if;
else
if(B='1')then
Cout<='1';
elsif(Cin='1')then
Cout<='1';
else
Cout<='0';
end if;
end if;
end process;
end Behavioral;
25

Waveform:

26

DAY 4: 5 . 02. 2015


Design 2:1 MUX using Behavioral and DataFlow
Behavioral:
Code:
entity mux_b is
Port ( S : in std_logic;
I : in std_logic_vector(1 downto 0);
Y : out std_logic);
end mux_b;
architecture Behavioral of mux_b is
begin
process(I,S)
begin
case S is
when '0' =>
y<=I(0);
when '1' =>
y<=I(1);
when others =>
null;
end case;
end process;
end Behavioral;

Schematic Diagram:

27

Truth Table:

Waveform:

MUX 2 : 1 Using Dataflow


Code:
entity mux_data is
Port ( I : in std_logic_vector(1 downto 0);
S : in std_logic;
Y : out std_logic);
end mux_data;
architecture DataFlow of mux_data is
begin
process(I,S)
begin
Y<= ((not S) and I(0)) or (S and I(1));
end process;
end DataFlow;

28

Schematic Diagram:

Truth Table:

Waveform:

29

Design 4:1 MUX using Behavioral


Code:
entity mux_41 is
Port ( I : in std_logic_vector(3 downto 0);
S : in std_logic_vector(1 downto 0);
Y : out std_logic);
end mux_41;
architecture Behavioral of mux_41 is
begin
process(I,S)
begin
case S is
when "00" =>
Y<=I(0);
when "01" =>
Y<=I(1);
when "10" =>
Y<=I(2);
when "11" =>
Y<=I(3);
when others =>
null;
end case;
end process;
end Behavioral;
DataFlow
Code:
entity mux_data is
Port ( I : in std_logic_vector(3 downto 0);
S : in std_logic_vector(1 downto 0);
Y : out std_logic);
end mux_data;
architecture DataFlow of mux_data is
begin
process(I,S)
begin
Y <= (I(0) and (not S(0) and not S(1)))
or (I(1) and (S(0) and not S(1)))
or (I(2) and (not S(0) and S(1)))
or (I(3) and (S(0) and S(1)));
end process;
end DataFlow;
30

Design a Decoder using DataFlow and Behavioral Architecture


DataFlow
Code:
entity 38decoder_d is
Port ( B : in std_logic_vector(2 downto 0);
D : out std_logic_vector(7 downto 0));
end 38decoder_d;
architecture DataFlow of 38decoder_d is
begin
process(B)
begin
D <= "00000000";
D(7) <= (B(0) and B(1) and B(2));
D(6) <= (not B(0) and B(1) and B(2));
D(5) <= (B(0) and not B(1) and B(2));
D(4) <= (not B(0) and not B(1) and B(2));
D(3) <= (B(0) and B(1) and not B(2));
D(2) <= (not B(0) and B(1) and not B(2));
D(1) <= (B(0) and not B(1) and not B(2));
D(0) <= (not B(0) and not B(1) and not B(2));
end process;
end DataFlow;

31

Behavioral
Code:
entity 38mux_b is
Port ( B : in std_logic_vector(2 downto 0);
O : out std_logic_vector(7 downto 0));
end 38mux_b;
architecture Behavioral of 38mux_b is
begin
process(B)
begin
O<="00000000";
case B is
when "000" =>
O(0)<='1';
when "001" =>
O(1)<='1';
when "010" =>
O(2)<='1';
when "011" =>
O(3)<='1';
when "100" =>
O(4)<='1';
when "101" =>
O(5)<='1';
when "110" =>
O(6)<='1';
when "111" =>
O(7)<='1';
when others =>
null;
end case;
end process;

end Behavioral;

32

Design a 4:1 MUX using when-else


Code:
entity muxwhen is
Port ( I : in std_logic_vector(3 downto 0);
S : in std_logic_vector(1 downto 0);
Y : out std_logic);
end muxwhen;
architecture DataFlow of muxwhen is
begin
Y<= I(0) when S="00" else
I(1) when S="01" else
I(2) when S="10" else
I(3) when S="11";
end DataFlow;

Design a 2:1 MUX using when-else


Code:
entity muxwhen2 is
Port ( I : in std_logic_vector(1 downto 0);
S : in std_logic;
Y : out std_logic);
end muxwhen2;
architecture DataFlow of muxwhen2 is
begin
Y<= I(0) when S=0 else
I(1) when S=1 else;
end DataFlow;

33

DAY 5: 12 .02 . 2015


Design 4 bit ALU
Behavioral
Code
entity alu_4bit_vhd is
Port ( A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
S : in std_logic_vector(2 downto 0);
Y : out std_logic_vector(3 downto 0));
end alu_4bit_vhd;
architecture Behavioral of alu_4bit_vhd is
begin
process(A, B, S)
begin
case S is
when "000" => Y <= A and B;
when "001" => Y <= A or B;
when "010" => Y <= A xor B;
when "011" => Y <= not A;
when "100" => Y <= A + B;
when "101" => Y <= A - B;
when "110" => Y <= A + "0001";
when "111" => Y <= A - "0001";
when others => NULL;
end case;
end process
end Behavioral;

Truth Table:
Select Line
000
001
010
011
100
101
110
111

Operation
A And B
A Or B
A Xor B
Not A
A+B
AB
A+1
A-1

34

Waveform :

35

4-bit Comparator (DataFlow)


Code:
entity Comparator is
Port ( A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
Gr : out std_logic;
Eq : out std_logic;
Ls : out std_logic);
end Comparator;
architecture Dataflow of Comparator is
begin
Gr <= '1' when A > B else '0';
Ls<= '1' when A < B else '0';
Eq<= '1' when A = B else '0';
end Dataflow;
Waveform:

36

Parity Checker (Behavioral)


Code:
entityParity_checker is
Port ( A : in std_logic_vector(3 downto 0);
P_odd : out std_logic;
P_even : out std_logic);
endParity_checker;
architecture Behavioral of Parity_checker is
begin
process(A)
variable temp : std_logic;
begin
temp := A(0) xor A(1);
for i in 2 to 3 loop
temp := temp xor A(i);
end loop;
P_odd<= temp;
P_even<= not temp;
end process;
end Behavioral;

Waveform:

37

DAY 5: 19 .02. 2015


Realisation Of Flip Flops
SR Flip Flop
Behavioral
Code:
entityS_R_FlipFlop is
Port ( S : in std_logic;
R : in std_logic;
C : in std_logic;
Q : out std_logic;
Qout : out std_logic);
endS_R_FlipFlop;
architecture Behavioral of S_R_FlipFlop is
begin
process(S,R,C)
begin
if(C'event and C='1') then
if(S='0' and R='1')then
Q<= '0';
Qout<= '1';
elsif(S='1' and R='0')then
Q<= '1';
Qout<= '0';
elsif(S='1' and R='1')then
Q<= 'X';
Qout<= 'X';
end if;
end if;
end process;
end Behavioral;

Waveform:

38

D-Flip Flop
Code:
entityD_FlipFlop is
Port ( D : in std_logic;
C : in std_logic;
Q : out std_logic;
Qnot : out std_logic);
endD_FlipFlop;
architecture Behavioral of D_FlipFlop is
begin
process(D,C)
begin
if(C'event and C='1') then
if(D='0') then
Q<='0';
Qnot<= '1';
else
Q<='1';
Qnot<='0';
end if;
end if;
end process;
end Behavioral;

Waveform:

39

JK Flip Flop
Code:
entityJK_FlipFlop is
Port ( J : in std_logic;
K : in std_logic;
C : in std_logic;
Q :inoutstd_logic;
Qnot :inoutstd_logic);
endJK_FlipFlop;
architecture Behavioral of JK_FlipFlop is
begin
process(J,K,C)
begin
if(C'event and C='1') then
if(J='0' and K ='1')then
Q<='0';
Qnot<='1';
elsif(J='1' and K='0') then
Q<='1';
Qnot<='0';
elsif(J='1' and K ='1') then
Q<= Qnot;
Qnot<= Q;
end if;
end if;
end process;
end Behavioral;

Waveform:

40

T Flip Flop
Code:
entity tff is
Port ( T : in std_logic;
C : in std_logic;
Q : inout std_logic;
QNOT : inout std_logic);
end tff;
architecture Behavioral of tff is
begin
process(T,C)
begin
Q<='1';
QNOT<=not Q;
if(C'event and C='1') then
if(T='1')then
Q<=not Q;
QNOT <= not Q;
end if;
end if;
end process;
end Behavioral;

Waveform:

41

UP Counter
Code:
entityUP_Cnt is
Port ( C : in std_logic;
clear : in std_logic;
Q : out std_logic_vector(2 downto 0));
endUP_Cnt;
architecture Behavioral of UP_Cnt is
Signal tmp :std_logic_vector(2 downto 0);
Begin
process(clear,C)
begin
if(clear = '1')then
tmp<= "000";
elsif (C'event and C='1') then
tmp<= tmp+1;
end if;
end process;
Q<=tmp;
end Behavioral;

Waveform:

42

Down Counter:
Code:
entity Dn_Cnt is
Port ( C : in std_logic;
clear : in std_logic;
Q : out std_logic_vector(2 downto 0));
endDn_Cnt;
architecture Behavioral of Dn_Cnt is
Signal tmp :std_logic_vector(2 downto 0);
begin
process(clear,C)
begin
if(clear = '1')then
tmp<= "111";
elsif (C'event and C='1') then
tmp<= tmp-1;
end if;
end process;
Q<=tmp;
end Behavioral;

Waveform:

43

DAY 6: 26 . 02 .2015
Full adder using two half adders (Structural approach)
Code:
entityFull_Adder_s is
Port ( x : in std_logic;
y : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic);
endFull_Adder_s;
architecture Structural of Full_Adder_s is
componentHalf_adder is
Port ( A : in std_logic;
B : in std_logic;
S : out std_logic;
C : out std_logic);
end component;
signali,j,k : std_logic;

begin
ha1: Half_adder port map (x,y,i,j);
ha2: Half_adder
port map (i,cin,sum,k);
cout<= k or j;
end Structural;
Schematic Diagram:

44

Waveform:

Ripple Carry Adder


Code:
entityRipple_carry_adder is
Port ( x : in std_logic_vector(3 downto 0);
y : in std_logic_vector(3 downto 0);
cin : in std_logic;
sum : out std_logic_vector(3 downto 0);
carry : out std_logic);
endRipple_carry_adder;
architecture Structural of Ripple_carry_adder is
componentFull_adder_impl is
Port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
S : out std_logic;
Cout : out std_logic);
end component;
signal c1,c2,c3 : std_logic;
begin
fa1 :Full_adder_impl port map (x(0),y(0), cin ,sum(0),c1);
fa2 :Full_adder_impl port map
(x(1),y(1), c1 ,sum(1),c2);
fa3 :Full_adder_impl port map (x(2),y(2), c2 ,sum(2),c3);
fa4 :Full_adder_impl port map (x(3),y(3), c3 ,sum(3),carry);
end Structural;

Waveform:

45

Adder Subtractor Composite Unit


Code
entity Composite_adder is
Port ( x : in std_logic_vector(3 downto 0);
y : in std_logic_vector(3 downto 0);
cin : in std_logic;
sum : out std_logic_vector(3 downto 0);
carry : out std_logic);
end Composite _adder;

architecture Structural of Composite_adder is


componentFull_adder_impl is
Port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
S : out std_logic;
Cout : out std_logic);
end component;

signal t : std_logic_vector(3 downto 0);


signal c1,c2,c3: std_logic;
begin
t(0) <= cinxor y(0);
t(1) <= cinxor y(1);
t(2) <= cinxor y(2);
t(3) <= cinxor y(3);
fa1 :Full_adder_impl port map (x(0),t(0), cin ,sum(0),c1);
fa2 :Full_adder_impl port map
(x(1),t(1), c1 ,sum(1),c2);
fa3 :Full_adder_impl port map (x(2),t(2), c2 ,sum(2),c3);
fa4 :Full_adder_impl port map (x(3),t(3), c3 ,sum(3),carry);
end Structural;

Waveform

46

Full Adder using loop (Structural)


Code:
entityRipple_carry_adder is
Port ( x : in std_logic_vector(3 downto 0);
y : in std_logic_vector(3 downto 0);
cin : in std_logic;
sum : out std_logic_vector(3 downto 0);
carry : out std_logic);
endRipple_carry_adder;
architecture Structural of Ripple_carry_adder is
componentFull_adder_impl is
Port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
S : out std_logic;
Cout : out std_logic);
end component;
signal t : std_logic_vector(3 downto 0);
signal c: std_logic_vector(4 downto 0);
begin
c(0) <= cin;
GK : for i in 0 to 3 generate
t(i)<= cinxor y(i);
FA : Full_adder_impl port map (x(i),t(i), c(i) ,sum(i),c(i+1));
end generate;
carry<= C(4);
end Structural;

Waveform

47

DAY 8: 2 .03. 2015

8to1 MUX(Structural)
Code:
entity mux81 is
Port ( I : in std_logic_vector(7 downto 0);
S : in std_logic_vector(2 downto 0);
Y : out std_logic);
end mux81;
architecture Structural of mux81 is
component Mux4_dataflow is
Port ( I : in std_logic_vector(3 downto 0);
S : in std_logic_vector(1 downto 0);
Y : out std_logic);
end component;
component mux_2 is
Port ( I : in std_logic_vector(1 downto 0);
S : in std_logic;
Y : out std_logic);
end component;
signalya: std_logic_vector(1 downto 0);
begin
mux1 : Mux4_dataflow port map (I(3 downto 0),S(1 downto 0),ya(0));
mux2 : Mux4_dataflow port map (I(7 downto 4),S(1 downto 0),ya(1));
mux3 : mux_2 port map (ya(1 downto 0),S(2),Y);

end Structural;
RTL Schematic:

48

Waveform:

4-bit Serial In Serial Out Register


Code:
entity SISO is
Port ( I : in std_logic;
C : in std_logic;
Q1 : inout std_logic_vector(3 downto 0);
QNOT1 : inout std_logic_vector(3 downto 0));
end SISO;
architecture Structural of SISO is
component dff is
Port ( D : in std_logic;
C : in std_logic;
Q : out std_logic;
QNOT : out std_logic);
end component;
begin
d1: dff port map(I, C, Q1(0), QNOT1(0));
d2: dff port map(Q1(0), C, Q1(1), QNOT1(1));
d3: dff port map(Q1(1), C, Q1(2), QNOT1(2));
d4: dff port map(Q1(2), C, Q1(3), QNOT1(3));
end Structural;
Schematic Diagram:

49

Waveform:

50

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