DAY 1:
15 .01.2015
Data Flow Architecture for Basic Gates
AND GATE
Code:
entity and_gate is
Port ( a : in std_logic;
b : in std_logic;
x : out std_logic);
end and_gate;
architecture DataFlow of and_gate is
begin
x <= a and b;
end DataFlow;
Schematic Diagram:
Truth Table:
Waveform:
OR Gate
Code:
entity or_gate is
Port ( a : in std_logic;
b : in std_logic;
x : out std_logic);
end or_gate;
architecture dataflow of or_gate is
begin
x <= a or b;
end dataflow;
Schematic Diagram:
Truth Table:
Waveform:
XOR Gate
Code:
entity xor_gate is
Port ( a : in std_logic;
b : in std_logic;
x : out std_logic);
end xor_gate;
architecture DataFlow of xor_gate is
begin
x <= a xor b;
end DataFlow;
Schematic Diagram:
Truth Table:
Waveform:
NOT Gate
Code:
entity not_gate is
Port ( a : in std_logic;
x : out std_logic);
end notgt;
architecture dataflow of not_gate is
begin
x <= not a;
end dataflow;
Schematic Diagram:
Waveform:
NAND Gate
Code:
entity nand_gate is
Port ( a : in std_logic;
b : in std_logic;
x : out std_logic);
end nand_gate;
architecture DataFlow of nand_gate is
begin
x <= a nand b;
end DataFlow;
Schematic Diagram:
Truth Table:
Waveform:
NOR Gate
Code:
entity nor_gate is
Port ( a : in std_logic;
b : in std_logic;
y : out std_logic);
end nor_gate;
architecture DataFlow of nor_gate is
begin
y <= a nor b;
end DataFlow;
Schematic Diagram:
Truth Table:
Waveform:
DAY 2: 22.01.2015
DataFlow Architecture for Basic Gates using Universal Gates.
AND GATE using NAND Gates
Code:
entity And_Nand is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end And_Nand;
architecture DataFlow of And_Nand is
begin
X <= (A nand B) nand (A nand B);
end DataFlow;
Schematic Diagram:
Truth Table:
Waveform:
Schematic Diagram:
Truth Table:
Waveform:
Schematic Diagram:
Waveform:
10
Schematic Diagram:
Truth Table:
Waveform:
11
Schematic Diagram:
Truth Table:
Waveform:
12
Schematic Diagram:
Waveform:
13
Half Adder:
Code:
entity Half_Adder is
Port ( A : in std_logic;
B : in std_logic;
S : out std_logic;
C : out std_logic);
end Half_Adder;
architecture DataFlow of Half_Adder is
begin
S <= A and B;
C <= A xor B;
end DataFlow;
Schematic Diagram:
Carry:
Sum :
14
Truth Table:
Sum:
Carry :
Waveform:
15
Full Adder
Code:
entity full_adder is
Port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
Sum : out std_logic;
Cout : out std_logic);
end full_adder;
architecture DataFlow of full_adder is
begin
Sum <= (A xor B) xor Cin;
Cout <= (A and B) or (B and Cin) or (A and Cin);
end DataFlow;
Schematic Diagram:
Carry:
16
Sum:
Truth Table:
Sum:
Carry:
Waveform:
17
DAY 3: 29.01.2015
Behavioral Architecture of Basic Gates
AND Gate:
Code:
entity and is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end and;
architecture Behavioral of and is
begin
process(A,B)
begin
if(A='0') then
X <='0';
elsif (B='0') then
X <= '0';
else
X<='1';
end if;
end process;
end Behavioral;
Schematic Diagram:
Truth Table:
Waveform:
18
OR Gate
Code:
Entity or is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end or;
architecture Behavioral of or is
begin
process(A,B)
begin
if(A='1')then
X<='1';
elsif(B='1')then
X<='1';
else
X<='0';
end if;
end process;
end Behavioral;
Schematic Diagram:
Truth Table:
Waveform:
19
NOT Gate
Code:
entity not is
Port ( A : in std_logic;
X : out std_logic);
end behavnot;
architecture Behavioral of not is
begin
process(A)
begin
if(A='0')then
X<='1';
else
X <='0';
end if;
end process;
end Behavioral;
Schematic Diagram:
Waveform:
20
NAND Gate
Code:
entity nand is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end nand;
architecture Behavioral of nand is
begin
process(A,B)
begin
if(A='0')then
X<='1';
elsif(B='0')then
X<='1';
else
X<='0';
end if;
end process;
end Behavioral;
Schematic Diagram:
Truth Table:
Waveform:
21
NOR Gate
Code:
entity nor is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end nor;
architecture Behavioral of nor is
begin
process(A,B)
begin
if(A='1')then
X<='0';
elsif(B='1')then
X<='0';
else
X<='1';
end if;
end process;
end Behavioral;
Schematic Diagram:
Truth Table:
Waveform:
22
XOR Gate
Code:
entity xor is
Port ( A : in std_logic;
B : in std_logic;
X : out std_logic);
end xor;
architecture Behavioral of xor is
begin
process(A,B)
begin
if(A=B)then
X<='0';
else
X<='1';
end if;
end process;
end Behavioral;
Schematic Diagram:
Truth Table:
Waveform:
23
Waveform:
24
Waveform:
26
Schematic Diagram:
27
Truth Table:
Waveform:
28
Schematic Diagram:
Truth Table:
Waveform:
29
31
Behavioral
Code:
entity 38mux_b is
Port ( B : in std_logic_vector(2 downto 0);
O : out std_logic_vector(7 downto 0));
end 38mux_b;
architecture Behavioral of 38mux_b is
begin
process(B)
begin
O<="00000000";
case B is
when "000" =>
O(0)<='1';
when "001" =>
O(1)<='1';
when "010" =>
O(2)<='1';
when "011" =>
O(3)<='1';
when "100" =>
O(4)<='1';
when "101" =>
O(5)<='1';
when "110" =>
O(6)<='1';
when "111" =>
O(7)<='1';
when others =>
null;
end case;
end process;
end Behavioral;
32
33
Truth Table:
Select Line
000
001
010
011
100
101
110
111
Operation
A And B
A Or B
A Xor B
Not A
A+B
AB
A+1
A-1
34
Waveform :
35
36
Waveform:
37
Waveform:
38
D-Flip Flop
Code:
entityD_FlipFlop is
Port ( D : in std_logic;
C : in std_logic;
Q : out std_logic;
Qnot : out std_logic);
endD_FlipFlop;
architecture Behavioral of D_FlipFlop is
begin
process(D,C)
begin
if(C'event and C='1') then
if(D='0') then
Q<='0';
Qnot<= '1';
else
Q<='1';
Qnot<='0';
end if;
end if;
end process;
end Behavioral;
Waveform:
39
JK Flip Flop
Code:
entityJK_FlipFlop is
Port ( J : in std_logic;
K : in std_logic;
C : in std_logic;
Q :inoutstd_logic;
Qnot :inoutstd_logic);
endJK_FlipFlop;
architecture Behavioral of JK_FlipFlop is
begin
process(J,K,C)
begin
if(C'event and C='1') then
if(J='0' and K ='1')then
Q<='0';
Qnot<='1';
elsif(J='1' and K='0') then
Q<='1';
Qnot<='0';
elsif(J='1' and K ='1') then
Q<= Qnot;
Qnot<= Q;
end if;
end if;
end process;
end Behavioral;
Waveform:
40
T Flip Flop
Code:
entity tff is
Port ( T : in std_logic;
C : in std_logic;
Q : inout std_logic;
QNOT : inout std_logic);
end tff;
architecture Behavioral of tff is
begin
process(T,C)
begin
Q<='1';
QNOT<=not Q;
if(C'event and C='1') then
if(T='1')then
Q<=not Q;
QNOT <= not Q;
end if;
end if;
end process;
end Behavioral;
Waveform:
41
UP Counter
Code:
entityUP_Cnt is
Port ( C : in std_logic;
clear : in std_logic;
Q : out std_logic_vector(2 downto 0));
endUP_Cnt;
architecture Behavioral of UP_Cnt is
Signal tmp :std_logic_vector(2 downto 0);
Begin
process(clear,C)
begin
if(clear = '1')then
tmp<= "000";
elsif (C'event and C='1') then
tmp<= tmp+1;
end if;
end process;
Q<=tmp;
end Behavioral;
Waveform:
42
Down Counter:
Code:
entity Dn_Cnt is
Port ( C : in std_logic;
clear : in std_logic;
Q : out std_logic_vector(2 downto 0));
endDn_Cnt;
architecture Behavioral of Dn_Cnt is
Signal tmp :std_logic_vector(2 downto 0);
begin
process(clear,C)
begin
if(clear = '1')then
tmp<= "111";
elsif (C'event and C='1') then
tmp<= tmp-1;
end if;
end process;
Q<=tmp;
end Behavioral;
Waveform:
43
DAY 6: 26 . 02 .2015
Full adder using two half adders (Structural approach)
Code:
entityFull_Adder_s is
Port ( x : in std_logic;
y : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic);
endFull_Adder_s;
architecture Structural of Full_Adder_s is
componentHalf_adder is
Port ( A : in std_logic;
B : in std_logic;
S : out std_logic;
C : out std_logic);
end component;
signali,j,k : std_logic;
begin
ha1: Half_adder port map (x,y,i,j);
ha2: Half_adder
port map (i,cin,sum,k);
cout<= k or j;
end Structural;
Schematic Diagram:
44
Waveform:
Waveform:
45
Waveform
46
Waveform
47
8to1 MUX(Structural)
Code:
entity mux81 is
Port ( I : in std_logic_vector(7 downto 0);
S : in std_logic_vector(2 downto 0);
Y : out std_logic);
end mux81;
architecture Structural of mux81 is
component Mux4_dataflow is
Port ( I : in std_logic_vector(3 downto 0);
S : in std_logic_vector(1 downto 0);
Y : out std_logic);
end component;
component mux_2 is
Port ( I : in std_logic_vector(1 downto 0);
S : in std_logic;
Y : out std_logic);
end component;
signalya: std_logic_vector(1 downto 0);
begin
mux1 : Mux4_dataflow port map (I(3 downto 0),S(1 downto 0),ya(0));
mux2 : Mux4_dataflow port map (I(7 downto 4),S(1 downto 0),ya(1));
mux3 : mux_2 port map (ya(1 downto 0),S(2),Y);
end Structural;
RTL Schematic:
48
Waveform:
49
Waveform:
50