Recongurable computing

2.1 Tredennicks Classication

Recongurable computing is a computer architecture combining some of the exibility of software

with the high performance of hardware by processing with very exible high speed computing fabrics
like eld-programmable gate arrays (FPGAs). The
principal dierence when compared to using ordinary
microprocessors is the ability to make substantial changes
to the datapath itself in addition to the control ow. On
the other hand, the main dierence with custom hardware, i.e. application-specic integrated circuits (ASICs)
is the possibility to adapt the hardware during runtime by
loading a new circuit on the recongurable fabric.

The fundamental model of the recongurable computing machine paradigm, the data-stream-based anti machine is well illustrated by the dierences to other machine paradigms that were introduced earlier, as shown
by Nick Tredennick's following classication scheme of
computing paradigms (see Table 1: Nick Tredennicks
Paradigm Classication Scheme). [7]

2.2 Hartensteins Xputer

Main article: Xputer

Computer scientist Reiner Hartenstein describes recongurable computing in terms of an anti-machine that, according to him, represents a fundamental paradigm shift
away from the more conventional von Neumann machine.
[8]
Hartenstein calls it Recongurable Computing Paradox, that software-to-congware migration (software-toFPGA migration) results in reported speed-up factors of
up to more than four orders of magnitude, as well as a
reduction in electricity consumption by up to almost four
orders of magnitudealthough the technological parameters of FPGAs are behind the Gordon Moore curve by
about four orders of magnitude, and the clock frequency
is substantially lower than that of microprocessors. This
paradox is due to a paradigm shift, and is also partly explained by the Von Neumann syndrome (Von Neumann
bottleneck).

History

The concept of recongurable computing has existed

since the 1960s, when Gerald Estrin's landmark paper
proposed the concept of a computer made of a standard
processor and an array of recongurable hardware.[1][2]
The main processor would control the behavior of the recongurable hardware. The latter would then be tailored
to perform a specic task, such as image processing or
pattern matching, as quickly as a dedicated piece of hardware. Once the task was done, the hardware could be adjusted to do some other task. This resulted in a hybrid
computer structure combining the exibility of software
with the speed of hardware; unfortunately this idea was
far ahead of its time in needed electronic technology.
In the 1980s and 1990s there was a renaissance in this
area of research with many proposed recongurable architectures developed in industry and academia,[3] such
as: Copacobana, Matrix, GARP,[4] Elixent, PACT
XPP, Silicon Hive, Montium, Pleiades, Morphosys,
PiCoGA.[5] Such designs were feasible due to the constant progress of silicon technology that let complex
designs be implemented on one chip. The worlds
rst commercial recongurable computer, the Algotronix
CHS2X4, was completed in 1991. It was not a commercial success, but was promising enough that Xilinx (the
inventor of the Field-Programmable Gate Array, FPGA)
bought the technology and hired the Algotronix sta.[6]

3 High-performance computing
High-Performance
Recongurable
Computing
(HPRC) is a computer architecture combining recongurable computing-based accelerators like FPGAs with
CPUs or multi-core microprocessors.
The increase of logic in an FPGA has enabled larger
and more complex algorithms to be programmed into the
FPGA. The attachment of such an FPGA to a modern
CPU over a high speed bus, like PCI express, has enabled the congurable logic to act more like a coprocessor
rather than a peripheral. This has brought recongurable
computing into the high-performance computing sphere.
Furthermore by replicating an algorithm on an FPGA or
the use of a multiplicity of FPGAs has enabled recongurable SIMD systems to be produced where several com-

Theories
1

5 CURRENT SYSTEMS

putational devices can concurrently operate on dierent tion can be divided into two groups:[15]
data, which is highly parallel computing.
This heterogeneous systems technique is used in computing research and especially in supercomputing.[9] A 2008
paper reported speed-up factors of more than 4 orders
of magnitude and energy saving factors by up to almost 4
orders of magnitude.[10] Some supercomputer rms oer
heterogeneous processing blocks including FPGAs as accelerators. One research area is the twin-paradigm programming tool ow productivity obtained for such heterogeneous systems.[11]

dynamic partial reconguration, also known as an

active partial reconguration - permits to change the
part of the device while the rest of an FPGA is still
running;
static partial reconguration - the device is not active
during the reconguration process. While the partial
data is sent into the FPGA, the rest of the device
is stopped (in the shutdown mode) and brought up
after the conguration is completed.

The US National Science Foundation has a center for high-performance recongurable computing
(CHREC).[12] In April 2011 the fourth Many-core and
Recongurable Supercomputing Conference was held in 4.1 Xilinx
Europe.[13]
There are two styles of partial reconguration of FPGA
Commercial High Performance recongurable computdevices from Xilinx: module-based and dierence-based.
ing systems are beginning to emerge with the announcement of IBM integrating FPGAs with its POWER
Module-based partial reconguration permits to reprocessor.[14]
congure distinct modular parts of the design. To
ensure the communication across the recongurable
module boundaries, special bus macros ought to be
4 Partial re-conguration
prepared. It works as a xed routing bridge that connects the recongurable module with the rest part
of the design. Module-based partial reconguration
Partial re-conguration is the process of changing a
requires to perform a set of specic guidelines durportion of recongurable hardware circuitry while the
ing at the stage of design specication. Finally for
other part is still running/operating. Field programmable
each recongurable module of the design, separate
gate arrays are often used as a support to partial recongbit-stream is created. Such a bit-stream is used to
uration.
perform the partial reconguration of an FPGA.
Electronic hardware, like software, can be designed modularly, by creating subcomponents and then higher-level
Dierence-based partial reconguration can be used
components to instantiate them. In many cases it is useful
when a small change is made to the design. It is esto be able to swap out one or several of these subcompopecially useful in case of changing LUT equations or
nents while the FPGA is still operating.
dedicated memory blocks content. The partial bitNormally, reconguring an FPGA requires it to be held
stream contains only information about dierences
in reset while an external controller reloads a design onto
between the current design structure (that resides
it. Partial reconguration allows for critical parts of the
in the FPGA) and the new content of an FPGA.
design to continue operating while a controller either on
There are two ways of dierence-based reconguthe FPGA or o of it loads a partial design into a recongration known as a front-end and back-end. The rst
urable module. Partial reconguration also can be used to
one is based on the modication of the design in the
save space for multiple designs by only storing the partial
hardware description languages (HDLs). It is clear
designs that change between designs.
that such a solution requires full repeating of the
A common example for when partial reconguration
synthesis and implementation processes. The backwould be useful is the case of a communication device.
end dierence-based partial reconguration permits
If the device is controlling multiple connections, some of
to make changes at the implementation stage of the
which require encryption, it would be useful to be able
prototyping ow. Therefore there is no need for reto load dierent encryption cores without bringing the
synthesis of the design. The usage of both methods
whole controller down.
(either front-end and back-end) leads to creation of
a partial bit-stream that can be used for a partial rePartial reconguration is not supported on all FPGAs. A
conguration of the FPGA.
special software ow with emphasis on modular design
is required. Typically the design modules are built along
well dened boundaries inside the FPGA that require the
design to be specially mapped to the internal hardware.
From the functionality of the design, partial recongura-

5 Current systems

5.4

COPACOBANA

3
RT and FPGA programming.

5.4 COPACOBANA
A fully FPGA-based computer addressing several markets is the COPACOBANA, the Cost Optimized Codebreaker and Analyzer and its successor RIVYERA.
A spin-o company SciEngines GmbH[20] of the
COPACOBANA-Project of the Universities of Bochum
and Kiel in Germany currently sells the fourth generation
of fully FPGA based computers. Well published congurations utilize for example 128 FPGAs per single computer making COPACOBANA and RIVYERA a well
known reference platform for cryptanalysis and bioinformatics.

6 Comparison of systems
An FPGA board is being used to recreate the Vector-06C computer

5.1

Computer emulation

With the advent of aordable FPGA boards, there is

an ever increasing number of students and hobbyists
projects that seek to recreate vintage computers or implement more novel architectures. [16] [17] [18] .[19] Such
projects are built with recongurable hardware (FPGAs),
and some devices support emulation of multiple vintage
computers using a single recongurable hardware (COne).

5.2

Mitrionics

Mitrionics has developed a SDK that enables software

written using a single assignment language to be compiled and executed on FPGA-based computers. The
Mitrion-C software language and Mitrion processor enable software developers to write and execute applications on FPGA-based computers in the same manner as
with other computing technologies, such as graphical processing units (GPUs), cell-based processors, parallel
processing units (PPUs), multi-core CPUs, and traditional single-core CPU clusters. (out of business)

5.3

National Instruments

National Instruments have developed a hybrid embedded

computing system called CompactRIO. CompactRIO
systems consist of recongurable chassis housing the
user-programmable FPGA, hot swappable I/O modules,
real-time controller for deterministic communication and
processing, and graphical LabVIEW software for rapid

As an emerging eld, classications of recongurable architectures are still being developed and rened as new
architectures are developed; no unifying taxonomy has
been suggested to date. However, several recurring parameters can be used to classify these systems.

6.1 Granularity
The granularity of the recongurable logic is dened as
the size of the smallest functional unit (congurable logic
block, CLB) that is addressed by the mapping tools. High
granularity, which can also be known as ne-grained, often implies a greater exibility when implementing algorithms into the hardware. However, there is a penalty associated with this in terms of increased power, area and
delay due to greater quantity of routing required per computation. Fine-grained architectures work at the bit-level
manipulation level; whilst coarse grained processing elements (recongurable datapath unit, rDPU) are better
optimised for standard data path applications. One of
the drawbacks of coarse grained architectures are that
they tend to lose some of their utilisation and performance if they need to perform smaller computations than
their granularity provides, for example for a one bit add
on a four bit wide functional unit would waste three bits.
This problem can be solved by having a coarse grain array (recongurable datapath array, rDPA) and a FPGA
on the same chip.
Coarse-grained architectures (rDPA) are intended for the
implementation for algorithms needing word-width data
paths (rDPU). As their functional blocks are optimized
for large computations and typically comprise word wide
arithmetic logic units (ALU), they will perform these
computations more quickly and with more power eciency than a set of interconnected smaller functional
units; this is due to the connecting wires being shorter, resulting in less wire capacitance and hence faster and lower

power designs. A potential undesirable consequence of

having larger computational blocks is that when the size
of operands may not match the algorithm an inecient
utilisation of resources can result. Often the type of applications to be run are known in advance allowing the
logic, memory and routing resources to be tailored to enhance the performance of the device whilst still providing
a certain level of exibility for future adaptation. Examples of this are domain specic arrays aimed at gaining
better performance in terms of power, area, throughput
than their more generic ner grained FPGA cousins by
reducing their exibility.

REFERENCES

6.4 Routing/interconnects
The exibility in recongurable devices mainly comes
from their routing interconnect. One style of interconnect made popular by FPGAs vendors, Xilinx and Altera
are the island style layout, where blocks are arranged in
an array with vertical and horizontal routing. A layout
with inadequate routing may suer from poor exibility and resource utilisation, therefore providing limited
performance. If too much interconnect is provided this
requires more transistors than necessary and thus more
silicon area, longer wires and more power consumption.

7 See also
6.2

Rate of reconguration

Conguration of these recongurable systems can happen

at deployment time, between execution phases or during
execution. In a typical recongurable system, a bit stream
is used to program the device at deployment time. Fine
grained systems by their own nature require greater conguration time than more coarse-grained architectures
due to more elements needing to be addressed and programmed. Therefore more coarse-grained architectures
gain from potential lower energy requirements, as less
information is transferred and utilised. Intuitively, the
slower the rate of reconguration the smaller the energy
consumption as the associated energy cost of reconguration are amortised over a longer period of time. Partial
re-conguration aims to allow part of the device to be reprogrammed while another part is still performing active
computation. Partial re-conguration allows smaller recongurable bit streams thus not wasting energy on transmitting redundant information in the bit stream. Compression of the bit stream is possible but careful analysis
is to be carried out to ensure that the energy saved by
using smaller bit streams is not outweighed by the computation needed to decompress the data.

6.3

Host coupling

Often the recongurable array is used as a processing

accelerator attached to a host processor. The level of
coupling determines the type of data transfers, latency,
power, throughput and overheads involved when utilising the recongurable logic. Some of the most intuitive
designs use a peripheral bus to provide a coprocessor like
arrangement for the recongurable array. However, there
have also been implementations where the recongurable
fabric is much closer to the processor, some are even implemented into the data path, utilising the processor registers. The job of the host processor is to perform the
control functions, congure the logic, schedule data and
to provide external interfacing.

Computing with Memory

Glossary of recongurable computing
High-performance recongurable computing
iLAND project
M-Labs
Mitrionics
One chip MSX
Partial re-conguration
PipeRench
PSoC
Sprinter

8 References
[1] Estrin, G (2002). Recongurable computer origins:
the UCLA xed-plus-variable (F+V) structure computer. IEEE Ann. Hist. Comput 24 (4): 39.
doi:10.1109/MAHC.2002.1114865.
[2] Estrin, G., Organization of Computer SystemsThe
Fixed Plus Variable Structure Computer, Proc. Western
Joint Computer Conf., Western Joint Computer Conference, New York, 1960, pp. 3340.
[3] C. Bobda: Introduction to Recongurable Computing:
Architectures; Springer, 2007
[4] Hauser, John R. and Wawrzynek, John, Garp: A MIPS
Processor with a Recongurable Coprocessor, Proceedings of the IEEE Symposium on Field-Programmable
Custom Computing Machines (FCCM '97, April 1618,
1997), pp. 2433.
[5] Campi, F.; Toma, M.; Lodi, A.; Cappelli, A.; Canegallo,
R.; Guerrieri, R., A VLIW processor with recongurable
instruction set for embedded applications, Solid-State
Circuits Conference, 2003. Digest of Technical Papers.
ISSCC. 2003 IEEE International , vol., no., pp. 250-491
vol.1, 2003

9.2

Partial re-conguration

[6] Algotronix History

[7] N. Tredennick: The Case for Recongurable Computing;
Microprocessor Report, Vol. 10 No. 10, 5 August 1996,
pp 2527.
[8] Hartenstein, R. 2001. A decade of recongurable computing: a visionary retrospective. In Proceedings of the
Conference on Design, Automation and Test in Europe
(DATE 2001) (Munich, Germany). W. Nebel and A. Jerraya, Eds. Design, Automation, and Test in Europe. IEEE
Press, Piscataway, NJ, 642649.
[9] N. Voros, R. Nikolaos, A. Rosti, M. Hbner (editors):
Dynamic System Reconguration in Heterogeneous Platforms - The MORPHEUS Approach; Springer Verlag,
2009
[10] Tarek El-Ghazawi et al. (February 2008). The promise
of high-performance recongurable computing. IEEE
Computer 41 (2): 6976. doi:10.1109/MC.2008.65.
[11] Esam El-Araby; Ivan Gonzalez; Tarek El-Ghazawi (January 2009). Exploiting Partial Runtime Reconguration
for High-Performance Recongurable Computing. ACM
Transactions on Recongurable Technology and Systems
(TRETS) 1 (4): 123. doi:10.1145/1462586.1462590.
[12] NSF center for High-performance Recongurable Computing. ocial web site. Retrieved August 19, 2011.
[13] Many-Core and Recongurable Supercomputing Conference. ocial web site. 2011. Retrieved August 19,
2011.

5
S. Hauck and A. DeHon, Recongurable Computing:
The Theory and Practice of FPGA-Based Computing, Morgan Kaufmann, 2008.
J. Henkel, S. Parameswaran (editors): Designing
Embedded Processors. A Low Power Perspective;
Springer Verlag, March 2007
J. Teich (editor) et al.: Recongurable Computing
Systems. Special Topic Issue of Journal it Information Technology, Oldenbourg Verlag, Munich.
Vol. 49(2007) Issue 3
T.J. Todman, G.A. Constantinides, S.J.E. Wilton,
O. Mencer, W. Luk and P.Y.K. Cheung, Recongurable Computing: Architectures and Design Methods, IEEE Proceedings: Computer & Digital Techniques, Vol. 152, No. 2, March 2005, pp. 193208.
A. Zomaya (editor): Handbook of Nature-Inspired
and Innovative Computing: Integrating Classical
Models with Emerging Technologies; Springer Verlag, 2006
J. M. Arnold and D. A. Buell, VHDL programming on Splash 2, in More FPGAs, Will
Moore and Wayne Luk, editors, Abingdon EE &
CS Books, Oxford, England, 1994, pp. 182
191.
(Proceedings,International Workshop on
Field-Programmable Logic, Oxford, 1993.)

[14] Altera and IBM Unveil FPGA-Accelerated POWER

Systems. HPCwire. 2014-11-17. Retrieved 2014-1214.

J. M. Arnold, D. A. Buell, D. Hoang, D. V. Pryor,

N. Shirazi, M. R. Thistle, Splash 2 and its applications, Proceedings, International Conference on
Computer Design, Cambridge, 1993, pp. 482486.

[15] Winiewski, Remigiusz (2009). Synthesis of compositional microprogram control units for programmable devices. Zielona Gra: University of Zielona Gra. p. 153.
ISBN 978-83-7481-293-1.

D. A. Buell and Kenneth L. Pocek, Custom computing machines: An introduction, The Journal of
Supercomputing, v. 9, 1995, pp. 219230.

[16] Apple2 FPGA. Retrieved 6 Sep 2012.

[17] FPGA Apple. Retrieved 6 Sep 2012.
[18] Niklaus Wirth. The Design of a RISC Architecture and
its Implementation with an FPGA (PDF). Retrieved 6
Sep 2012.
[19] Jan Gray. Designing a Simple FPGA-Optimized RISC
CPU and System-on-a-Chip (PDF). Retrieved 6 Sep
2012.
[20] SciEngines website

Further reading

9.1

Recongurable computing

Cardoso, Joo M. P.; Hbner, Michael (Eds.),

Recongurable Computing: From FPGAs to Hardware/Software Codesign, Springer, 2011.

9.2 Partial re-conguration

OpenPR: An open source partial reconguration
tool ow
ReSim: an open source library for the RTL simulation of partial reconguration and partially recongurable designs
GoAhead: an alternative but more exible partial
reconguration tool chain
Website of the ReCoBus-Builder project for easily
implementing complex recongurable systems
Website of the DRESD (Dynamic Recongurability
in Embedded System Design) research project
http://www.dagstuhl.de/Materials/Files/06/06141/
AutoVision:
06141.StecheleWalter.Slides.pdf
Dynamically Recongurable SoC

11

10

See also

FPGA: Field Programmable Gate Array

11

External links

Introduction to Dynamic Partial Reconguration

Partial Reconguration by Xilinx
Partial Reconguration by Altera

EXTERNAL LINKS

12
12.1

Text and image sources, contributors, and licenses

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