Reg.

No:

B.E./B.Tech. DEGREE EXAMINATION, November - 2009

Second Year - Third Semester
CS2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

Model Question Paper - I

(Common to CSE and IT)
(Regulation 2008)
Time: Three Hours

Maximum Marks: 100

ANSWER ALL QUESTIONS
Part A (10 x 2 = 20 marks)

1. Convert the following number from one base to other.

/
k
t

(354.52)16 = ( )10
(100)10 = ( )16.

.
e
b

2. What are the different ways to represent a negative number?

u
t
e

3. What is logic synthesis?

4. What is the need for code conversion? Give two commonly used codes.

s
c
/

5. What is decoder? Draw the block diagram and the truth table for 2 to 4 decoder
6. Give some applications of multiplexer.

/
:
p

7. Convert a JK flip flop to T flip flop.

8. What is the maximum range of a memory that can be accessed using 10 address lines?

t
t
h

9. What is a hazard?

10. What are the assumptions that must be made for fundamental mode circuit?
Part B (5 x 16 = 80 marks)
11 (a) What is the advantage of using Tabulation method? Determine the prime implicants
of the following function using Tabulation method.

(16)

F(w, x, y, z) = (1, 4, 6, 7, 8, 9, 10, 11, 15)

(or)
(b) (i) Explain about common postulates used to formulate various algebraic
structures.

(12)

(ii) Given the following Boolean function

F = AC + AB + ABC + BC
Express it in sum of minterms and find the minimal SOP expression.

http://csetube.weebly.com/

(4)

12 (a) Design a BCD to 7 segment decoder.

(16)
(or)

(b) With suitable block diagram explain the operation of BCD adder.

(16)

13 (a) Define decoder. Design a 3 to 8 decoder. With suitable block diagram explain how a
4 to 16 decoder can be formed by using the same.

(16)

(or)
(b) Construct a Full adder and write a HDL program module for the same.
14 (a) Explain the different types of shift registers with neat diagram.

(16)
(16)

(or)
(b) Design a sequence detector to detect the sequence 101011.

(16)

15 (a) An asynchronous sequential circuit is described by the following excitation and

output function.
X = (Y1Z1W2) + (Y1Z1W2)

/
k
t

S = X
(i)

.
e
b

Draw the logic diagram of the circuit.

(ii) Derive the transition table and output map.

tu

(iii) Describe the behavior of the circuit

(16)

e
s
c
(or)

(b) Explain essential, static and dynamic hazards in digital circuit. Give hazard-free

/
/
:

realization for the Boolean function.

F(I, J, K, L) = (1, 3, 4, 5, 6, 7, 9, 11, 15)

p
t
t

http://csetube.weebly.com/

(16)

Reg.No:

B.E./B.Tech. DEGREE EXAMINATION, November - 2009

Second Year - Third Semester
CS2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

Model Question Paper - II

(Common to CSE and IT)
(Regulation 2008)
Time: Three Hours

Maximum Marks: 100

ANSWER ALL QUESTIONS
Part A (10 x 2 = 20 marks)

1. Simplify the following Boolean expression to a minimum number of literals:

AB+ACD+ABD+ (AB)CD

/
k
t

2. Simplify the following Boolean function by Karnaugh map method:

F (A, B, C, D) = m (1, 5, 9, 12, 13, 15).

.
e
b

3. Define combinational circuit.

u
t
e

4. Draw a 2 to 1 multiplexer circuit.

5. What is a priority encoder?

s
c
/

6. State a limitation of RS flip flop.

7. What is a binary counter?

/
:
p

8. What are the models used to represent clocked sequential circuits?

9. What are difference between PLA and PAL?

t
t
h

10. What are assumptions made for pulse mode circuit?

Part B (5 x 16 = 80 marks)

11 (a) Simplify the following Boolean Function F together with dont care condition using
Karnaugh map method.
(i) F(A, B, C, D) = m(0, 6, 8,13, 14), d(A, B, C, D) = m(2, 4, 10)

(6)

(ii) F(A, B, C, D) = m(0, 2, 4, 5, 8, 14, 15), d(A, B, C, D) = m(7, 10, 13)

(5)

(iii) F(A, B, C, D) = m(4, 6, 7, 8, 12, 15), d(A, B, C, D) = m(2, 3, 5, 10, 11, 14)

(5)

(or)
(b) Simplify the following Boolean expressions to a minimum number of literals.
(i) ABC+ABC+AB

(3)

(ii) ABC+AC+B

(3)

(iii) (A+B)(A+B)

(3)

http://csetube.weebly.com/

(iv) BC(AD+AD)+AB

(3)

(iv) (A+B+AB)+(AB+AC+BC)

(4)

12 (a) (i) Design a combinational circuit to convert gray code to BCD.

(ii) What are the design procedures to design a combinational circuit?

(12)
(4)

(or)
(b) (i) Design a combinational circuit to convert gray code to Excess- 3 code.
(ii) Design a 3-bit adder

(12)
(4)

13 (a) (i) Implement the following Boolean function using multiplexer.

F(W, X, Y, Z) = (1, 2, 3, 6, 7, 8, 11, 12, 14)

(8)

(ii) A combinational circuit is defined by the functions

F1= (1, 3, 5)

/
k
t

F2= (5, 6, 7)

.
e
b

Implement the circuit with a PLA having 3 inputs, 3 product terms and two
outputs.

u
t
e

(or)

(b) Design a BCD adder circuit and write a HDL program module for the same

s
c
/

14 (a) Design a synchronous BCD counter using JK flip-flop.

/
:
p

(8)

(12)
(16)

(or)

(b) (i) Write a verilog description for JK negative edge triggered flip flop with

tt

clock CLK

(10)

(ii) Explain the characteristic table of JK flip flop.

(6)

15 (a) Develop the state diagram and primitive flow table for a logic system that has 2
inputs, x and y and an output z. And reduce primitive flow table. The behavior of the
circuit is stated as follows. Initially x=y=0. Whenever x=1 and y=0 then z=1,
whenever x=0 and y=1 then z=0. When x=y=0 or x=y=1 no change in z, it remains in
the previous state. The logic system has edge triggered inputs without having a clock.
The logic system changes state on the rising edges of the 2 inputs. Static input values
are not to have any effect in changing the z output.

(16)

(or)
(b) (i) What is the objective of state assignment in asynchronous circuit? Give hazard-free
realization for the Boolean functions.
F(A, B, C, D) = M(0, 2, 6, 7, 8, 10, 12)
(ii) Summarize the design procedure for asynchronous sequential circuit.

http://csetube.weebly.com/

(8)
(8)

Reg.No:

B.E./B.Tech. DEGREE EXAMINATION, November - 2009

Second Year - Third Semester
CS2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

Model Question Paper - III

(Common to CSE and IT)
(Regulation 2008)
Time: Three Hours

Maximum Marks: 100

ANSWER ALL QUESTIONS
Part A (10 x 2 = 20 marks)

1. Find the 2s complement and 1s complement of 101101.

2. Simplify X1+X1X2.

/
k
t

3. Draw a 1 to 2 demultiplexer circuit.

4. List the important features of HDL?

.
e
b

5. What are the functions of encoders and decoders?

u
t
e

6. What is a multiplexer?

7. How many flip-flops are required for designing synchronous MOD50 counter?

s
c
/

8. What is shift Register? List the types.

9. Define Race condition. How can it be avoided?

/
:
p

10. Define Hazards.

tt

Part B (5 x 16 = 80 marks)

11 (a) Using Tabulation method simplify the Boolean function.

F(V, W, X, Y, Z) = (0, 1, 8, 11, 12, 15, 20, 21, 22, 24, 29, 31) which has the dont
care conditions d(9, 18, 30).

(16)
(or)

(b) (i) Simplify the Boolean function using map method:

F(W, X, Y, Z) = (0, 2, 4, 6, 8, 10, 12, 14)

(10)

(ii) Perform subtraction on the following numbers using the 9s complement of the
subtrahend.
(1) 5763 3145.
(2) 59 9876.

(6)

(3) 5200 561.

12 (a) Design a four bit magnitude comparator to compare two 4-bit numbers.

http://csetube.weebly.com/

(16)

(or)

(b) Construct a combinational circuit to convert the given BCD into an Excess-3 code. For
example when the input to the circuit is 0110, then the circuit should generate the
output as 1001.

(16)

13 (a) Construct a full adder circuit and write a HDL program module for the same.

(16)

(or)
(b) (i) Implement the following function with a multiplexer
F(A, B, C) = (1, 2, 4, 5)

(8)

(ii) What is microprogrammed control unit? Explain the different types of

ROM.

(8)

14 (a) Design a binary up-down counter.

/
k
t

(or)

e.

(b) (i) Summarize the design procedure for synchronous sequential circuit.
(ii) Reduce the following state diagram

b
u
t

(16)

(6)
(10)

e
s
c

/
/
:

p
t
t

15 (a) Design an asynchronous sequential circuit with two inputs x1 and x2 and one output
z. Initially both the inputs are equal to 0. When x1 or x2 becomes 1, z becomes 1.
When second input also becomes 1, z becomes 0. The output stays at 0 until circuit
goes back to initial state.

(16)
(or)

(b) Discuss in detail the static hazards.

http://csetube.weebly.com/

(16)