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High Speed Interconnects for System on Chip

Dinesh Sharma
dinesh@ee.iitb.ac.in
Department Of Electrical Engineering
Indian Institute Of Technology, Bombay

March 4, 2015

Concept of Inductive Peaking

On-chip interconnects can be


modeled as distributed RC which is
essentially a low pass filter.

Bandwidth enhancement techniques


used in RF amplifiers can be
employed for bandwidth
enhancement on interconnects

Inductive Peaking: Line termination


circuit exhibits inductive input
impedance

Shows enhancement of about


500MHz in 3dB bandwidth.

R0

R0

R0

R0
L

DRIVER
C0

C0

C0

C0
RL

Bandwidth Enhancement Vs Load Inductance

For a given line length, the amount


of bandwidth enhancement is a
function of inductance and load
resistance.

Significant bandwidth enhancement


can be achieved for a wide range of
inductance values greater than
Lpeak .

The required inductance for


significant enhancement in
bandwidth is a few hundreds of nano
Henries !!

An active inductor is required

Beta Multiplier: A Gyrator

Vref

v
Mp1
i1
Mn1

The Beta Multiplier essentially forms a


gyrator circuit with two Gm elements
connected back to back along with the
parasitic capacitance of the transistors.

So Beta Multiplier Circuits can exhibit


inductive input impedance for some
frequency range if designed properly.

Mp2
v1

v2

i2
Mn2

Beta Multiplier: Input Impedance

Zin =

1 =

{(1 2 + k2 3 )s2 + (1 + 2 + k(3 + 2 ))s + 1 + k }


{(gmp1 + R13 ){(1 + 1 s)(1 + 2 s)(1 + 4 s)}}

Cg1
gmn1

3 = Cg3 rop1
=

gmp1 /gmp2
gmn1 /gmn2

Rin =

2 =
4 =

Cg2
gmp2
Cg3
gmp1

R1 =

R3 = rop1
k=

1
gmn1 rop1
1
gmp1 + rop1

(1 ) +

1
gmn1

R1
R3

i1 = gmp1 (vint - vg2)


int

i1
ro_p1

1/gmp2

Cg3
Cg1

i2
1/gmn1

Cg2

i2 = gmn2 vg1

Beta Multiplier: Equivalent Circuit

Relative location of poles and zeros determine nature of


impedance (inductive of capacitive)

If the first zero occurs a decade prior to the first pole, input
impedance is inductive

Leff

=
+

gmn11rop1 > 0.9 and any two time constants being equal
ensures that a zero occurs a decade prior to the first pole

Cg1
Cg2
rop1
+
gmp1 rop1 + 1 gmn1 gmp2

Cg2
Cg3
+
gmp2 gmn1 rop1 gmn1 gmp1 rop1
(1

) + gmn11rop1
1
gmp1 + rop1

Reff

Ceff

= KCgx

Zin

Req
Ceq
Leq

Current Mode Receiver Circuit with Beta Multiplier

Effective impedance offered by the receiver is


equal to the parallel combination of the
impedance offered by individual beta multipliers.

Voltage at input node swings around Vref . Small


voltage swing on the line is sensed and
amplified by the inverting amplifier.

Vref is generated by shorting the input and


output of an inverter to ensure that the value of
Vref is the same as switching threshold of
receiver amplifier across all process corners.

Vdd
Mp11

Source Type
Mp22 Beta Mult.

Mn11

Mn22 Inv Amp

Input
Vref
Mp1

Mp2

Mn1

Mn2

Sink Type
Beta Mult.

rout of Vref generation circuit comes in series with beta


multiplier Zin and hence beta multiplier has to be sized
accordingly.

Vref generation circuit consumes static power.

Simulation Results
Performance Comparison of three signaling schemes (line=6
mm, Power measured at 1Gbps)
Signaling
Scheme
CMS-BMul(30 mV)[1]
CMS-Diode-CC(30 mV)[2]
Voltage Mode

Delay
(ps)
420
500
1000

Throughput
(Gbps)
2.56
2.45
2.85

Power
( W )
310
380
3000

Area
(m2 )
2.00
2.00
12.53

Inductive termination gives 16% improvement in delay and


about 18 % improvement in power compared to current
mode with diode termination.

Compared to voltage mode, it offers more than 50 %


improvement in delay at an order of magnitude lower
power.

[1] M Dave et. al., ISLPED 2008, [2] V. Venkatraman et. al. ISQED 2005

Concept of Dynamic Over-driving/Pre-emphasis

Current mode transmission can be speeded up by using


high drive current.

However, this increases static power consumption.

One possible solution is to dump high drive current only


when the state of the line needs to be changed from 0 to 1
or from 1 to 0.

When the line remains at 1 or 0 from one bit to the next, we


use a small drive current to maintain the line at the
required voltage.

This is called Dynamic Over Driving.

Dynamic Over-driving essentially means amplifying high


frequency components of the input signal

Possible implementation of Dynamic Over-driving

Steady State (Weak)


Driver

The p channel driver gate is low (enabled)


when the input is 1.

As the line reaches VDD VTp , the upper


p channel transistor turns off, restricting
line voltage swing.

Similarly the n channel driver transistor is


enabled when the input is 0 and the lower
transistor turns off when the input
approaches VTn during discharge.

VDD
Swing Control (High)
p Drive
Input
n Drive
Swing Control (Low)

A. Katoch et. al. ESSCIRC, 2005

Possible implementation of Dynamic Over-driving

Dynamic (Strong)
Driver
VDD
Input

Wire

The feedback inverter acts as an inverting


amplifier converting low swing logic levels on
the wire to full swing (inverted) CMOS logic
level on its output.

Feedback

P channel gate is low (enabled) only when the input is high


AND the line is at 0.

N channel gate is high (enabled) only when the input is low


AND the line is at 1.

Input to the feedback inverter is a low swing level around


VDD /2. Therefore it consumes static power.

Self limiting Strong Driver

Dynamic (Strong)
Driver

P channel driver dumps current to charge


the line.

VDD
Input

Input = 1, Wire voltage < Vm


Inverter output = 1, NAND output = 0, NOR output = 0

Wire

Input = 0, Wire voltage > Vm


Inverter output = 0, NAND output = 1, NOR output = 1

N channel sinks current to discharge the


line.
As soon as low swing logic level on the line = input
Inverter output = input, NAND output = 1, NOR output = 0

Feedback

This disables both drive transistors automatically.

A. Katoch et. al. ESSCIRC, 2005

Dynamic Over-driving with Inductive termination?


Dynamic Over-driving (DOD) and Inductive line termination
both essentially amplify high frequency components of input
signal.

Can we use both?

Current Mode Signaling Schemes with Ideal


Components
Following four current mode signaling schemes were simulated:
CMS Scheme with DOD and Resistive Load
CMS Scheme with Simple Driver and Resistive Load
CMS Scheme Inductive Load
CMS Scheme with DOD and Inductive Load
Implementation details of these circuits are:
Dynamic Over-driving driver is implemented by ideal VCCS
with current wave shape as shown in the figure. Controlling
voltage is input.
Simple driver is implemented as VCCS with square wave
shape. The input current ranging from Iavg to +Iavg .

t +I

(tt )

p
Iavg = peak p static
t
RL = 4k, l = 4H

Comparison of Delay
With Large Overdrive (Ipeak = 500A)

Dynamic over-driving shows 5


improvement in delay over RC

Inductive peaking does not offer


substantial additional advantage when
combined with dynamic over-driving.

Inductive peaking alone shows 25% of


improvement in delay over RC

With Small Overdrive (Ipeak = 50A)

Dynamic Over-driving alone and inductive


peaking alone give nearly the same delay

Inductive peaking along with dynamic


over-driving shows around 20%
improvement in delay over dynamic
over-driving alone

Comparison of Throughput (Eye-opening)

Dynamic over-driving improves


throughput by 5 over RC

Inductive peaking does not offer


substantial additional advantage
when combined with dynamic
over-driving.

Inductive peaking shows throughput


enhancement of 26% over RC

Conclusion: Inductive Peaking vs Dynamic Overdrive

For very high data rate applications, dynamic over-driving


alone should be employed as inductive peaking does not
offer any additional advantages

For low power and low data rate applications, the use of
inductive peaking can give 26% improvement in throughput
over RC

For low power and low data rate applications, the use of
inductive peaking can give 16% improvement in delay over
RC

For low power and low data rate applications, the use of
dynamic overdrive along with inductive peaking can further
improve throughput by 20%

Proposed CMS Scheme with Smart Bias


We propose a Dynamic Overdrive scheme in which both the
strong and the weak drivers use constant current sources
controlled by process aware bias generators.
Strong Dr.

Weak Dr.
Vdd

p Bias Gen

Short
pMOS

Vbp

Long
nMOS
Vdd

Wire

Rx

Output

Delay
Input

n Bias Gen

Vdd
Long
pMOS

RxBias

Vbn

Inv.
Amp

Short
nMOS

There is no feedback inverter in the driver circuit

Bias voltages change in the desired direction to keep the


current through weak and strong drivers the same across
all corners

Simulation Setup

Foundry specified four corner model files and mismatch


model file for Monte Carlo simulations were used.

All the signaling schemes offer the same input capacitance


(equivalent to one minimum sized inverter).

All signaling scheme drive FO4 load.

Line RLC used were: Rline = 244 /mm,


Lline = 1.5nH/mm, Cline = 201fF /mm.

All schemes were designed for a throughput of 2.65Gbps.

Current mode schemes are designed for Ipeak = 500A

Overall Comparison
10000

1.5
1
0.5

Data Rate(Mbps)

800

CMS Power <VM Power

400
200

10

12

10

100
1000
Data Rate(Mbps)

600

Line =1.5mm

200

10

100

(c)
Data Rate = 500 Mbps
X 6.6

400

10000

(e) Data Rate=500 Mbps

150

(f)

4 6 8 10 12 14
Line Length (mm)
Line=6mm

1
0.1

50

0
4 5 6 7 8 9 10
0
Line Length (mm)
DODFpw+RxFb [2]
DODFb+RxFb [1]
2

X8

100

200

(d)

600

4
6
8
10
Line Length (mm)

800

(b)

Line=6mm
1000
125 Mbps

Power (uW)

Data Rate=50 Mbps

Energy (pJ)

(a)

Power (uW)

Power (uW)

Delay (ns)

2.5

0.01
10
100
1000
10000
4 6 8 10 12 14
Data Rate (Mbps)
Line Length (mm)
Proposed
DODFpw+RxBMul [3]
Voltage Mode

40% reduction in delay over voltage-mode.


Linear growth of delay without repeaters
Reduction in power consumption by a factor of 8 for a 6mm
line at 500Mbps

Overall Comparison
10000

1.5
1
0.5

Data Rate(Mbps)

800

CMS Power <VM Power

400
200

10

12

10

100
1000
Data Rate(Mbps)

600

Line =1.5mm

200

10

100

(c)
Data Rate = 500 Mbps
X 6.6

400

10000

(e) Data Rate=500 Mbps

150

(f)

4 6 8 10 12 14
Line Length (mm)
Line=6mm

1
0.1

50

0
4 5 6 7 8 9 10
0
Line Length (mm)
DODFpw+RxFb [2]
DODFb+RxFb [1]
2

X8

100

200

(d)

600

4
6
8
10
Line Length (mm)

800

(b)

Line=6mm
1000
125 Mbps

Power (uW)

Data Rate=50 Mbps

Energy (pJ)

(a)

Power (uW)

Power (uW)

Delay (ns)

2.5

0.01
10
100
1000
10000
4 6 8 10 12 14
Data Rate (Mbps)
Line Length (mm)
Proposed
DODFpw+RxBMul [3]
Voltage Mode

For wires longer than 1.5mm working at data rates more


than 500MHz, the power consumption of the proposed
scheme is less than that of buffer inserted interconnects.
Proposed signaling scheme offers around 40%
improvement in power as compared to other dynamic

Bidirectional Links

In many applications, on-chip buses need to carry signal in both


directions.
For example, the bus between processor and memory, main
processor and floating point multiplier etc.
Often bidirectional buffers with direction control are used for
this.

Limitations of Conventional Bidirectional Buffer

Back-to-Back Connected
Tri-state Buffers
En
En=

En

En

One of the two tri-state buffers is


enabled at a given time

Two transistors in stack increased


sizes of PMOS and NMOS

Delay of a bidirectional repeater is more


than that of a unidirectional buffer

Direction control signal is required by


each repeater
Buffers offer huge load to direction
control signal
Buffers carrying direction control signal
consume additional power

En

Direction
Signal
Wire
Segment

Wire
Segment

Wire
Segment

En

En

En

En

We need a repeaterless Signaling Scheme

The Proposed Current Mode Bidirectional Link

Employs only two bidirectional transceivers, one at each


end of the line.

Direction signal is required only at two ends of the line

The direction control signal can be the same as one of the


control signal or derived from it based on communication
protocol

Assumption: Direction signal (Tx/Rx) is locally available at


both ends before data transmission starts

Proposed Current-Mode Transceiver


Transmitter Part

Receiver Part
Strong
Driver

Short
PMOS

Weak
Driver
Terminator

Vbp
Tx/Rx

Long
NMOS

Inverter
Amplifier

Vbp
Tx/Rx
Tx_ip_1

In
Data

Delay
element

Vbn

out

Wire

Long
PMOS

Tx_ip_0

Tx/Rx
Vbn

Tx/Rx

Short
NMOS

Either the transmitter part or the receiver part is enabled at a


time

Speed-Power of Proposed Bidirectional CMS Scheme


Current-Mode Vs. Voltage-Mode
CMBid

(a)

VMBid

(b)

Power (uW)

10e3 Data Rate=500Mbps

Delay (ns)

2.5
2
1.5
1
0.5
0
2

35%

Line Length (mm)

1.7 lower power for 2mm lines


and 7 lower power for 8mm
line

3 4 5 6 7
Line Length (mm)

Power crossover frequency


100Mbps for 4mm long lines

5 reduction in power at 1Gbps


For lines longer than 2mm
communicating at data-rates
more than 180Mbps, the
proposed scheme consumes
less power than voltage-mode

(d)

Line=4mm

1e3

Crossover
Data Rate (Mbps)

Power (uW)

1e2

100Mbps

1e2

35% improvement in delay for


nearly all line lengths

7x

1e3

(c)

10e3

180

5X

100
Data Rate(Mbps)

1000

CMBid
Power

140
100
60
20
2

VMBid
Power

Line Length (mm)

Designed in 180nm for Vdd =1.8V using nominal Vt devices


Line Characteristics: R=211/mm and C=0.245pF/mm

Effect on Supply Noise


Peak Current Drawn From Supply

68% reduction in peak current and hence contribution to


supply noise is much less

80% reduction in active area

Pre-emphasis - Capacitively coupled

Buffer drives line through a series capacitor.

The series capacitor injects sharp current pulses whenever


it sees a transition at its input. When there is no transition
there is no current through the capacitor. Hence it
performs edge detection
To Line

data

Iline

Vbp

Vbn

time

Pre-emphasis - Capacitively coupled

The current injected into the line is given by I = C dV


dt
By controlling the rise time of the inverter and the
capacitance value we can control the amount of current
injected into the line on transitions
To Line

data

Iline

Vbp

Vbn

time

Model of the Capacitively coupled link


gm
Cs
data

Line
RL
Vcm

The weak driver is modeled as a controlled current source


(gm ).

The main transmitter is modeled as an inverter with an


output impedance Rs

The line is terminated in a resistance RL to the common


mode voltage Vcm

The logic swing on the line is given by gm Vdd 4 RL

We will use this model to investigate this architecture

Design of the capacitively coupled link

gm
Cs
data

Line
RL
Vcm

We can find the transmitter design parameters (RS , gm , C


and RL ) in many ways

We fix gm and RL so as to get a desired logic swing on the


line, with steady state leakage as an additional constraint

RS is chosen sufficiently smaller than the impedance of the


series capacitor at the operating frequency

Design of the capacitively coupled link

gm
Cs
data

Line
RL
Vcm

That leaves design of C and Rs which define the amount


of pre-emphasis

Model the line transfer function analytically and construct its


inverse
Model the transmitter transfer function and equate it to
inverse of the line and solve for the transmitter parameters
An accurate model of the line transfer function is very
elaborate and not invertible
Approximations need to be made and that may result in a
sub-optimal transmitter

Design of the capacitively coupled link

gm
Cs
data

Line
RL
Vcm

We can find the pre-emphasis empirically

Model the line as a multi section RC in a simulation setup


Inject pseudo-random data at the input and monitor the eye
opening at the receiver input
Adjust the pre-emphasis till the eye at the receiver looks
healthy
But response of line depends on the bit sequence and a
random sequence that covers all cases will take very long
to simulate

Optimum amount of pre-emphasis

gm
Cs
data

Line
RL
Vcm

If the pre-emphasis is more than optimum the edges are


amplified more than required. This causes overshoots at
the receiver

If the complementary bit appears when this overshoot is


maximum it may not meet the required noise margin

If the pre-emphasis is less than optimum then we dont get


the maximum possible bandwidth enhancement

Optimum amount of Pre-emphasis

Tests with random bits can be misleading!

We will try to find how the response of the line changes


with pre-emphasis for certain scrupulously chosen vectors
and try to find the optimum pre-emphasis

Worst Case sequences : Pre-emphasis higher than


optimum

...0001000...0001111011111...

Receiver Voltage (mV )

WC1

26mV

WC2

10mV

Worst Case sequences : Pre-emphasis lower than


optimum

Receiver Voltage (mV )

WC1

4mV

...0001000...0001111011111...

WC2

20mV

Worst Case Sequences : Optimum Pre-emphasis

...0001000...0001111011111...

Receiver Voltage (mV )

WC1

15mV

WC2

15mV

time(ns)

Part I
Variation Tolerant Current Mode

Need for Process Variation Tolerance

Current mode signaling derives its advantages over


voltage mode due to the reduced swing on the line.

Careful design is necessary, otherwise small changes in


device parameters can have a disproportionate effect on
the performance of the system.

In modern short channel processes, variations in transistor


parameters are large some of the parameters can vary
by as much as 60%.

we have to design circuits, so that they are robust with


respect to batch-to-batch variations, as well as variations
between devices on the same die.

Batch-to-batch or inter-die variations can shift operating


points and drive strengths.

Intra-die variations cause mismatch in parameters of


transmitter and receiver transistors.

Robustness requirements

Process, Supply Voltage and Temperature variations will


affect the core logic as well as data communication
circuitry.

The requirement for data transmission is therefore not of


complete invariance with respect to PVT variations.

We have to ensure that throughput and delay properties of


the interconnect are at least as good as data generation
and clock rates.

Thus the deterioration in interconnect properties should be


no worse than the deterioration in general logic.

Because global interconnects, by definition, connect


remote points on the die, on chip variations can be of
greater concern.

Effect of common mode voltage mismatch

Ideal

In case of ideal match, small fluctuations


in line voltage are converted to rail to rail
swing by the receiver.

If, however, the mismatch is large, the


small swing on the line may be completely
ignored by the receiver.

It is important, therefore, that the amount


of swing on the line is much more than the
mismatch in common mode voltages.

But high swing will cause power


dissipation.

It is better to have smart bias circuits,


which will reduce mismatch and the need
for a large swing.

VcmRx
Transmitter

Receiver

Misaligned
VcmRx

System parameters affected by variations

Variations in the following parameters have a strong influence


on the performance of the signaling scheme:
1. Ipeak : Peak current supplied by the strong driver during
input transition
2. tp : Duration for which the strong driver is ON
3. V : Line voltage swing at the receiver end in steady state
4. Mismatch between any VCMRx and operating point of an
amplifier

CMS Scheme with Feedback (CMS-Fb)


Strong
Driver

Weak
Driver

VDD
Receiver Eq. Circuit
Wire

Input

RxOut

LineRx

RL

I1
Feedback

Vcm Rx

Wire

NAND/NOR generates pulses to turn-on/off the strong


driver

Input transition the strong driver turns on


line voltage at transmitter end crosses VM of inverter I1
strong driver turns off.

Weak driver supplies Istatic and line voltage swing at


receiver end is VCMRx Istatic RL

A. Katoch et. al. ESSCIRC, 2005

Effect of Inter-die Process Variations on CMS with


feedback
Strong
Driver

Weak
Driver

VDD
Receiver Eq. Circuit
Wire

Input

LineRx

RxOut

RL

+ Vcm Rx

I1
Feedback

Wire

Variations in Ipeak are well compensated due to the


feedback at the driver end.
If the driver is weaker due to process variations, the feed
back system keeps it on for longer till the line reaches the
desired voltage.
This might, however, not be optimum from a power point of
view.

Effect of Intra-die Process Variations on CMS-Fb

VCMRx

VMTx

Line voltage is not constant for


constant low input voltage

During low to high transition


the strong driver is turned off
well before the line voltage
crosses VCMRx

CMS Scheme without Feedback (CMS-Fpw)


Strong
Driver

Weak
Driver

Fixed Width
Pulse Generator

Input

VDD
Receiver Eq. Circuit
Wire

LineRx

RxOut

Delay
RL

Vcm Rx

tp is given by delay element

Less sensitive to intra-die variations

In the skewed corners, sourcing Ipeak and sinking Ipeak are


different, leading to different rise and fall delay

Throughput can degrade significantly in skewed corners

A.Tabrizi et. al. MWSCAS, 2007

Minimizing Process Dependence


To minimize process dependence, we need smart bias circuits
which sense the process corner and adjust the bias to
compensate for variations.
Vdd

Long Channel transistors show relatively less variation


with process compared to Short Channel transistors in
the same process.

We can make use of this difference to design a bias


generator which senses the process corner and tries
to increase the transistor current in the slow corners
and to decrease it in the fast corners.

Simple bias generators using inverters with input and


output shorted and which use this feature are shown
here.

Short p MOS
Vbp
Long n MOS

Vdd
Long p MOS
Vbn
Short n MOS

Proposed CMS Scheme with Smart Bias


We propose a Dynamic Overdrive scheme in which both the
strong and the weak drivers use constant current sources
controlled by process aware bias generators.
Strong Dr.

Weak Dr.
Vdd

p Bias Gen

Short
pMOS

Vbp

Long
nMOS
Vdd

Wire

Rx

Output

Delay
Input

n Bias Gen

Vdd
Long
pMOS

RxBias

Vbn

Inv.
Amp

Short
nMOS

There is no feedback inverter in the driver circuit

Bias voltages change in the desired direction to keep the


current through weak and strong drivers the same across
all corners

Derivation of Improved Bias Circuit


(c)

(b)

(a)

Short
Mp

11
00

Short
1
0
11
00
1
0
00
11
Vbp_1

Long
11
00
00
11
Vbn

Short

Short

1
0

Vgn

Mn 1
Long

Long
11
00
1
0
00
11
1
0

Short

11
00
00
11

Short

Coarse

1
0
0
1

Mp

00

Short

Vbp
Long

Fine

Vbp_1 responds to NMOS Mn1 as well due to fixed bias


voltage

Vbn follows NMOS variations better because of two


stacked NMOS transistors but overcompensates in skewed
corners

Two state implementation gives near perfect compensation

Improved Bias Circuit for Proposed CMS Scheme

Extra
Sensor
Vbn_F

Extra
Sensor
Vbn_C
Long

Long
Vbp_C
Ioutn

Extra
Sensor

Small

Vbp_F
Extra
Sensor

Small

Inverter based with ExtraVt Drop (BiasFCD)

Ioutp

Probability Density Function of Iout

Effect of Process Variation on the Proposed CMS


Scheme

Ipeak remains nearly the same across all corners. In


extreme corners, SS and FF, small change in Ipeak is
compensated by the opposite change in tp .

V = Istatic RL remains the same across all corners,


1
RL = gmn +g
mp

The inverter with input-output shorted and the inverter


amplifier are designed using fingers and placed close to
each other so that their switching thresholds are closely
matched across all corners.

This makes the proposed circuit less sensitive to intra die


process variations as well.

Simulation Setup

Foundry specified four corner model files and mismatch


model file for Monte Carlo simulations were used.

All the signaling schemes offer the same input capacitance


(equivalent to one minimum sized inverter).

All signaling scheme drive FO4 load.

Line RLC used were: Rline = 244 /mm,


Lline = 1.5nH/mm, Cline = 201fF /mm.

All schemes were designed for a throughput of 2.65Gbps.

Current mode schemes are designed for Ipeak = 500A

Effect of Intra-die Process Variations

Mismatch in VM of inverter can be up to 40 mV. 1 . For


VM-mismatch of 40 mV
CMS system
CMS-Fb
CMS-Fpw
CMS-Bias

Percentage Degradation
Delay
Throughput
25
33
10
14
4
9.5

Mismatch Data sheet from the foundry

Effect of Inter-die Process Variations


Signaling System/
Logic Circuit
CMS-Fb
CMS-Fpw
CMS-Bias
Voltage Mode
Ring Oscillator Freq

Percentage Degradation
SS
SNFP FNSP
17.5
5.7
2.9
32
33.6
34.9
18.75
8.2
7.14
27
<1
2.8
23
2.88
3

Interconnects with CMS-Fpw scheme become the


bottleneck in overall performance of the chip in skewed
corners

Degradation in the throughput of the proposed scheme in


the skewed corners is around 7% which is less than that in
CMS-Fpw scheme

Overall Comparison
Performance Comparison of four signaling schemes (line=6
mm, Power measured at 1Gbps)
Signaling
Scheme
CMS-Fb(90 mV)
CMS-Fpw
Proposed CMS
Voltage Mode

Delay
(ps)
700
503
490
1100

Throughput
(Gbps)
2.56
2.65
2.56
2.85

Power
( W )
146
114
113
655

Area
(m2 )
2.00
2.40
3.07
12.53

The CMS-Fb scheme consumes higher power than other


schemes due to static power consumption in the feedback
inverter

The proposed scheme shows 78% improvement in area


over voltage mode scheme whereas other schemes,
CMS-Fb and CMS-Fpw show 84% and 80% respectively

Part II
Measured Results

Motivation

Delays of on-chip interconnects are of the order of


hundreds of pico-seconds.

It is nearly impossible to measure these off-chip.

We need on chip delay measurement circuits. We have


designed two test circuits based on:

Time to Frequency Conversion

Time to Voltage Conversion

Time to Frequency Conversion

S 0
S 1

RO
RO with
Wire

Tx Wire Rx

Transmission gates were used to


implement switches.

Multiplexer(demultiplexer) are designed so


that delays for both possible paths through
the mux/demux pair are the same.

The floor plan of the circuit is such that the


beginning and the end of the long
interconnect are close to each other.

Therefore when the short path L3 is


chosen, the total delay corresponds to the
delay in inverters, mux/demux etc.

L3
L1

L2

CMS Link

Demux

Mux

(a) Delay Measurement Circuit: Principle

I
N
V
E
R
T
E
R
S

D
E
M
U
X
M
U
X

L1

Transmitter

Wire

L3

Receiver
L2
L3=L1+L2

(b) Delay Measurement with CMS Link: Floorplan

S 0
S 1

RO
RO with
Wire

We first measure the frequency of


oscillation choosing the short wire path
between the demux and mux.

This gives the delay of the measurement


circuit except for the system under test.

We now select the interconnect system


whose delay we want to measure and find
the frequency again.

L3
L1

Tx Wire Rx

L2

CMS Link

Demux

Mux

(a) Delay Measurement Circuit: Principle

I
N
V
E
R
T
E
R
S

D
E
M
U
X
M
U
X

L1

Transmitter

Wire

L3

Receiver
L2
L3=L1+L2

(b) Delay Measurement with CMS Link: Floorplan

Delay = 0.5

1
fRO

1
fsystem

Time to Frequency Conversion: Accuracy


To assess the accuracy of the scheme, we simulated the whole
circuit, for different line lengths up to 14 mm in a 180 nm
process.

The delay through the interconnect scheme was noted


from the simulation results. We call this the Simulated
Delay

The delay was also calculated by the formula:




1
1

0.5
fRO
fsystem
We call this the Calculated Delay

These results were tabulated to assess the expected


accuracy from this test scheme.

Time to Frequency Conversion: Accuracy

Line Length
(mm)
4
6
10
14

Simulated
Delay (ps)
501
661
1068
1575

Calculated
Delay (ps)
507
658
1077
1599

% Error
1.2
0.4
0.8
1.5

Delays are the average of rise and fall delay

Power-delay product can be evaluated using this circuit.

This being a differential measurement, the only source of


error is differences in rise and fall time

Time to Voltage Conversion


Vdd

Vref

Mn0

Mn1

Clock
I

Test Pulse
Input

0
1

Delayed
System Input
Under Test

Pulse Select

Capacitor C is pre-charged to peak value during the


negative phase of the clock.

It is then discharged for a time equal to the delay through


the system.

Delay =

Value of k is found experimentally using a calibration pulse


of known duration.

CV
I

= kV

Time to Voltage Conversion: Accuracy

Line
Length
(mm)
4
6
10
14

Simulated Delay
rising
falling
(ps)
(ps)
380
393
478
497
730
769
1065
1149

Calculated Delay
rising
falling
(ps)
(ps)
378
398
482
503
733
781
1078
1171

Error
rising falling
%
%
0.8
1.0
0.8
1.2
0.4
1.8
1.2
1.9

This scheme permits the measurement of rise and fall


delays separately.

Accuracy of about 2% is predicted by simulations.

Current-Mode Signaling Test Chip-1

1.5mm 1.5mm chip fabricated in 180nm MM/RF process

44-pin die packaged in QFN56 package

Measurement Results

(Frequency measured using a 6-digit frequency counter)


Signaling
Scheme
Voltage Mode
CMS-Fb
CMS-Bias

Delay
(ns)
1.191
1.006
0.938

Energy
(pJ)
4.54
1.52
0.851

EDP
(pJns)
5.328
1.52
0.799

Measured at
Data Rate (Mbps)
371
400
621

The proposed circuit offers 22% improvement in delay and 85%


improvement in EDP over voltage-mode scheme.

Comparison with Existing Dynamic Over-driving CMS


Schemes

Source

JSSCC
2006
Sim./Measured Meas.
Tech.
130nm
Line (mm)
10
Gain in Delay
32%
Gain in Energy/bit 35.48%
Gain in EDP
56.5%
Data Rate (Gbps)
3
Activity
1.0

CICC
ESSCIRC
This This*
2006 2005(CMS-Fb) work work
Meas.
Meas.
Meas. Sim.
250nm
130nm
180nm 180nm
5
10
6
6
28.3%
53%
22.5% 32%
67%
25%
81.0% 87%
76.8%
65.5%
85% 90%
2
0.7
0.62
1
1.0
NA
1.0
1.0

Performance of Proposed CMS Scheme


(a) VM

CMSFb

Power (mW)

Delay (ns)

10

1.2
40%

0.8

Energy/bit (pJ)

(c)

5
6
7
Line Length (mm)

180

Power
of
CMSBias

At least 7 lower
power in the worst
process corner

78% gain in active


area

65% reduction in
peak current

Power
of
VM

100

4
5
6
7
Line Length (mm)

140

(d)

Line=6mm

Data Rate=600 Mbps

0.1

Breakeven
Data Rate (Mbps)

0.4

CMSBias

(b)

1.6

8
66.66 Mbps

100

Data Rate(Mbps)

1000

60
20
2

4
5
6
7
Line Length (mm)

Voltage-mode scheme was optimized for delay


separately for every line length

Comparison With Buffer Insertion and Other


Current-Mode

The proposed dynamic over-driving CMS scheme offers


26-40% improvement in delay over the voltage-mode
scheme for 2mm-8mm long lines.

These also offer improvement in energy consumption over


buffer insertion scheme for lines longer than 2mm
operating at data-rates more than around 66Mbps.

The proposed 6mm long link reduces energy consumption


at least by a factor of 7 compared to the voltage-mode
scheme at 1Gbps.

It offers 85% improvement in Energy Delay Product (EDP)


over voltage-mode scheme.

The scheme proposed by us offers 22% improvement in


Power Delay Product (PDP) over the current mode scheme
with feedback proposed by Katoch et al.

Current-Mode Signaling Test Chip-2

180nm Process

CMS schemes with ring


oscillator based delay
measurement scheme

Test setup to emulate intra-die


variations

Measurement Setup for Intra-die Variations

Mismatch in Parameters of the Transistors in Transmitter


and in Receiver

6% of mismatch in | Vth0 | of MOSFETs placed 1.5mm


apart leads to 60mV of mismatch in VM of inverters

Nwell of the PMOS in transmitter (VbnwTx) and that of


PMOS in receiver (VbnwTx) are assigned separate pins

Vary voltages at VbNwTx and VbNwRx to cause mismatch


in PMOS of transmitter and receiver

Maximum difference between VbNwTx and VbNwRx


should correspond to change of VM of 60mV

Effect of Intra-die Variations: Measurement Results

Delay (ns)

2.5

CMSBias
CMSFb

2
2.5X

1.5
1

0.5
0.6 0.4 0.2 0 0.2 0.4 0.6
VbNwTxVbNwRx
Difference inPMOS Substrate Bias
Between TX and RX

1
0.95
0.9
0.85
0.8
0.75
0.7
1.4

Inverter VM (V)

60mV

0.859V
1.6
1.8
2
2.2
PMOS Substrate Bias (V)

Average delay of CMS-Fb becomes 2 for VM mismatch of 60mV


Degradation in speed due to VM mismatch can be reduced by
designing the circuit for higher voltage swing on the line

Effect of Intra-die Variations for Different Voltage


Swing on Line
CMSBiasIin=0
CMSBiasIin=4u
CMSBiasIin=10u
CMSFbIin=0
CMSFbIin=4u
CMSFbIin=10u

Delay (ns)

2.5
2
1.5

1.7x

1
0.5

VMTx=0.803V
VMRx=0.859V

0.6

0.4

VMTx=0.859V
VMRx=0.859V

800
CMSBias

CMSFb
6%

Power (uW)

700

600

VMTx=0.859V
VMRx=0.803V

0.2
0
0.2
0.4
NwellBiasTXNwellBiasRx (V)

0.6

500

4
8
12
Ext. Static Iin (uA)

16

Higher voltage swing design reduces degradation in average


delay but increases average power
Even with higher voltage swing average delay degrades by 50%
in the presence of intra-die variations

Measurement Results (4x1 Mux-demux Based Scheme) :

Delay,

Energy and Energy-Delay-Product (EDP) of 10mm line

Signaling
Scheme
CMS-Fb
CMS-Bias

Delay
(ns)
0.935
0.850

Energy
(pJ)
1.1302
0.7035

EDP
(pJns)
1.057
0.597

Data rate
(Gbps)
0.64
0.64

Vdd-int=1.8 for both the schemes, Vdd-mux=2.0 for CMS-Bias and


Vdd-mux=2.5 for CMS-Fb for fair comparison
Power consumption in bias circuit is distributed evenly in 16-bit bus

Proposed CMS scheme (CMS-Bias) offers 9% improvement in


delay, 37% improvement in energy/bit and 40% improvement in
EDP over CMS-Fb scheme at data rates of 0.64 Gbps for
periodic signal.

Measurement Results for Bidirectional Links

Measurement results match simulation results within 20%

Voltage-mode bidirectional link was not put on silicon due


to limited number of pads

Signaling
Scheme
CM-Bid

Delay
(ns)
1.16

Power
(W )
680

PDP
(mWns)
0.788

Data rate
of Measurement(Gbps)
0.56

Matched Model Parameters

BSIM parameters corresponding to this run were extracted

A few main model parameters (BSIM) were changed to


define four process corners (FF,SS,FS,SF)

Main model parameters (BSIM) were adjusted to match


Isat , Vth , Ioff and a few points on measured Ids -Vgs
characteristics of the devices fabricated in this process run.

Simulation with Matched Model Parameters


Parameters
Isatn (mA)
Isatp (mA)
Vtn (mV)
Vtp (mV)
Ioffn (pA)
Ioffp (pA)
Idsn /Idsp @ Vgs
Idsn @0.9 (A)
Idsp @0.9 (A)
Idsn @1.2 (A)
Idsp @1.2 (A)
Idsn @1.8 (A)
Idsn @1.8 (A)

TT

Measured MMP % Match


Basic Device Parameters
6.23
6.44
6.43
99.8
2.40
2.22
2.28
97.3
501
510
506
99.2
494
493
499
98.8
75
170
120
82.4
80
48
58
80.5
Ids Vgs points
66.6
65
66.4
97.85
76.2
70
67.5
96.45
154.4
150
145
96.67
191
170
172
98.82
347
330
317
96
491
440
452
97.27

Measurement Results and Simulation Results with


MMP
CMBid (MMP)

CMSBid (Measured)

VMBid (MMP )

Power (uW)

Delay (ns)

1.7
1.5
1.3
1.1
0.9

2200
1700
1200
700
200

PDP (X 1e12)

1.6

1.7
Vdd (V)

1.8

2.8
2.3
1.8
1.3
0.8
0.3

1.6

1.7
Vdd (V)
Improvement in Specs
For Simulations using MMP
Vdd (V)
1.6

1.6

1.7
Vdd (V)

1.8

Delay(%) Power(x)

1.8

PDP(x)

36.8

4.5

7.2

1.7

34.4

4.39

6.8

1.8

34.21

4.01

6.0

Conclusion

Global interconnects form a major bottleneck for


performance of digital system at scaled down technology.
Use of current mode signaling is promising to remove this
bottleneck.
Through simulation, circuit fabrication and actual
measurements, we have demonstrated that current mode
signaling has overwhelming advantages over the currently
used voltage mode buffer insertion schemes.
We have demonstrated that the particular configuration
suggested by us for a current mode scheme is superior to
other current mode schemes.
Our scheme is robust with respect to batch to batch
parametric variations and to on chip parametric variation.
Therefore we assert that it is a practical option for use in
modern systems for implementing both unidirectional and
bidirectional data links.

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