Dinesh Sharma
dinesh@ee.iitb.ac.in
Department Of Electrical Engineering
Indian Institute Of Technology, Bombay
March 4, 2015
R0
R0
R0
R0
L
DRIVER
C0
C0
C0
C0
RL
Vref
v
Mp1
i1
Mn1
Mp2
v1
v2
i2
Mn2
Zin =
1 =
Cg1
gmn1
3 = Cg3 rop1
=
gmp1 /gmp2
gmn1 /gmn2
Rin =
2 =
4 =
Cg2
gmp2
Cg3
gmp1
R1 =
R3 = rop1
k=
1
gmn1 rop1
1
gmp1 + rop1
(1 ) +
1
gmn1
R1
R3
i1
ro_p1
1/gmp2
Cg3
Cg1
i2
1/gmn1
Cg2
i2 = gmn2 vg1
If the first zero occurs a decade prior to the first pole, input
impedance is inductive
Leff
=
+
gmn11rop1 > 0.9 and any two time constants being equal
ensures that a zero occurs a decade prior to the first pole
Cg1
Cg2
rop1
+
gmp1 rop1 + 1 gmn1 gmp2
Cg2
Cg3
+
gmp2 gmn1 rop1 gmn1 gmp1 rop1
(1
) + gmn11rop1
1
gmp1 + rop1
Reff
Ceff
= KCgx
Zin
Req
Ceq
Leq
Vdd
Mp11
Source Type
Mp22 Beta Mult.
Mn11
Input
Vref
Mp1
Mp2
Mn1
Mn2
Sink Type
Beta Mult.
Simulation Results
Performance Comparison of three signaling schemes (line=6
mm, Power measured at 1Gbps)
Signaling
Scheme
CMS-BMul(30 mV)[1]
CMS-Diode-CC(30 mV)[2]
Voltage Mode
Delay
(ps)
420
500
1000
Throughput
(Gbps)
2.56
2.45
2.85
Power
( W )
310
380
3000
Area
(m2 )
2.00
2.00
12.53
[1] M Dave et. al., ISLPED 2008, [2] V. Venkatraman et. al. ISQED 2005
VDD
Swing Control (High)
p Drive
Input
n Drive
Swing Control (Low)
Dynamic (Strong)
Driver
VDD
Input
Wire
Feedback
Dynamic (Strong)
Driver
VDD
Input
Wire
Feedback
t +I
(tt )
p
Iavg = peak p static
t
RL = 4k, l = 4H
Comparison of Delay
With Large Overdrive (Ipeak = 500A)
For low power and low data rate applications, the use of
inductive peaking can give 26% improvement in throughput
over RC
For low power and low data rate applications, the use of
inductive peaking can give 16% improvement in delay over
RC
For low power and low data rate applications, the use of
dynamic overdrive along with inductive peaking can further
improve throughput by 20%
Weak Dr.
Vdd
p Bias Gen
Short
pMOS
Vbp
Long
nMOS
Vdd
Wire
Rx
Output
Delay
Input
n Bias Gen
Vdd
Long
pMOS
RxBias
Vbn
Inv.
Amp
Short
nMOS
Simulation Setup
Overall Comparison
10000
1.5
1
0.5
Data Rate(Mbps)
800
400
200
10
12
10
100
1000
Data Rate(Mbps)
600
Line =1.5mm
200
10
100
(c)
Data Rate = 500 Mbps
X 6.6
400
10000
150
(f)
4 6 8 10 12 14
Line Length (mm)
Line=6mm
1
0.1
50
0
4 5 6 7 8 9 10
0
Line Length (mm)
DODFpw+RxFb [2]
DODFb+RxFb [1]
2
X8
100
200
(d)
600
4
6
8
10
Line Length (mm)
800
(b)
Line=6mm
1000
125 Mbps
Power (uW)
Energy (pJ)
(a)
Power (uW)
Power (uW)
Delay (ns)
2.5
0.01
10
100
1000
10000
4 6 8 10 12 14
Data Rate (Mbps)
Line Length (mm)
Proposed
DODFpw+RxBMul [3]
Voltage Mode
Overall Comparison
10000
1.5
1
0.5
Data Rate(Mbps)
800
400
200
10
12
10
100
1000
Data Rate(Mbps)
600
Line =1.5mm
200
10
100
(c)
Data Rate = 500 Mbps
X 6.6
400
10000
150
(f)
4 6 8 10 12 14
Line Length (mm)
Line=6mm
1
0.1
50
0
4 5 6 7 8 9 10
0
Line Length (mm)
DODFpw+RxFb [2]
DODFb+RxFb [1]
2
X8
100
200
(d)
600
4
6
8
10
Line Length (mm)
800
(b)
Line=6mm
1000
125 Mbps
Power (uW)
Energy (pJ)
(a)
Power (uW)
Power (uW)
Delay (ns)
2.5
0.01
10
100
1000
10000
4 6 8 10 12 14
Data Rate (Mbps)
Line Length (mm)
Proposed
DODFpw+RxBMul [3]
Voltage Mode
Bidirectional Links
Back-to-Back Connected
Tri-state Buffers
En
En=
En
En
En
Direction
Signal
Wire
Segment
Wire
Segment
Wire
Segment
En
En
En
En
Receiver Part
Strong
Driver
Short
PMOS
Weak
Driver
Terminator
Vbp
Tx/Rx
Long
NMOS
Inverter
Amplifier
Vbp
Tx/Rx
Tx_ip_1
In
Data
Delay
element
Vbn
out
Wire
Long
PMOS
Tx_ip_0
Tx/Rx
Vbn
Tx/Rx
Short
NMOS
(a)
VMBid
(b)
Power (uW)
Delay (ns)
2.5
2
1.5
1
0.5
0
2
35%
3 4 5 6 7
Line Length (mm)
(d)
Line=4mm
1e3
Crossover
Data Rate (Mbps)
Power (uW)
1e2
100Mbps
1e2
7x
1e3
(c)
10e3
180
5X
100
Data Rate(Mbps)
1000
CMBid
Power
140
100
60
20
2
VMBid
Power
data
Iline
Vbp
Vbn
time
data
Iline
Vbp
Vbn
time
Line
RL
Vcm
gm
Cs
data
Line
RL
Vcm
gm
Cs
data
Line
RL
Vcm
gm
Cs
data
Line
RL
Vcm
gm
Cs
data
Line
RL
Vcm
...0001000...0001111011111...
WC1
26mV
WC2
10mV
WC1
4mV
...0001000...0001111011111...
WC2
20mV
...0001000...0001111011111...
WC1
15mV
WC2
15mV
time(ns)
Part I
Variation Tolerant Current Mode
Robustness requirements
Ideal
VcmRx
Transmitter
Receiver
Misaligned
VcmRx
Weak
Driver
VDD
Receiver Eq. Circuit
Wire
Input
RxOut
LineRx
RL
I1
Feedback
Vcm Rx
Wire
Weak
Driver
VDD
Receiver Eq. Circuit
Wire
Input
LineRx
RxOut
RL
+ Vcm Rx
I1
Feedback
Wire
VCMRx
VMTx
Weak
Driver
Fixed Width
Pulse Generator
Input
VDD
Receiver Eq. Circuit
Wire
LineRx
RxOut
Delay
RL
Vcm Rx
Short p MOS
Vbp
Long n MOS
Vdd
Long p MOS
Vbn
Short n MOS
Weak Dr.
Vdd
p Bias Gen
Short
pMOS
Vbp
Long
nMOS
Vdd
Wire
Rx
Output
Delay
Input
n Bias Gen
Vdd
Long
pMOS
RxBias
Vbn
Inv.
Amp
Short
nMOS
(b)
(a)
Short
Mp
11
00
Short
1
0
11
00
1
0
00
11
Vbp_1
Long
11
00
00
11
Vbn
Short
Short
1
0
Vgn
Mn 1
Long
Long
11
00
1
0
00
11
1
0
Short
11
00
00
11
Short
Coarse
1
0
0
1
Mp
00
Short
Vbp
Long
Fine
Extra
Sensor
Vbn_F
Extra
Sensor
Vbn_C
Long
Long
Vbp_C
Ioutn
Extra
Sensor
Small
Vbp_F
Extra
Sensor
Small
Ioutp
Simulation Setup
Percentage Degradation
Delay
Throughput
25
33
10
14
4
9.5
Percentage Degradation
SS
SNFP FNSP
17.5
5.7
2.9
32
33.6
34.9
18.75
8.2
7.14
27
<1
2.8
23
2.88
3
Overall Comparison
Performance Comparison of four signaling schemes (line=6
mm, Power measured at 1Gbps)
Signaling
Scheme
CMS-Fb(90 mV)
CMS-Fpw
Proposed CMS
Voltage Mode
Delay
(ps)
700
503
490
1100
Throughput
(Gbps)
2.56
2.65
2.56
2.85
Power
( W )
146
114
113
655
Area
(m2 )
2.00
2.40
3.07
12.53
Part II
Measured Results
Motivation
S 0
S 1
RO
RO with
Wire
Tx Wire Rx
L3
L1
L2
CMS Link
Demux
Mux
I
N
V
E
R
T
E
R
S
D
E
M
U
X
M
U
X
L1
Transmitter
Wire
L3
Receiver
L2
L3=L1+L2
S 0
S 1
RO
RO with
Wire
L3
L1
Tx Wire Rx
L2
CMS Link
Demux
Mux
I
N
V
E
R
T
E
R
S
D
E
M
U
X
M
U
X
L1
Transmitter
Wire
L3
Receiver
L2
L3=L1+L2
Delay = 0.5
1
fRO
1
fsystem
0.5
fRO
fsystem
We call this the Calculated Delay
Line Length
(mm)
4
6
10
14
Simulated
Delay (ps)
501
661
1068
1575
Calculated
Delay (ps)
507
658
1077
1599
% Error
1.2
0.4
0.8
1.5
Vref
Mn0
Mn1
Clock
I
Test Pulse
Input
0
1
Delayed
System Input
Under Test
Pulse Select
Delay =
CV
I
= kV
Line
Length
(mm)
4
6
10
14
Simulated Delay
rising
falling
(ps)
(ps)
380
393
478
497
730
769
1065
1149
Calculated Delay
rising
falling
(ps)
(ps)
378
398
482
503
733
781
1078
1171
Error
rising falling
%
%
0.8
1.0
0.8
1.2
0.4
1.8
1.2
1.9
Measurement Results
Delay
(ns)
1.191
1.006
0.938
Energy
(pJ)
4.54
1.52
0.851
EDP
(pJns)
5.328
1.52
0.799
Measured at
Data Rate (Mbps)
371
400
621
Source
JSSCC
2006
Sim./Measured Meas.
Tech.
130nm
Line (mm)
10
Gain in Delay
32%
Gain in Energy/bit 35.48%
Gain in EDP
56.5%
Data Rate (Gbps)
3
Activity
1.0
CICC
ESSCIRC
This This*
2006 2005(CMS-Fb) work work
Meas.
Meas.
Meas. Sim.
250nm
130nm
180nm 180nm
5
10
6
6
28.3%
53%
22.5% 32%
67%
25%
81.0% 87%
76.8%
65.5%
85% 90%
2
0.7
0.62
1
1.0
NA
1.0
1.0
CMSFb
Power (mW)
Delay (ns)
10
1.2
40%
0.8
Energy/bit (pJ)
(c)
5
6
7
Line Length (mm)
180
Power
of
CMSBias
At least 7 lower
power in the worst
process corner
65% reduction in
peak current
Power
of
VM
100
4
5
6
7
Line Length (mm)
140
(d)
Line=6mm
0.1
Breakeven
Data Rate (Mbps)
0.4
CMSBias
(b)
1.6
8
66.66 Mbps
100
Data Rate(Mbps)
1000
60
20
2
4
5
6
7
Line Length (mm)
180nm Process
Delay (ns)
2.5
CMSBias
CMSFb
2
2.5X
1.5
1
0.5
0.6 0.4 0.2 0 0.2 0.4 0.6
VbNwTxVbNwRx
Difference inPMOS Substrate Bias
Between TX and RX
1
0.95
0.9
0.85
0.8
0.75
0.7
1.4
Inverter VM (V)
60mV
0.859V
1.6
1.8
2
2.2
PMOS Substrate Bias (V)
Delay (ns)
2.5
2
1.5
1.7x
1
0.5
VMTx=0.803V
VMRx=0.859V
0.6
0.4
VMTx=0.859V
VMRx=0.859V
800
CMSBias
CMSFb
6%
Power (uW)
700
600
VMTx=0.859V
VMRx=0.803V
0.2
0
0.2
0.4
NwellBiasTXNwellBiasRx (V)
0.6
500
4
8
12
Ext. Static Iin (uA)
16
Delay,
Signaling
Scheme
CMS-Fb
CMS-Bias
Delay
(ns)
0.935
0.850
Energy
(pJ)
1.1302
0.7035
EDP
(pJns)
1.057
0.597
Data rate
(Gbps)
0.64
0.64
Signaling
Scheme
CM-Bid
Delay
(ns)
1.16
Power
(W )
680
PDP
(mWns)
0.788
Data rate
of Measurement(Gbps)
0.56
TT
CMSBid (Measured)
VMBid (MMP )
Power (uW)
Delay (ns)
1.7
1.5
1.3
1.1
0.9
2200
1700
1200
700
200
PDP (X 1e12)
1.6
1.7
Vdd (V)
1.8
2.8
2.3
1.8
1.3
0.8
0.3
1.6
1.7
Vdd (V)
Improvement in Specs
For Simulations using MMP
Vdd (V)
1.6
1.6
1.7
Vdd (V)
1.8
Delay(%) Power(x)
1.8
PDP(x)
36.8
4.5
7.2
1.7
34.4
4.39
6.8
1.8
34.21
4.01
6.0
Conclusion