COURSE OBJECTIVE
The
course
provides
an
in-depth
understanding
of
the
operation
of
to
interface
and
build
microprocessors
and Microcontroller
based
applications involving inter facing of 8255 with 8086 and serial communication. The
objective
of
this
course
is
to
teach
students
design
and
interfacing
of
and
understand
the
impact
of
computer
hardware
on
software
fashion
so
that
constraints in embedded
the
students
have
systems. It teaches
basic
understanding
the students
how
of
is to
various
use the
course
is
intended
as
first
level
course
for
microprocessor
and
machine or
assembly language
for
embedded
system
applications,
simulator
to
hardware-software
perform
software
integration.
development,
hardware development
and
SYLLABUS
MICROPROCESSORS AND MICROCONTROLLERS
UNIT-I
8086 Architecture: Introduction to
UNIT-VII
8051 Real Time Control: Interrupts, timer/counter and serial communication,
Programming Timer interrupts, Programming external hardware interrupts, Programming
serial communication interrupts, Programming 8051 Times and counters.
UNIT-VIII
The AVR RISC microcontrollers architecture: Introduction, AVR family architecture,
Register file, The ALU, memory access and instruction execution, I/O memory. EEPROM,
I/O ports, Timers, UART and Interrupt Structure.
TEXT BOOKS:
1. Kenneth J Ayala, The 8051 Micro Controller Architecture,
Programming
INTRODUCTION
In December 1970, Gilbert Hyatt filed a patent application entitled Single Chip
Integrated Circuit Computer Architecture, the first basic patent on the microprocessor.
The microprocessor was invented in the year 1971 in the Intel labs. The first processor
was a 4 bit processor and was called 4004.The following table gives chronologically the
microprocessor revolution.
4004
Year of
Introduc
tion
1971
4 bits
Memory
Addressi
ng
1KB
8008
1972
8 bits
16KB
18
800KHz
8080
1973
8 bits
64KB
40
2 MHz
8085
1976
8 bits
64KB
40
3-6 MHz
8086
1978
16 bits
1 MB
40
5-10 MHz
8088
1980
8/16
bits
1MB
40
5-8MHz
PC/XT
80186
1982
16 bits
1 MB
68
5-8MHz
More a
Microcontroller
80286
1982
16 bits
68
60-12.5MHz
PC/AT, 15 million
PCs sold in 6 years
80386DX
1985
32 bits
132
PGA
20-33MHz
2,75,000
transistors
80386SX
1988
16/32
bits
100
20MHz
32b int
16b ext
80486DX
1989
32 bits
168
PGA
25-66MHz
Flaot pt cop,
Command line to
Microproces
sors
Word
Length
16 MB
real,
4GBv
4GB real,
64TBv
16MB
real,
64TBv
4 GB real,
64TBv
Pins
Clock
16
750KHz
Remarks
Intels 1st P
Mark-8 used this;
1st computer for
the home.
6000trs, Altair-1st
PC
Popular
IBM PC, Intel
became one of
fortune 500
companies.
Pentium
Pentium Pro
1993
1995
Pentium II
1997
Pentium II
Xeon
1998
Pentium III
Xeon
1999
64 bits
4 GB, 16
KB cache
237
PGA
60-200 MHz
64 bits
64Gb,
256K/512
K L2
Cache
387
PGA
150MHz
64 bits
64Gb
242
400MHz
64 bits
512k/1M/
2M L2
cache
528
pins
LGA
400MHz
64 bits
16 k L1
data + 16
k L1
instr; 512
kB/1
MB/2 MB
L2
370
PGA
1GHz
423
PGA
Pentium 4
2000
64 bits
514,864
KB
Xeon
2001
64 bits
8 MB iL3
cache
Itanium
2001
64 bits
2MB/ 4MB
L3 cache
Itanium 2
2002
64 bits
1.5 9MB
L3 cache
Centrino
mobile
2003
64 bits
Pentium 4
processor
extreme
2003
64 bits
Centrino M
(mobile)
2004
64 bits
1.3 - 2GHz
3.33 GHz
418
pins
FCPGA
611
pins
FCPGA
800 MHz
200 MHz
e-commerce
applications
1.5 GHz,
Professional quality
movies, rendering
3D graphics.
Choice of operating
system
Enabling ecommerce security
transactions
Business
applications
Mobile specific,
increased battery
life.
2 MB L2
cache
423
pins
PGA
3.80 GHz
Hyper threading
technology, games
90nm,2MB L2
cache400MHz
power-system
optimized system
bus
INTRODUCTION TO MICROPROCESSOR
Microprocessor: A silicon chip that contains a CPU. In the world of personal Computers,
the terms microprocessor and CPU are used interchangeably. A microprocessor
(sometimes abbreviated P) is a digital electronic component with miniaturized
transistors on a single semiconductor integrated circuit (IC).One or more
microprocessors typically serves as a central processing unit (CPU) in a computer system
or handheld device. Microprocessors made possible the advent of the microcomputer. At
the heart of all personal computers and most working stations sits a microprocessor.
Microprocessors also control the logic of almost all digital devices, from clock radios to
fuel-injection systems for automobiles.
Three basic characteristics differentiate microprocessors:
Instruction set: The set of instructions that the microprocessor can execute.
Bandwidth: The number of bits processed in a single instruction.
Clock speed: Given in megahertz (MHz), the clock speed determines how many
instructions per second the processor can execute.
Microcontroller:
A highly integrated chip that contains all the components comprising a controller.
Typically this includes a CPU, RAM, some form of ROM, I/O ports, and timers. Unlike a
general-purpose computer, which also includes all of these components, a
microcontroller is designed for a very specific task - to control a particular system.
A microcontroller differs from a microprocessor, which is a general-purpose chip that is
used to create a multi-function computer or device and requires multiple chips to handle
various tasks. A microcontroller is meant to be more self-contained and independent,
and functions as a tiny, dedicated computer.
The great advantage of microcontrollers, as opposed to using larger microprocessors, is
that the parts-count and design costs of the item being controlled can be kept to a
minimum. They are typically designed using CMOS (complementary metal oxide
semiconductor) technology, an efficient fabrication technique that uses less power and is
more immune to power spikes than other techniques. Microcontrollers are sometimes
called embedded microcontrollers, which just means that they are part of an embedded
system that is, one part of a larger device or system
Embedded system:
by a common data bus. Where point-to-point data transfer is required, the digital
format is the preferred method
Control Bus
The control bus is used by the CPU to direct and monitor the actions of the other
functional areas of the computer. It is used to transmit a variety of individual signals
(read, write, interrupt, acknowledge, and so forth) necessary
to control and
coordinate the operations of the computer. The individual signals transmitted over the
control bus and their functions are covered in the appropriate functional area description.
Address Bus
The address bus consists of all the signals necessary to define any of the possible
memory address locations within the computer, or for modular memories any of the
possible memory addresses locations within a module. An address is defined as a label,
symbol, or other set of characters used to designate a location or register where
information is stored. Before data or instructions can be written into or read from
memory by the CPU or I/O sections, an address must be transmitted to memory over
the address bus.
Data Bus
The bidirectional data bus, sometimes called the memory bus, handles the transfer of
all data and instructions between functional areas of the computer. The bi directional
data bus can only transmit in one direction at a time. The data bus is used to transfer
instructions from memory to the CPU for execution. It carries data (operands) to and
from the CPU and memory as required by instruction translation. The data bus is also
used to transfer data between memory and the I/O section during input/output
operations
Tristate bus
Three-state, tri-state, or 3-state logic allows an output port to assume a high
impedance state in addition to the 0 and 1 logic levels, effectively removing the output
from the circuit. This allows multiple circuits to share the same output line or lines (such
as a bus).
UNIT-I
8085 Microprocessor
Introduction to 8085
It was introduced in 1977.
It is 8-bit microprocessor.
Its actual name is 8085 A.
It is single NMOS device.
It contains 6200 transistors approx.
Its dimensions are 164 mm x 222 mm.
It is having 40 pins Dual-In line-Package (DIP).
It has three advanced versions:
8085 AH
8085 AH2
8085 AH1
These advanced versions are designed using HMOS technology.
The advanced versions consume 20% less power supply.
The clock frequencies of 8085 are:
8085 A 3 MHz
8085 AH 3 MHz
8085 AH2 5 MHz
8085 AH1 6 MHz
Pin Diagram of 8085
RESET OUT:
It is used to reset the peripheral devices and other ICs on the circuit.
It is an output signal.
It is an active high signal.
The output on this pin goes high whenever RESET IN is given low signal.
The output remains high as long as RESET IN is kept low.
Interrupt Pins
Interrupt:
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
Classification of Interrupts
Maskable Interrupts
INTR
Non-Maskable Interrupts
The interrupts which are always in enabled mode are called non-maskable interrupts.
These interrupts can never be disabled by any software instruction.
TRAP is a non-maskable interrupt.
Vectored Interrupts
The interrupts which have fixed memory location for transfer of control from normal
execution.
Each vectored interrupt points to the particular location in memory.
Non-Vectored Interrupts
The interrupts which don't have fixed memory location for transfer of control from
normal execution.
The address of the memory location is sent along with the interrupt.
INTR is a non-vectored interrupt.
The interrupts which are triggered at leading or trailing edge are called edge
triggered interrupts.
RST 7.5 is an edge triggered interrupt.
It is triggered during the leading (positive) edge.
The interrupts which are triggered at high or low level are called level triggered
interrupts.
RST 6.5
RST 5.5
INTR
TRAP is edge and level triggered interrupt.
Whenever there exists a simultaneous request at two or more pins then the pin with
higher priority is selected by the microprocessor.
Priority is considered only when there are simultaneous requests.
Priority of interrupts:
It is an non-maskable interrupt.
It has the highest priority.
It cannot be disabled.
It is both edge and level triggered.
It means TRAP signal must go from low to high.
And must remain high for a certain period of time.
TRAP is usually used for power failure and emergency shutoff.
It is a Maskable interrupt.
It has the second highest priority.
It is positive edge triggered only.
The internal flip-flop is triggered by the rising edge.
The flip-flop remains high until it is cleared by RESET IN.
It is a Maskable interrupt.
It has the third highest priority.
It is level triggered only.
The pin has to be held high for a specific period of time.
RST 6.5 can be enabled by EI instruction.
It can be disabled by DI instruction.
It is a Maskable interrupt.
It has the fourth highest priority.
It is also level triggered.
The pin has to be held high for a specific period of time.
This interrupt is very similar to RST 6.5.
It
It
It
It
is a maskable interrupt.
has the lowest priority.
is also level triggered.
is a general purpose interrupt.
These pins serve the dual purpose of transmitting lower order address and data byte.
During 1st clock cycle, these pins act as lower half of address.
In remaining clock cycles, these pins act as data bus.
The separation of lower order address and data is done by address latch.
RD (Pin 32 (Output))
WR (Pin 31 (Output))
This pin is used to synchronize slower peripheral devices with fast microprocessor.
A low value causes the microprocessor to enter into wait state.
The microprocessor remains in wait state until the input at this pin goes high.
Processing Unit
Instruction Unit
Storage and Interface Unit
Processing Unit
Instruction Unit
Instruction Register
Instruction Decoder
Timing and Control Unit
Storage and Interface Unit
Interrupt Controller
Serial I/O Controller
Power Supply
Accumulator
Arithmetic Operations:
Logic Operations:
Temporary Register
It is an 8-bit register.
It is used to store temporary 8-bit operand from general purpose register.
It is also used to store intermediate results.
Status Flags
Status Flags are set of flip-flops which are used to check the status of Accumulator after
the operation is performed.
S = Sign Flag
Z = Zero Flag
AC = Auxiliary Carry Flag
P = Parity Flag
CY = Carry Flag
It tells the sign of result stored in Accumulator after the operation is performed.
If result is ve, sign flag is set (1).
If result is +ve, sign flag is reset (0).
It tells whether the result stored in Accumulator is zero or not after the operation is
performed.
If result is zero, zero flag is set (1).
If result is not zero, zero flag is reset (0).
The contents of Accumulator and Status Flags clubbed together is known as Program
Status
Word (PSW).
It is a 16-bit word.
Instruction Register
Instruction Decoder
Program Counter
Stack Pointer
Increment/Decrement Register
Address Latch
It is group of 8 buffers.
The upper-byte of 16-bit address is stored in this latch.
And then it is made available to the peripheral devices.
Address/Data Latch
It is used to convert serial data into parallel and parallel data into serial.
Microprocessor works with 8-bit parallel data.
Serial I/O devices works with serial transfer of data.
Therefore, this unit is the interface between microprocessor and serial I/O devices.
Interrupt Controller
Interrupt Controller
Interrupt controller receives these interrupts according to their priority and applies
them to the microprocessor.
There is one outgoing signal INTA which is called Interrupt Acknowledge.
Power Supply
Accumulator Register (AX) consists of 2 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX. AL in this case contains the loworder byte of the word, and AH contains the high-order byte. Accumulator can be used
for I/O operations and string manipulation.
Base Register (BX) consists of 2 8-bit registers BL and BH, which can be combined
together and used as a 16-bit register BX. BL in this case contains the low-order byte of
the word, and BH contains the high-order byte. BX register usually contains a data
pointer used for based, based indexed or register indirect addressing.
Count Register (CX) consists of 2 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX. When combined, CL register contains the
low-order byte of the word, and CH contains the high-order byte. Count register can be
used as a counter in string manipulation and shift/rotate instructions.
Data Register (DX) consists of 2 8-bit registers DL and DH, which can be combined
together and used as a 16-bit register DX. When combined, DL register contains the
low-order byte of the word, and DH contains the high-order byte. Data register can be
used as a port number in I/O operations. In integer 32-bit multiply and divide
instruction the DX register contains high-order word of the initial or resulting number.
Different registers and their operations are listed below:
Register
AX
AL
AH
BX
CX
CL
DX
Operations
Word multiply, Word divide, word I/O
Byte Multiply, Byte Divide, Byte I/O, translate, Decimal Arithmetic
Byte Multiply, Byte Divide
Translate
String Operations, Loops
Variable Shift and Rotate
Word Multiply, word Divide, Indirect I/O
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and
register indirect addressing, as well as a source data addresses in string manipulation
instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and
register indirect addressing, as well as a destination data addresses in string
manipulation instructions.
Instruction Pointer Register This is a crucially important register which is used to
control which instruction the CPU executes. The IP, or program counter, is used to store
the memory location of the next instruction to be executed.
The CPU checks the program counter to ascertain which instruction to carry out next. It
then updates the program counter to point to the next instruction. Thus the program
counter will always point to the next instruction to be executed.
Segment Registers:
Additional registers called segment registers generate memory address when combined
with other in the microprocessor. In 8086 microprocessor, memory is divided into 4
segments as follow:
There are four different 64 KB segments for instructions, stack, data and extra data. To
specify where in 1 MB of processor memory these 4 segments are located the processor
uses four segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with
processor instructions. The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register. CS register cannot be changed directly.
The CS register is automatically updated during far jump, far call and far return
instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack. By default, the processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register
can be changed directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with
program data. By default, the processor assumes that all data referenced by general
registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment.
DS register can be changed directly using POP and LDS instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually
with program data. By default, the processor assumes that the DI register references
the ES segment in string manipulation instructions. ES register can be changed directly
using POP and LES instructions.
It is possible to change default segments used by general and index registers by
prefixing instructions with a CS, SS, DS or ES prefix.
Segment Register
Default Offset
CS
IP (Instruction Pointer)
DS
SI, DI
SS
SP, BP
ES
DI
Carry Flag (CF): This flag indicates an overflow condition for unsigned integer
arithmetic. It is also used in multiple-precision arithmetic.
Auxiliary Flag (AF): If an
lower nibble (i.e. D0 D3)
given by D3 bit to D4 is AF
by the processor to perform
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits
of the result contains even number of 1s, the Parity Flag is set and for odd number of
1s, the Parity Flag is reset.
Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is
reset.
Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If
the result of operation is negative, sign flag is set.
Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF
indicates that the result has exceeded the capacity of machine.
2. Control Flags:
Control flags are set or reset deliberately to control the operations of the execution unit.
Control flags are as follows:
Trap Flag (TP):
a. It is used for single step control.
b. It allows user to execute one instruction of a program at a time for debugging.
c. When trap flag is set, program can be run in single step mode.
Interrupt Flag (IF):
a. It is an interrupt enable/disable flag.
b. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is
disabled.
c. It can be set by executing instruction sit and can be cleared by executing CLI
instruction.
Direction Flag (DF):
a. It is used in string operation.
b. If it is set, string bytes are accessed from higher memory address to lower memory
address.
c. When it is reset, the string bytes are accessed from lower memory address to higher
memory address.
MEMORY SEGMENTATION:
Since address registers and address operands are only 16 bits they can only address 64k
bytes. In order to address the 20-bit address range of the 8086, physical addresses
(those that are put on the address bus) are always formed by adding the values of one
of the instruction are executed? The use of segment registers reduces the size of
pointers to 16 bits. This reduces the code size but also restricts the addressing range of
a pointer to 64k bytes. Performing address arithmetic within data structures larger than
64k is awkward. This is the biggest drawback of the 8086 architecture. We will restrict
ourselves to short programs where all of the code, data and stack are placed into
thesame 64k segment (i.e. CS=DS=SS).
Most of the registers contain data/instruction offsets within 64 KB memory segment.
There are four different 64 KB segments for instructions, stack, data and extra data. To
specify where in 1 MB of processor memory these 4 segments are located the processor
uses four segment registers:
Memory
Program, data and stack memories occupy the same memory space. As the most of the
processor instructions use 16-bit pointers the processor can effectively address only
64KB of memory.
To access memory outside of 64 KB the CPU uses special segment registers to specify
where the code, stack and data 64 KB segments are positioned within 1 MB of memory
(see the "Registers" section below).
16-bit pointers and data are stored as: address: low-order byte address+1: high-order
byte
Program memory - program can be located anywhere in memory. Jump and call
instructions can be used for short jumps within currently selected 64 KB code segment,
as well as for far jumps anywhere within 1 MB of memory.
All conditional jump instructions can be used to jump within approximately +127 to 127 bytes from current instruction.
Data memory - the processor can access data in any one out of 4 available segments,
which limits the size of accessible memory to 256 KB (if all four segments point to
different 64 KB blocks).
Accessing data from the Data, Code, Stack or Extra segments can be usually done by
prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by
default may use the ES or SS segments instead of DS segment).
Word data can be located at odd or even byte boundaries. The processor uses two
memory accesses to read 16-bit word located at odd byte boundaries. Reading word
data from even byte boundaries requires only one memory access.
Stack memory can be placed anywhere in memory. The stack can be located at odd
memory addresses, but it is not recommended for performance reasons (see "Data
Memory" above).
Reserved locations: 0000h - 03FFh are reserved for interrupt vectors. Each interrupt
vector is a 32-bit pointer in format segment: offset.
FFFF0h - FFFFFh - after RESET the processor always starts program execution at the
FFFF0h address.
Segment registers to the 16-bit address to form a 20-bit address. The segment registers
themselves only contain the most-significant 16 bits of the 20-bit value that is
contributed by the segment registers. The least significant four bits of the segment
address are always zero.
By default, the DS (data segment) is used for data transfer instructions (e.g. MOV),
CS(code segment) is used with control transfer instructions(e.g. JMP or CALL), and SS is
used with the stack pointer (e.g. PUSH or to save/restore addresses during CALL/RET or
INT instructions).
Code segment (CS) is a 16-bit register containing address of 64 KB segment with
processor instructions. The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register. CS register cannot be changed directly.
The CS register is automatically updated during far jump, far call and far return
instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack. By default, the processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register
can be changed directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with
program data. By default, the processor assumes that all data referenced by general
registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS
register can be changed directly using POP and LDS instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually
with program data. By default, the processor assumes that the DI registers references
the ES segment in string manipulation instructions. ES register can be changed directly
using POP and LES instructions. It is possible to change default segments used by
general and index registers by prefixing instructions with a CS, SS, DS or ES prefix.
Generation of 20-bit Physical Address:
LOGICAL ADDRESS
SEGMENT REGISTER
0000
ADDER
Fig: One way four 64-Kbyte segment might be positioned within the 1-Mbyte address space of an
8086
PHYSICAL
ADDRESS
FFFFFH
7FFFFH
MEMORY
HIGHEST ADDRESS
TOP OF EXTRA SEGMENT
64K
70000H
5FFFFH
64K
50000H
SS = 5000H
4489FH
64K
348A0H
2FFFFH
64K
20000H
PHYSICAL
ADDRESS
MEMORY
4489FH
38AB4H
CODE BYTE
IP=4214H
START OF CODE SEGMENT
CS=348AH
348A0H
(a) Diagram
CS
IP
3 4 8 A 0
4 2 1 4
3 8 A B 4
PHYSICAL ADDRESS
(b) Computation
HARDWIRED ZERO
When 8086 executes an instruction, it performs the specified function on data. These
data are called its operands and may be part of the instruction, reside in one of the
internal registers of the microprocessor, stored at an address in memory or held at an
I/O port, to access these different types of operands, the 8086 is provided with various
addressing modes (Data Addressing Modes).
Data Addressing Modes of 8086
The 8086 has 12 addressing modes. The various 8086 addressing modes can be
classified into five groups.
A.
Addressing modes for accessing immediate and register data (register and
immediate modes).
B.
Addressing modes for accessing data in memory (memory modes)
C.
Addressing modes for accessing I/O ports (I/O modes)
D.
Relative addressing mode
E.
Implied addressing mode
8086 ADDRESSING MODES
A.
Immediate addressing mode:
In this mode, 8 or 16 bit data can be specified as part of the instruction.
OP Code
Immediate
Operand
Example 1 : MOV CL, 03 H
Moves the 8 bit data 03 H into CL
Example 2 : MOV DX, 0525 H
Moves the 16 bit data 0525 H into DX
In the above two examples, the source operand is in immediate mode and the
destination operand is in register mode.
A constant such as VALUE can be defined by the assembler EQUATE directive such as
VALUE EQU 35H
Example
: MOV BH, VALUE
Used to load 35 H into BH
Register addressing mode :
The operand to be accessed is specified as residing in an internal register of 8086. Fig.
below shows internal registers, any one can be used as a source or destination operand,
however only the data registers can be accessed as either a byte or word.
Register
Accumulator
Base
Count
Data
Stack pointer
Base pointer
Operand sizes
Byte (Reg 8)
Word
AL, AH
BL, BH
CL, CH
DL, DH
-
(Reg 16)
Ax
Bx
Cx
Dx
SP
BP
Source index
Destination index
Code Segment
Data Segment
Stack Segment
Extra Segment
SI
DI
CS
DS
SS
ES
CS
DS
:
Direct Address
SS
ES
The Execution Unit (EU) has direct access to all registers and data for register and
immediate operands. However the EU cannot directly access the memory operands. It
must use the BIU, in order to access memory operands.
In the direct addressing mode, the 16 bit effective address (EA) is taken directly from
the displacement field of the instruction.
Example 1 : MOV CX, START
If the 16 bit value assigned to the offset START by the programmer using an assembler
pseudo instruction such as DW is 0040 and [DS] = 3050.
Then BIU generates the 20 bit physical address 30540 H.
The content of 30540 is moved to CL
The content of 30541 is moved to CH
Example 2 : MOV CH, START
If [DS] = 3050 and START = 0040
8 bit content of memory location 30540 is moved to CH.
Example 3 : MOV START, BX
With [DS] = 3050, the value of START is 0040.
Physical address : 30540
MOV instruction moves (BL) and (BH) to locations 30540 and 30541 respectively.
Register indirect addressing mode :
The EA is specified in either pointer (BX) register or an index (SI or DI) register. The 20
bit physical address is computed using DS and EA.
Example : MOV [DI], BX
register indirect
If [DS] = 5004, [DI] = 0020, [Bx] = 2456
The content of BX(2456) is moved
CS
PA =
DS
SS
=
ES
PA=50060.
PA =
Example
CS
DS
BX
SI
SS
:
or
+
or
+ 8 or 16bit displacement
ES
BP
DI
: MOV ALPHA [SI] [BX], CL
If [BX] = 0200, ALPHA 08, [SI] = 1000 H and [DS] = 3000
Meaning
Format
Operation
MOV
Move
MOV D, S
(S) (D)
Destination
Memory
Accumulator
Register
Register
Memory
Register
Memory
Seg. Register
Seg. Register
(Word Operation) Reg 16
(Word Operation) Memory 16
Source
Accumulator
Memory
Register
Memory
Register
Immediate
Immediate
Reg 16
Mem 16
Seg Reg
Seg Reg
Flags
affected
None
Example
MOV TEMP, AL
MOV AX, TEMP
MOV AX, BX
MOV BP, Stack top
MOV COUNT [DI], CX
MOV CL, 04
MOV MASK [BX] [SI], 2F
MOV ES, CX
MOV DS, Seg base
MOV BP SS
MOV [BX], CS
MOV instruction cannot transfer data directly between a source and a destination that
both reside in external memory.
INPUT/OUTPUT INSTRUCTIONS:
IN acc, port: In transfers a byte or a word from input port to the AL register or the AX
register respectively. The port number my be specified either with an immediate byte
constant, allowing access to ports numbered 0 through 255 or with a number previously
placed in the DX register allowing variable access (by changing the value in DX) to ports
numbered from 0 through 65,535.
In Operands
Example
acc, immB
acc, DX
OUT port, acc : Out transfers a byte or a word from the AL register or the AX register
respectively to an output port. The port numbers may be specified either with an
immediate byte or with a number previously placed in the register DX allowing variable
access.
No flags are affected.
In Operands
Example
Imm 8, acc
DX, acc
XCHG D, S :
Mnemonic
XCHG
Destination
Accumulator
Memory
Register
Meaning
Exchange
Format
XCHGD,S
Source
Reg 16
Register
Register
Operation
(D) (S)
Flags affected
None
Example
XCHG, AX, BX
XCHG TEMP, AX
XCHG AL, BL
Data
00
01
0302
0303
.
.
030F
03
02
Result (0351) = 02
.
08
:
:
:
MOV [SJ+1], AL
INT20
Meaning
Operation
LAHF
SAHF
CLC
STC
CMC
CLI
STI
(AH)Flags
(flags) (AH)
(CF) 0
(CF) 1
(CF) (CF)
(IF) 0
(IF) 1
Flags
affected
None
SF,ZF,AF,PF,CF
CF
CF
CF
IF
IF
NEXT:
MOV SB
LOOP NEXT
HLT
Load and store strings: (LOD SB/LOD SW and STO SB/STO SW)
LOD SB: Loads a byte from a string in memory into AL. The address in SI is used
relative to DS to determine the address of the memory location of the string element.
(AL) [(DS) + (SI)]
(SI) (SI) + 1
LOD SW: The word string element at the physical address derived from DS and SI is to
be loaded into AX. SI is automatically incremented by 2.
(AX) [(DS) + (SI)]
(SI) (SI) + 2
STO SB: Stores a byte from AL into a string location in memory. This time the contents
of ES and DI are used to form the address of the storage location in memory
[(ES) + (DI)] (AL)
(DI) (DI) + 1
STO SW :
[(ES) + (DI)] (AX)
(DI) (DI) + 2
Mnemonic
Meaning
Format
MOV SB
Move
String
Byte
MOV SB
Operation
((ES)+(DI))((DS)+(SI))
(SI)(SI) 1
Move
String
Word
MOV
SW
(DI) 1
((ES)+(DI))((DS)+(SI))
((ES)+(DI)+1)(DS)+(SI)+1)
(SI) (SI) 2
LOD SB /
LOD SW
Load
String
LOD SB/
LOD SW
STOSB/
STOSW
Store
String
STOSB/
STOSW
MOV SW
Example :
AGAIN :
(DI) (DI) 2
(AL) or (AX) ((DS)+(SI))
(SI)(SI) 1 or 2
((ES)+(DI))(AL) or (AX)
(DI) (DI) 71 or 2
Flags affected
None
None
None
None
NEXT :
Clear A000 to A00F to 0016
Repeat String : REP
The basic string operations must be repeated to process arrays of data. This is done by
inserting a repeat prefix before the instruction that is to be repeated.
Prefix REP causes the basic string operation to be repeated until the contents of register
CX become equal to zero. Each time the instruction is executed, it causes CX to be
tested for zero, if CX is found to be nonzero it is decremented by 1 and the basic string
operation is repeated.
Example : Clearing a block of memory by repeating STOSB
MOV AX, 0
MOV ES, AX
MOV DI, A000
MOV CX, OF
CDF
REP STOSB
NEXT:
The prefixes REPE and REPZ stand for same function. They are meant for use with the
CMPS and SCAS instructions. With REPE/REPZ the basic compare or scan operation can
be repeated as long as both the contents of CX are not equal to zero and zero flag is 1.
REPNE and REPNZ works similarly to REPE/REPZ except that now the operation is
repeated as long as CX0 and ZF=0. Comparison or scanning is to be performed as long
as the string elements are unequal (ZF=0) and the end of the string is not yet found
(CX0).
Prefix
REP
REPE/ REPZ
REPNE/REPNZ
Example :
Used with
MOVS
STOS
CMPS
SCAS
CMPS
SCAS
Meaning
Repeat while not end of
string CX0
CX0 & ZF=1
CX0 & ZF=0
CLD
; DF =0
MOV AX, DATA SEGMENT ADDR
MOV DS, AX
MOV AX, EXTRA SEGMENT ADDR
MOV ES, AX
MOV CX, 20
MOV SI, OFFSET MASTER
MOV DI, OFFSET COPY
REP MOVSB
Moves a block of 32 consecutive bytes from the block of memory locations starting at
offset address MASTER with respect to the current data segment (DS) to a block of
locations starting at offset address copy with respect to the current extra segment (ES).
Auto Indexing for String Instructions:
SI & DI addresses are either automatically incremented or decremented based on the
setting of the direction flag DF.
When CLD (Clear Direction Flag) is executed DF=0 permits auto increment by 1.
When STD (Set Direction Flag) is executed DF=1 permits auto decrement by 1.
Mnemonic
Meaning
Format
Operation
CLD
STD
Clear DF
Set DF
CLD
STD
(DF) 0
(DF) 1
Flags
affected
DF
DF
1. LDS Instruction:
LDS register, memory (Loads register and DS with words from memory)
This instruction copies a word from two memory locations into the register specified in
the instruction. It then copies a word from the next two memory locations into the DS
register. LDS is useful for pointing SI and DS at the start of the string before using one
of the string instructions. LDS affects no flags.
Example 1 :LDS BX [1234]
Copy contents of memory at displacement 1234 in DS to BL. Contents of 1235H to BH.
Copy contents at displacement of 1236H and 1237H is DS to DS register.
Example 2:
3. LES instruction :
LES register, memory
Example 1:
LES BX, [789A H]
(BX) [789A] in DS
(ES) [789C] in DS
Example 2 :
LES DI, [BX]
(DI) [BX] in DS
(ES) [BX+2] in DS
Assembler Directives
ASSUME
DB - Defined Byte.
DD - Defined Double Word
DQ - Defined Quad Word
DT - Define Ten Bytes
DW - Define Word
ASSUME Directive - The ASSUME directive is used to tell the assembler that the name
of the logical segment should be used for a specified segment. The 8086 works directly
with only 4 physical segments: a Code segment, a data segment, a stack segment, and
an extra segment.
Example:
ASUME CS: CODE; this tells the assembler that the logical segment named CODE
contains the instruction statements for the program and should be treated as a code
segment.
ASUME DS:DATA ;This tells the assembler that for any instruction which refers to a
data in the data segment, data will found in the logical segment DATA.
DB - DB directive is used to declare a byte type variable or to store a byte in memory
location.
Example:
1. PRICE DB 49h, 98h, 29h; Declare an array of 3 bytes, named as PRICE and
initialize.
2. NAME DB ABCDEF; Declare an array of 6 bytes and initialize with ASCII code for
letters
3. TEMP DB 100 DUP(?) ;Set 100 bytes of storage in memory and give it the name as
TEMP, but leave the 100 bytes uninitialized. Program instructions will load values into
these locations.
DW - The DW directive is used to define a variable of type word or to reserve storage
location of type word in memory.
Example:
MULTIPLIER DW 437Ah; this declares a variable of type word and named it as
MULTIPLIER. This variable is initialized with the value 437Ah when it is loaded
into memory to run.
EXP1 DW 1234h, 3456h, 5678h; this declares an array of 3 words and initialized with
specified values.
STOR1 DW 100 DUP(0); Reserve an array of 100 words of memory and initialize all
words with 0000.Array is named as STOR1.
END - END directive is placed after the last statement of a program to tell the assembler
that this is the end of the program module. The assembler will ignore any statement
after an END directive. Carriage return is required after the END directive.
ENDP - ENDP directive is used along with the name of the procedure to indicate the end
of a procedure to the assembler
Example:
SQUARE_NUM PROCE; It start the procedure; some steps to find the square root of a
number
SQUARE_NUM ENDP; Hear it is the End for the procedure
END - End Program
ENDP - End Procedure
ENDS - End Segment
EQU - Equate
EVEN - Align on Even Memory Address
EXTRN
ENDS - This ENDS directive is used with name of the segment to indicate the end of that
logic segment.
Example:
CODE SEGMENT; Hear it Start the logic ;segment containing code
; Some instructions statements to perform the logical
;operation
CODE ENDS ;End of segment named as ;CODE
EQU - This EQU directive is used to give a name to some value or to a symbol. Each
time the assembler finds the name in the program, it will replace the name with the
value or symbol you given to that name.
Example:
FACTOR EQU 03H; you has to write this statement at the starting of your program and
later in the program you can use this as follows
ADD AL, FACTOR; When it codes this instruction the assembler will code it as ADDAL,
03H ;The advantage of using EQU in this manner is, if FACTOR is used many no of times
in a program and you want to change the value, all you had to do is change the EQU
statement at beginning, it will changes the rest of all.
EVEN - This EVEN directive instructs the assembler to increment the location of the
counter to the next even address if it is not already in the even address. If the word is at
even address 8086 can read a memory in 1 bus cycle. If the word starts at an odd
address, the 8086 will take 2 bus cycles to get the data. A series of words can be read
much more quickly if they are at even address. When EVEN is used the location counter
will simply incremented to next address and NOP instruction is inserted in that
incremented location.
Example:
DATA1 SEGMENT
; Location counter will point to 0009 after assembler reads
; next statement
SALES DB 9 DUP (?); declare an array of 9 bytes
EVEN ; increment location counter to 000AH
RECORD DW 100 DUP( 0 ) ;Array of 100 words will start
;from an even address for quicker read
DATA1 ENDS
GROUP - Group Related Segments
LABLE
NAME
OFFSET
ORG Originate
GROUP - The GROUP directive is used to group the logical segments named after the
directive into one logical group segment.
INCLUDE - This INCLUDE directive is used to insert a block of source code from the
named file into the current source module.
PROC - Procedure
PTR - Pointer
PUBLC
SEGMENT
SHORT
TYPE
PROC - The PROC directive is used to identify the start of a procedure. The term near or
far is used to specify the type of the procedure.
Example:
SMART PROC FAR ; This identifies that the start of a procedure named as SMART and
instructs the assembler that the procedure is far .
SMART ENDP This PROC is used with ENDP to indicate the break of the procedure.
PTR - This PTR operator is used to assign a specific type of a variable or to a label.
Example:
INC [BX] ; This instruction will not know whether to increment the byte pointed to by
BX or a word pointed to by BX.
INC BYTE PTR [BX] ;increment the byte
;pointed to by BX
This PTR operator can also be used to override the declared type of variable . If we want
to access the a byte in an array WORDS DW 437Ah, 0B97h, MOV AL, BYTE PTR
WORDS
PUBLIC - The PUBLIC directive is used to instruct the assembler that a specified name
or label will be accessed from other modules.
Example:
PUBLIC DIVISOR, DIVIDEND ;these two variables are public so these are available to
all modules. If an instruction in a module refers to a variable in another assembly
module, we can access that module by declaring as EXTRN directive.
TYPE - TYPE operator instructs the assembler to determine the type of a variable and
determines the number of bytes specified to that variable.
Example:
Byte type variable assembler will give a value 1
Word type variable assembler will give a value 2
Double word type variable assembler will give a value 4
ADD BX, TYPE WORD_ ARRAY ; hear we want to increment BX to point to next word in
an array of words.
REVIEW QUESTIONS
1.
2.
3.
4.
5.
c) a & b
c) a & b
c)RST7.5&RST6.5
c) INTR, TRAP
c) none
13. In 8086, Example for Non maskable interrupts are
a) Trap
b) RST6.5
c) INTR
14. What does microprocessor speed depends on?
a) Clock
b) Data bus width
c) Address bus width
15. Can ROM be used as stack?
a) Yes b) No c) sometimes yes, sometimes no
16. Which processor structure is pipelined?
a) all x80 processors
b) all x85 processors
a) 0023H
b) 0024H
c) 0033H
c) a & b
c) 12000H
c) 1A00H
Key:
1 C 2 C 3 C 4 B 5 B 6 B 7 A 8 B 9 A 10 C 11 B 12 B 13 A 14 C 15 B 16 C 17 C 18 B 19 D
20 B 21 A 22 B 23 A 24 B