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SuccessiveapproximationADCWikipedia,thefreeencyclopedia

SuccessiveapproximationADC
FromWikipedia,thefreeencyclopedia

AsuccessiveapproximationADCisatypeofanalogtodigitalconverterthatconvertsacontinuous
analogwaveformintoadiscretedigitalrepresentationviaabinarysearchthroughallpossible
quantizationlevelsbeforefinallyconverginguponadigitaloutputforeachconversion.

Contents
1Blockdiagram
2Algorithm
3ChargeredistributionsuccessiveapproximationADC
3.1Usewithnonidealanalogcircuits
4Seealso
5References
6Externallinks

Blockdiagram
Key
DAC=DigitaltoAnalogconverter
EOC=endofconversion
SAR=successiveapproximationregister
S/H=sampleandholdcircuit
Vin=inputvoltage
Vref=referencevoltage

Algorithm
ThesuccessiveapproximationAnalogtodigital
convertercircuittypicallyconsistsoffourchief
subcircuits:

SuccessiveApproximationADCBlockDiagram

1. Asampleandholdcircuittoacquiretheinputvoltage(Vin).
2. AnanalogvoltagecomparatorthatcomparesVintotheoutputoftheinternalDACand
outputstheresultofthecomparisontothesuccessiveapproximationregister(SAR).
3. Asuccessiveapproximationregistersubcircuitdesignedtosupplyanapproximatedigital
codeofVintotheinternalDAC.
4. AninternalreferenceDACthat,forcomparisonwithVREF,suppliesthecomparatorwithan
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analogvoltageequaltothedigitalcodeoutputoftheSARin.
Thesuccessiveapproximationregisterisinitializedsothatthemostsignificantbit(MSB)isequaltoa
digital1.ThiscodeisfedintotheDAC,whichthensuppliestheanalogequivalentofthisdigitalcode
(Vref/2)intothecomparatorcircuitforcomparisonwiththesampledinputvoltage.Ifthisanalogvoltage
exceedsVinthecomparatorcausestheSARtoresetthisbitotherwise,thebitislefta1.Thenthenext
bitissetto1andthesametestisdone,continuingthisbinarysearchuntileverybitintheSARhasbeen
tested.Theresultingcodeisthedigitalapproximationofthesampledinputvoltageandisfinallyoutput
bytheSARattheendoftheconversion(EOC).
Mathematically,letVin=xVref,soxin[1,1]isthenormalizedinputvoltage.Theobjectiveisto
approximatelydigitizextoanaccuracyof1/2n.Thealgorithmproceedsasfollows:
1. Initialapproximationx0=0.
2. ithapproximationxi=xi1s(xi1x)/2i.
where,s(x)isthesignumfunction(sgn(x))(+1forx0,1forx<0).Itfollowsusingmathematical
inductionthat|xnx|1/2n.
Asshownintheabovealgorithm,aSARADCrequires:
1. AninputvoltagesourceVin.
2. AreferencevoltagesourceVreftonormalizetheinput.
3. ADACtoconverttheithapproximationxitoavoltage.
4. AComparatortoperformthefunctions(xix)bycomparingtheDAC'svoltagewiththe
inputvoltage.
5. ARegistertostoretheoutputofthecomparatorandapplyxi1s(xi1x)/2i.

Example:Thetenstepstoconvertingananaloginputto10bitdigital,usingsuccessiveapproximation,
isshownhere,forallvoltagesfrom5Vto0Vin0.1Viterations.Sincethereferencevoltageis5V,when
theinputvoltageisalso5Vallbitsareset.Asthevoltageisdecreasedto4.9V,onlysomeoftheleast
significantbitsarecleared.TheMSBwillremainsetuntiltheinputisonehalfthereferencevoltage,
2.5V.
Thebinaryweightsassignedtoeachbit,startingwiththeMSB,are2.5,1.25,0.625,0.3125,0.15625,
0.078125,0.0390625,0.01953125,0.009765625,0.0048828125.Alloftheseaddupto4.9951171875,
meaningbinary1111111111,andisoneLSBlessthan5.
WhentheanaloginputisbeingcomparedtotheinternalDACoutput,iteffectivelyisbeingcomparedto
eachofthesebinaryweights,startingwiththe2.5Vandeitherkeepingitorclearingitasaresult.Then
byaddingthenextweighttothepreviousresult,comparingagain,andrepeatinguntilallthebitsand
theirweightshavebeencomparedtotheinput,theendresult,abinarynumber,representingtheanalog
input,isfound.
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Chargeredistributionsuccessive
approximationADC
Oneofthemostcommonimplementationsofthesuccessive
approximationADC,thechargeredistributionsuccessive
approximationADC,usesachargescalingDAC.Thecharge
scalingDACsimplyconsistsofanarrayofindividuallyswitched
binaryweightedcapacitors.Theamountofchargeuponeach
capacitorinthearrayisusedtoperformtheaforementioned
binarysearchinconjunctionwithacomparatorinternaltothe
DACandthesuccessiveapproximationregister.

ADCusingsuccessiveapproximation

1. First,thecapacitorarrayiscompletely
dischargedtotheoffsetvoltageofthe
comparator,VOS.Thisstepprovides
automaticoffsetcancellation(i.e.The
offsetvoltagerepresentsnothingbut
deadchargewhichcan'tbejuggledby
thecapacitors).
2. Next,allofthecapacitorswithinthe
arrayareswitchedtotheinputsignal,

ChargeScalingDAC

vIN.Thecapacitorsnowhaveacharge
equaltotheirrespectivecapacitancetimestheinputvoltageminustheoffsetvoltageupon
eachofthem.
3. Inthethirdstep,thecapacitorsarethenswitchedsothatthischargeisappliedacrossthe
comparator'sinput,creatingacomparatorinputvoltageequaltovIN.
4. Finally,theactualconversionprocessproceeds.First,theMSBcapacitorisswitchedto
VREF,whichcorrespondstothefullscalerangeoftheADC.Duetothebinaryweightingof
thearraytheMSBcapacitorformsa1:1chargedividerwiththerestofthearray.Thus,the
inputvoltagetothecomparatorisnowvINplusVREF/2.Subsequently,ifvINisgreaterthan
VREF/2thenthecomparatoroutputsadigital1astheMSB,otherwiseitoutputsadigital0
astheMSB.Eachcapacitoristestedinthesamemanneruntilthecomparatorinputvoltage
convergestotheoffsetvoltage,oratleastascloseaspossiblegiventheresolutionofthe
DAC.

Usewithnonidealanalogcircuits
Whenimplementedasananalogcircuitwherethevalueofeachsuccessivebitisnotperfectly2^N
(e.g.1.1,2.12,4.05,8.01,etc.)asuccessiveapproximationapproachmightnotoutputtheidealvalue
becausethebinarysearchalgorithmincorrectlyremoveswhatitbelievestobehalfofthevaluesthe
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unknowninputcannotbe.Dependingonthedifferencebetweenactualandidealperformance,the
maximumerrorcaneasilyexceedseveralLSBs,especiallyastheerrorbetweentheactualandideal2^N
becomeslargeforoneormorebits.Sincewedon'tknowtheactualunknowninput,itisthereforevery
importantthataccuracyoftheanalogcircuitusedtoimplementaSARADCbeveryclosetotheideal
2^Nvaluesotherwise,wecannotguaranteeabestmatchsearch.

Seealso
Quantizationnoise
Digitaltoanalogconverter

References
R.J.Baker,CMOSCircuitDesign,Layout,and

3bitssimulationofacapacitiveADC

Simulation,ThirdEdition,WileyIEEE,2010.ISBN978
0470881323

Externallinks
UnderstandingSARADCs(http://www.maxim
ic.com/appnotes.cfm/appnote_number/1080/CMP/WP50)
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