PPT(10/8/2010)
1.1
Digital Electronics II
Mike Brookes
Please pick up: Notes from
f
the front
f
desk
2. Where is it used ?
3. Why is it used ?
NOTATION.PPT(10/8/2010)
Lecture List
Notation,, Cause and Effect
1: Notation, Cause and Effect, Flipflops, Counters
Addition Circuits
13: Adders and propagation delays
14. Fast Adders: bit inversion & carry lookahead
15. Fast adders: Carry skip and carry save
1.2
NOTATION.PPT(10/8/2010)
1.3
Lecture Notes
Very concise - ensure you understand each sentence.
Book
Tocci, Widmer & Moss, Digital Systems: Principles &
Applications, Pearson, 11th ed, 2010.
ISBN 0130387932
Covers most of the course though not in the same order. I
do not follow any book closely.
Problem Sheets
Problems graded:
everyone should do A, B and C
D and E are harder
Tutorial questions
URL
htt //
http://www.ee.ic.ac.uk/hp/staff/dmb/courses/dig2/dig2.htm
i
k/h / t ff/d b/
/di 2/di 2 ht
Discussion Group
http://learn.imperial.ac.uk
Office
O
ce Hours
ou s
Room 812: Mon 10:00-11:00 and Fri 15:00-16:00
NOTATION.PPT(10/8/2010)
1.4
Lecture 1
Objectives
NOTATION.PPT(10/8/2010)
1.5
Notation
Logic Levels
A logic
g 1 ((or high)
g ) is always
y the most p
positive of the two
voltage levels.
e.g. CMOS: 0 & 5V, ECL 1.75 & 0.9V
Gates
The label indicates how many of the inputs must be high
to make the output high:
&
AND gate: all inputs high
1
OR gate: one or more inputs high
=1
Exclusive-OR: exactly one input high
2n
Even Parity: even number of inputs high
Inversion Triangles
We can invert signals on the way in or on the way out:
A
B
!X
NOTATION.PPT(10/8/2010)
1.6
B
X
I
Input
t B going
i high
hi h causes X to
t go low
l
Input A going low causes X to go high
P
Propagation
ti Delay:
D l
The time delay between a cause (an input
changing) and its effect (an output changing).
typ
max
A to X (tPHL)
15
1.5
45
4.5
65
6.5
ns
A to X (tPLH)
1.5
6.0
8.0
ns
tPHL and tPLH refer to the direction that the output changes:
high-to-low or low-to-high.
NOTATION.PPT(10/8/2010)
1.7
D-Flipflop
DATA
CLOCK
1D
C1
CLOCK
DATA
Q
Notation:
N
t ti
>
input effect happens on the rising edge
C1 C Clock input, 1 This input is input number 1.
1D D Data input,
1 This input is controlled by input number 1
1.
The meaning of a number depends on its position:
A number after a letter is used to identify a particular input.
A number before a letter means that this input is controlled
by one of the other inputs.
NOTATION.PPT(10/8/2010)
1.8
Ripple Counter
Q0
Q1
1D
CLOCK
1D
C1
Q2
1D
C1
C1
Notation:
N
t ti
Notice inverters on the CLOCK and DATA inputs
Least significant bit of a number is always labelled 0
CLOCK
Q0
Q1
Q2
Q2:0
NOTATION.PPT(10/8/2010)
1.9
Synchronous Counter
CLOCK
C1
Q0
Q1
Q2
D0
Logic
D=Q+1
1D
Q0
D1
Q1
D2
Q2
Notation:
A register is a bunch of flipflops with the same CLOCK.
The individual flipflops are rectangles stacked on top of
each other. Only the top one is labelled.
All shared signals (e.g. the CLOCK input) go to the
notched common control block at the top of the stack.
The logic
g block must add 1 onto the current value of the
counter, Q, to generate the next value of the counter, D.
Suppose it has a propagation delay of 10 ns.
All flipflops change state within a fraction of a nanosecond.
CLOCK
Q2:0
D2:0
P
Propagation
ti D
Delays:
l
CLOCK to
t Qi = 6ns
6
CLOCK to Di = 16ns
NOTATION.PPT(10/8/2010)
1.10
Dependency Notation
Input Labels:
Inputs
p
are labelled with a function letter to show what
effect they have on the circuit. They have this effect
whenever they are high (i.e. at logic 1).
The function letter is usually followed by an identification
number (which must be unique):
C1
M7
D
Clock number 1
Mode input number 7
Data input (no identification number)
Dependencies:
If an input is affected by one or more other signals, we list
their identification numbers in front of the function
letter:
3,2,5D
3 2 5D
Data
D
t input
i
t affected
ff t d by
b input
i
t 3,2
3 2 and
d 5 iin th
thatt
order.
NOTATION.PPT(10/8/2010)
1.11
Device Types
&, 1, =1
(blank)
MUX
CTR
SRG
RAM
Gates
Latch, Flipflop or register
Multiplexer
Adder
Multiplier
Counter
Shift Register
Read/Write memory
Note: These lists are for reference only. You are not
expected to memorize them.
NOTATION.PPT(10/8/2010)
1.12
Quiz Questions
1. The voltage levels for the TTL logic family are 0.4 V and
2.8 V. Which one of these corresponds to logic 1?
2. If a gate is labelled 1, under what circumstances will
the output be high?
3. What does the propagation delay of a circuit mean?
4. Why does it make no sense to talk about the
propagation delay between a flipflops DATA input and
the flipflops output?
5. A flipflops inputs are labelled C1 and 1D respectively.
Why does the 1 come after the C but before the D?
6. What is the meaning of the > sign just before the C1 in
a flipflops symbol?
7 What is the meaning of a triangle drawn where an input
7.
or output wire meets a logic symbol?
8. What is a register?
Answers are all in the notes.
INTERFACING.PPT(01/10/2009)
2.1
Lecture 2
Objectives
Explain
E
l i h
how d
data
t is
i sentt between
b t
two
t
digital
di it l systems
t
using a synchronous bit-serial protocol
Synchronous: same clock at transmitter & receiver
Bit-serial: Only one bit sent at a time
Protocol: The procedure for exchanging
information
g
the timing
g constraints in a transmission
Investigate
system
INTERFACING.PPT(01/10/2009)
2.2
DATA
CLOCK
CLOCK
FRAME
DATA
B senses
1 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0
134
0 1 0
18
T
Transmitting
itti 8 bit values
l
ffrom A tto B
B:
FRAME indicates the first bit of each value; the other 7
bits follow on consecutive clock cycles. The FRAME
signal is often called a frame sync pulse.
DATA changes
h
on the
th falling
f lli CLOCK edge
d
Propagation delays are often omitted from diagram.
DATA is sensed by system B on the rising CLOCK
edge to maximise tolerance to timing errors. We must
always clock a flipflop at a time when its DATA input is
not changing.
INTERFACING.PPT(01/10/2009)
2.3
Transmission Delays
Examples:
Coax
C
cable:
bl
c r 20 cm/ns for r =2.3 (teflon)
PCB with ground plane:
1.4c ((1.4+r) cm/ns 17 cm/ns for r =5 ((fibreglass)
g
)
Rule-of-thumb:
Data travels along typical wires and circuit board tracks at
about 15 cm/ns: half the speed of light.
INTERFACING.PPT(01/10/2009)
2.4
Timing Specifications
A
CA
tD
DA
C1
1D
C1
tC
CLOCK
Time:
DB
CB
tP
CA
CB
DA
DB
Time:
tP
T
tC, tD
tP+tD
T+tC
P
Propagation
ti delay
d l ffor d
device
i A
A.
Clock Period.
Transmission line delays for CLOCK and DATA
F Device
For
D i B:
B
INTERFACING.PPT(01/10/2009)
2.5
tH
DATA
CLOCK
1D
tS
Q
CLOCK
C1
DATA
Q
tP
DATA mustt be
b held
h ld constant
t t ffor att least
l
t
tH after the CLOCK edge.
INTERFACING.PPT(01/10/2009)
2.6
Timing Constraints
A
CA
tD
DA
DB
CB
C1
1D
C1
tC
CLOCK
0
CA
DA
DB
CB
For Device B:
tP+tD
T+tC
T+tP+tD
D t input
Data
i
t (DB) changes
h
att tP+tD (and
( d T+
T tP+tD )
INTERFACING.PPT(01/10/2009)
2.7
Example Values
A
CA
DA
tD
C1
CLOCK
DB
CB
1D
C1
tC
F Motorola
For
M t l 56001 27MH
27MHz DSP processor:
INTERFACING.PPT(01/10/2009)
2.8
DA
tD
C1
CLOCK
DB
CB
1D
C1
tC
Setup
p Requirement:
q
tP + tD + tS < T + tC
T+tC + tH < tP + tD + T
Hold Requirement:
No.
INTERFACING.PPT(01/10/2009)
2.9
Quiz Questions
1. What is a bit-serial transmission system?
2 What is a synchronous transmission system?
2.
3. In a synchronous transmission system in which the
transmitted data changes on the rising edge of the
CLOCK, why is it normal for the receiver to sense the
data on the falling edge of the CLOCK ?
4. What is the purpose of the frame sync signal In a
synchronous bit-serial transmission system?
5. How far does a signal travel along a typical wire in one
nanosecond?
6. What do the terms setup time and hold time mean?
7. Why do you get a pair of timing inequalities for each
flipflop or register in a circuit?
8. In formulating the timing inequalities, how do you
choose what to use for a quantity whose value may lie
anywhere within a particular range?
Answers are all in the notes.
INTERFACING.PPT(01/10/2009)
2.10
Lecture 3
Objectives
Explain
E
l i h
how d
data
t is
i sentt between
b t
two
t
digital
di it l systems
t
using an asynchronous bit-serial protocol
INTERFACING.PPT(01/10/2009)
2.11
1
Start Bit
1
Stop Bit
Time/T: 0
1 2 3 4 5 6 7 8
INTERFACING.PPT(01/10/2009)
2.12
1+
CT0:7
CT=0
G1
ZERO
The CT
CT=0
0 output from counter goes high when the contents of the
counter, CT, are zero. Generate this signal using a NOR gate
connected to all 8 counter outputs.
INTERFACING.PPT(01/10/2009)
2.13
RS232 Receiver
DATA
CLOCK cycle:
2C1/2
Timing
Circuit
CT=24,...,136
CT0:7
see previous
slide for
details
DATA
Decode
D
d
Logic
MID
G2
1D
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
INTERFACING.PPT(01/10/2009)
2.14
Double Buffering
151
DATA
}
CLOCK cycle:
24 40
The 8 data bits only stay in the shift register for 3T before
they get shifted out again by the next data byte.
Host microprocessor must respond to an interrupt within
this time and retrieve the data.
Use a second register to grab the data at T=151 and
keep it for a whole 10T. This gives the P more time.
TRANSFER
SRG
CLOCK (16 baud rate)
2C1/2
G2
CT=151
CT=24,...,136
Timing
Ti
i Ci
Circuitit
&
Decode Logic
DATA
2C1
G2
MID
1D
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
1D
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
INTERFACING.PPT(01/10/2009)
2.15
Timing Errors
Ideal situation:
Receiver clock period P = T/16
Counter starts counting exactly on DATA falling edge
Real situation:
Receiver clock period not exactly T/16
Counter starts with some delay
On first rising edge of P after DATA goes low
P slightly
too small
P much
too small
INTERFACING.PPT(01/10/2009)
2.16
DATA
CLOCK
CT
Neglecting
eg ect g logic
og c p
propagation
opagat o de
delays,
ays, 0 < < P where
e e P is
s
receiver clock period.
Count 01 a time after the START bit
Count n n+1 a time nP+ after the START bit
Timing in the last (MSB) bit cell:
Sample
Instant
8T
9T
DATA
Counter: CT
135
136
137
MID
136P+
We will sample the correct bit cell if: 8T < 136P+ < 9T
8T < 136P+0
136P+P < 9T
T/P < 17
T/P > 15.2
INTERFACING.PPT(01/10/2009)
2.17
Quiz Questions
1. How can you be sure that in the RS232 protocol there
will always be a high-to-low transition at the beginning
of each transmitted byte ?
2. What is the function of the clock enable input on a
counter or register?
3 What logic gate is needed to detect when the contents
3.
of a counter is equal to zero?
4. If an asynchronous protocol has one START bit, eight
data bits and one STOP bit, how may bitcell periods is it
from the beginning of the START bit until the centre of
the STOP bit?
5. What is the function of an input pin that is labelled
2C1/2?
6. If the CLOCK input of a counter has period P, what is
the range of possible delays between the counters
enable pin going high and the counter incrementing?
7. What is the purpose of double buffering the data in an
asynchronous
h
bit
bit-serial
i l receiver?
i ?
8. How can you tell if a binary number is an odd multiple of
16?
Answers are all in the notes.
INTERFACING.PPT(01/10/2009)
2.18
Lecture 4
Objectives
E l i h
Explain
how memory iis connected
t d tto a microprocessor
i
INTERFACING.PPT(01/10/2009)
2.19
$FFFF
$
I
Input/Output
/O
$F000
$EFFF
ROM
16k words
Addresses (hexadecimal)
$B000
Unused
$7FFF
RAM
32k words
$0000
INOUT =
ROM
=
RAM
=
A15:12
F:
E:
D:
C:
B:
A:
9:
8:
7:
6:
5:
4:
3:
2:
1:
0:
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Input/Output
ROM
ROM
ROM
ROM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
INTERFACING.PPT(01/10/2009)
2.20
Memory
A
A15:0
16
16
D7:0
D
Control
Signals
D
8
Control
Signals
CLOCK
INTERFACING.PPT(01/10/2009)
2.21
INTERFACING.PPT(01/10/2009)
2.22
M em ory
A
A15:0
16
16
D 7:0
8
D
8
M C LO C K
W RITE
C LO CK
Write Cycle
MCLOCK
A15:0
WRITE
from P
D7:0
from mem
INTERFACING.PPT(01/10/2009)
2.23
Read Cycle
Write Cycle
MCLOCK
A15:0
WRITE
from P
D7:0
from mem
INTERFACING.PPT(01/10/2009)
2.24
Dynamic RAM:
8k 8 Static RAM
RAM
8192 8
A12:0
WR
OE
CE
A
WR
D7:0
CE
OE
WR
D0:7
Action
0
1
1
1
?
0
1
?
?
0
0
1
Hi Z
Hi Z
Out
In
Disabled
Idle
Read
Write
OE
CE
CE
OE
A12:0
WR
D7:0
INTERFACING.PPT(01/10/2009)
2.25
8k 8 Static RAM
The 64k memory cells are arranged in a square array:
256 Cells
8 32
= 256 cells
32 cells
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
32
cells
A12:0
(8192-way multiplexer)
CEWR
Dn
CEOE!WR
INTERFACING.PPT(01/10/2009)
2.26
Quiz Questions
1. What is the memory map of a microprocessor system
2 Why do all microprocessor systems include some read
2.
readonly memory (ROM)
3. What does it mean if a digital device has a tri-state
output? When are such outputs necessary ?
4. What is the difference between the chip enable and the
output enable inputs of a static RAM?
5. If a static RAM has n address inputs and m data
outputs, how many bits of information does it store?
6. What is the binary value of the three most significant
address bits for the hexadecimal address $BC37 ?
INTERFACING.PPT(01/10/2009)
2.27
Lecture 5
Objectives
IInvestigate
ti t the
th timing
ti i constraints
t i t for
f a microprocessor
i
when reading from or writing to memory.
INTERFACING.PPT(01/10/2009)
2.28
RAM
8192 8
A12:0
WR
OE
CE
A
WR
D7:0
CE
OE
WR
D0:7
Action
0
1
1
1
?
0
1
?
?
0
0
1
Hi Z
Hi Z
O t
Out
In
Disabled
Idle
R d
Read
Write
OE
CE
A12:0
D7:0
CE
p Enable: disabling
g chip
p cuts p
power by
y 80%.
%
Chip
OE
WR
INTERFACING.PPT(01/10/2009)
2.29
CEOE!WR
A12:0
D7:0
>5
<35
High, Low
<10 (20)
Constant, Hi Z
>5
<20 (35)
Care Input
{ Don't
Unknown Output
INTERFACING.PPT(01/10/2009)
2.30
>5
>30
A12:0
CEWR
CEOE!WR
D7:0
>5
<10
>15 >2
>5
INTERFACING.PPT(01/10/2009)
2.31
RAM
8k 8
A15:13
A
A15 0
A15:0
A12 0
A12:0
13
16
WRITE
D7:0
OE = MCLOCK !WRITE
OE
1
MCLOCK
CE
WR
WR = MCLOCK WRITE
250
500
MCLOCK
>33
<181
A15:0
WRITE
WR or OE
0 5
255
505
INTERFACING.PPT(01/10/2009)
2.32
<181
250
255
<378
505
500
>533
MCLOCK
A12:0
WRITE
D0:7
OE
WR
>15
RAM Requirements:
>5
>30
A12:0
D7 0
D7:0
D
W RITE
MCLOCK
>2
>5
RAM
8k 8
A
D
OE
WR
INTERFACING.PPT(01/10/2009)
2.33
>505
500 505 <515
MCLOCK
A12:0
WRITE
WR
OE
D0:7
P Requirements:
>30
>10,<83
A12:0
D7:0
D
W RITE
MCLOCK
RAM
8k 8
OE
WR
Requirements:
INTERFACING.PPT(01/10/2009)
2.34
>505
500 505 <515
MCLOCK
A12:0
WRITE
WR
OE
D0:7
P Requirements:
>30
>10,<83
A12:0
D7:0
D
W RITE
MCLOCK
RAM
8k 8
OE
WR
Requirements:
Min hold:
Max hold:
May need to add some delay to !OE signal to meet min hold
INTERFACING.PPT(01/10/2009)
2.35
Quiz Questions
1. What is the access time of a static RAM?
2 When writing to a static RAM
2.
RAM, why is does the state of
the data inputs matter only at the end of the write
pulse?
3. How do you check timing constraints if the manufacturer
specifies a maximum propagation delay but no
minimum ?
4. How do you check timing constraints if the validity of an
output depends on several of the input signals ?
SYNCSM.PPT(01/10/2009)
3.1
Lecture 6
Control Logic
Objectives
Understand
U
d t d how
h
digital
di it l systems
t
may b
be di
divided
id d iinto
t a
data path and control logic
SYNCSM.PPT(01/10/2009)
3.2
Control Logic
Most digital systems can be divided into
Data Path: adders,, registers
g
etc
Control Logic: generates timing signals to ensure
things happen at the right time and in the right order
Control logic can be implemented with:
Microprocessor/Microcontroller
+ Cheap, very flexible, design easy (software)
Slow: most actions require >20 instructions = 2 s @
clock speed of 10 MHz.
U ffor slow
Use
l
applications.
li ti
Counters/Shift Registers
+ Fast, Cheap, Very easy design.
Simple systems only.
A special case of synchronous state machines.
Use for very simple systems (fast or slow).
SYNCSM.PPT(01/10/2009)
3.3
Shift Registers
Easy way to make a sequence of events happen in response
to a trigger:
P, Q, R and S are delayed
versions of D but with all
transitions on the CLOCK
Delay from D to P is between
0 and 1 clock cycle.
TT
CLOCK
D
SRG
C1
1D
P
Q
R
S
CLOCK
D
P
Q
R
S
P!R
!RS
QR
SYNCSM.PPT(01/10/2009)
3.4
1D
GO
C1
R
1D
X
Y
Z
SYNCSM.PPT(01/10/2009)
3.5
CLOCK
GO
D
X
Y
RAMDAT
WR
ADDR
SYNCSM.PPT(01/10/2009)
3.6
Synchronous Counters
CLOCK
0001
CTR4
C1
D3:0
CLOCK
1D
CT
Q3:0
Q
Q3:0
15
14
13
12
11
10
1
B
SYNCSM.PPT(01/10/2009)
3.7
Synchronous RESET
CLOCK
!RST
0001
CTR4
C1
P
Q
CLOCK
C1/+
D3:0
1D
CT
!RST
Q3:0
1R
Q3:0
!RST
2
!RST
!RST
!RST
14
RST
3
RST
RST
!RST
13
RST
!RST
RST
RST
RST
4
!RST
!RST
RST
RST
12
5
RST
RST
!RST
!RST
RST
11
RST
RST
RST
!RST
!RST
10
!RST
!RST
!RST
SYNCSM.PPT(01/10/2009)
3.8
CTRDIV10
CLOCK
+/C1
Q3
Q2
Q1
Q0
3
CT
Q3
Q0
Notation:
1R
Q3
Q2
Q1
Q0
3
CT
0
CT = Contents
0 = least significant bit (LSB)
Bit k has a binary weight of 2k
1R means reset on next C1 (CLOCK edge)
1001 = 9
1011 = 11
1101 = 13
1111 = 15
10
11
12
13
14
15
SYNCSM.PPT(01/10/2009)
3.9
Output Glitches
If k counter bits change simultaneously, other logic
ccircuits
cu s us
using
g them
e may
ay b
briefly
e y see a
any
yo
of 2k poss
possible
be
values.
Glitches are possible at the logic circuit output if both:
1. These 2k values include any that would cause
the logic
g circuit output
p to change.
g
and 2. The logic circuit output is meant to remain at
a constant value.
CTR4
CLOCK
3
CT
0
Q3
Q2
Q1
Q0
Q0:3 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Q3
Q2
Q1
Q0
Y
SYNCSM.PPT(01/10/2009)
3.10
Q3
Q2
Q1
Q0
3
CT
0
1D
C1
Q0:3 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Q3
Q2
Q1
Q0
Y
Z
Alternatively
y use a count sequence
q
where only
y one bit
changes at a time (e.g. Gray code):
0
11
10
14
15
13
12
Top and bottom rows differ only in the MSB any even
count length can be made by branching to the bottom row
after
f half
h lf the
h counts. D
Dashed
h d liline gives
i
a 12
12 counter.
SYNCSM.PPT(01/10/2009)
3.11
Quiz Questions
SYNCSM.PPT(01/10/2009)
3.12
Lecture 7
Data Decoding with a Counter
U i a counter
Using
t tto measure ti
time iintervals
t
l
SYNCSM.PPT(01/10/2009)
3.13
Data Decoding
Task: Decode a data stream where a 0 or 1 is transmitted
as a pulse lasting 2/3T or 1/3T respectively.
Problem: you dont know the value of T.
0
IN
T
Method:
SYNCSM.PPT(01/10/2009)
3.14
Counter Symbol
CTR10X
IN
M3
RST
CLOCK
(1 MHz)
Q9
Q9
1R
C1/3+/3
Notation:
1R: The 1 means that this input only has any effect when C1
is active ((i.e. the rising
g edge
g of CLOCK).
) R means the RST
input sets the counter to zero when it is high.
SYNCSM.PPT(01/10/2009)
3.15
Method:
Use a 1-bit
1 bit shift register to generate a reset pulse
pulse.
IN
1D
CLOCK
RST
C1
(1 MHz)
CLOCK
IN
Z
RST
RST goes high for one clock cycle every time IN goes high
CLOCK
IN
Z
RST
SYNCSM.PPT(01/10/2009)
3.16
IN
1D
C1
1D
RST
C1
CLOCK
(1 MHz)
Potential Problem 2:
If IN changes just on the clock edge, Y (and RST) could oscillate.
Doesnt matter because the counter only looks at RST on
the next clock rising edge and the oscillation will be gone
byy then.
P = 1 s
CLOCK
IN
Y
Z
RST
Counter
x
Glitch
x+1
No reset
0
Reset
SYNCSM.PPT(01/10/2009)
3.17
C
Counter
t
+200
100
+100
200
SYNCSM.PPT(01/10/2009)
3.18
Y
RST
Counter
OUT
0
OUT gives the decoded data stream but one bitcell late.
SYNCSM.PPT(01/10/2009)
3.19
T / 3P 0.5 2n
T 1.5 2n P 1536 s
2:1
1:2
1
?
1:1
1 2
0
2:2
1
1
0
1
SYNCSM.PPT(01/10/2009)
3.20
IN
CLOCK
Y
V P
V+P
W P
WP
SYNCSM.PPT(01/10/2009)
3.21
Quiz Questions
SYNCSM.PPT(01/10/2009)
3.22
Lecture 8
Synchronous State Machine Analysis
Objectives
R i
Review
th
the d
definition
fi iti off a synchronous
h
state
t t machine
hi
pp
the alternative ways
y of drawing
g the state
Appreciate
diagram
SYNCSM.PPT(01/10/2009)
3.23
Inputs
CLOCK
NEXT_STATE
O t t
Outputs
C1
1D
STATE
Combinational
Logic
NEXT_STATE
Rules:
Never mess around with the clock signal
Never use asynchronous SET/RESET inputs to
register (asynchronous = independent of CLOCK)
SYNCSM.PPT(01/10/2009)
3.24
Outputs
C1
NEXT_STATE
1D
STATE
Combinational
Logic
NEXT_STATE
Which state to g
go to at the next CLOCK
This too may change during a state but the only thing
that matters is its value just before CLOCK
combinational
bi ti
l logic
l i has
h no internal
i t
l ffeedback
db k lloops
no memory
SYNCSM.PPT(01/10/2009)
3.25
CLOCK
NS0
C1
S0
1D
NS1
S1
NS0
State Table:
Truth table for the combinational logic:
One row per state: n flipflops 2n rows
One column per input combination:
m input signals 2m columns
Each cell specifies the next state and the output
signals during the current state
for clarity, we separate the two using a /
NS1,NS0/Y
S1,S0
A=0
A=1
00
01
10
11
11/0
11/0
11/1
01/1
10/1
10/0
10/0
01/1
SYNCSM.PPT(01/10/2009)
3.26
A=0
0
A=1
00
01
10
11
11/0
11/0
11/1
01/1
10/1
10/0
10/0
01/1
0
A
Y=A
2 A
Y=A
3
Y=1
S1:0
A=0
A=1
0
1
2
3
3
3
3
1
2
2
2
1
Output Signal: /Y
S1:0
A=0
A=1
0
1
2
3
/0
/0
/1
/1
/1
/0
/0
/1
Y=A
Y=0
Y=!A
Y=1
1 A
A Y=0
SYNCSM.PPT(01/10/2009)
3.27
Timing Diagram
A
0
A
Y=A
2 A
Y=A
3
Y=1
1 A
A Y=0
CLOCK
A
State: S1:0
St t S
State
Sequence:
Determine this first. Next state depends on input
values just before CLOCK .
Output Signals:
Defined by Boolean expressions within each state.
If all the expressions are constant 0 or 1 then outputs
only ever change on clock . (Moore machine)
If any expressions involve the inputs (e.g. Y=A) then
it is possible for the outputs to change in the middle
of a state. (Mealy machine)
SYNCSM.PPT(01/10/2009)
3.28
Self-Transitions
A
0
A
Y=A
2 A
Y=A
3
Y=1
1 A
A Y=0
0
A
Y=A
2 A
Y=A
3
Y=1
1 A
A Y=0
SYNCSM.PPT(01/10/2009)
3.29
0
A
Y=A
2 A
Y=A
3
Y=1
1 A
A Y=0
A/1
3
Y=1
1 A
A Y=0
Output: /Y
Default: Y=0
SYNCSM.PPT(01/10/2009)
3.30
Output Glitches
When making a transition from one state to another, the
logic is likely to generate a glitch on an output if:
two or more state bits change
the output has the same value in both states
some combination of the changing state bits would
cause the output to change
A
0
A
Y=A
2 A
Y=A
3
Y=1
1 A
A Y=0
SYNCSM.PPT(01/10/2009)
3.31
CLOCK
NS0
C1
1D
NS1
S0
S1
NS0
CLOCK
A
State: S1:0
S0
S1
P = AS0
Y = PS1
The two inputs to the XOR gate (P and S1) are meant to
change simultaneously.
In fact S1 changes first because of the delay through the
NOR gate.
The XOR gate sees the effect of S1 changing before it
sees the effect of S0 changing. It is as if we went briefly
into state 3.
SYNCSM.PPT(01/10/2009)
3.32
Quiz Questions
SYNCSM.PPT(01/10/2009)
3.33
Lecture 9
Synchronous State Machine Design
Objectives
To learn
T
l
how
h
tto design
d i a state
t t machine
hi tto meett
specific objectives
SYNCSM.PPT(01/10/2009)
3.34
SYNCSM.PPT(01/10/2009)
3.35
(1)
0
a 00
b 001
c 11
11
b
/0
a
/0
1
a
/0
(2)
b
/0
c
/1
1
(3)
a
/0
0
b
/0
c
/1
(4)
d
/1
0
a
/0
d 110
0
b
/0
c
/1
d
/1
0
SYNCSM.PPT(01/10/2009)
3.36
Explanatory Notes
(1) If IN goes high for two (or more) clock cycles then OUT must
go high, whereas if it goes high for only one clock cycle then
OUT stays
t
llow. It follows
f ll
th
thatt th
the ttwo hi
histories
t i IN low
l
for
f
ages and IN low for ages then high for one clock are
different because if IN is high for the next clock we need
different outputs. Hence we need to introduce state b.
(2) If IN goes high for one clock and then goes low again, we can
forget it ever changed at all. This glitch on IN will not affect any
of our future actions and so we can just return to state a.
If on the other hand we are in state b and IN stays high for a
second clock cycle, then the output must change. It follows
that we need a new state, c.
(3) The need for state d is exactly the same as for state b earlier.
We reach state d at the end of an output pulse when IN has
returned low for one clock cycle. We dont change OUT yet
because it might be a false alarm.
(4) If we are in state d and IN remains low for a second clock
cycle, then it really is the end of the pulse and OUT must go
low. We can forget the pulse ever existed and just return to
state a.
SYNCSM.PPT(01/10/2009)
3.37
Equivalent States
An initial design often creates more states than are
necessary.
States A and B are said to be equivalent if, for any
possible input sequence, you get identical output
waveforms regardless of whether the initial state is A
or B.
You can simplify a state machine by merging equivalent
states into a single state.
Two states are definitely equivalent if:
They have the same outputs for every possible input
combination.
They have the same next state for every possible
input combination (assuming they themselves are
equivalent).
This rule wont always find all possible equivalent states
and so wont necessarily make the state machine as
simple as possible (you will learn a complete rule next
year).
SYNCSM.PPT(01/10/2009)
3.38
1
1
00
/0
0
01
/0
11
/1
10
/1
0
SYNCSM.PPT(01/10/2009)
3.39
NS1,NS0/OUT
S1,S0
IN=0
IN=1
00
01
11
10
00/0
00/0
10/1
00/1
01/0
11/0
11/1
11/1
NS1 IN ( S1 S 0) S1 S 0
NS 0 IN
OUT S1
IN
CLOCK
NS1
NS0
C1
1D
S1
S0
Combinational
Logic
OUT
NS1
NS0
SYNCSM.PPT(01/10/2009)
3.40
Unsynchronised Inputs
An input transition just before CLOCK can cause the NS
bits to change within the setup/hold window of the register.
If k of the NS bits change we might go to any of 2k states:
CLOCK
State
IN
NS1
NS0
S1
S0
State 3:
IN causes NS0:1 to change from 11 to 10 k=1.
NS0 too late for S0 but causes glitch on S0
S0 goes low on next CLOCK Everything
Everything is OK
OK.
State 2:
IN causes NS0:1 to change from 00 to 11 k=2.
NS0 changes in time so S0 1.
NS1 changes too late so S1 0.
0
Next state is 01 which is an ILLEGAL destination.
SYNCSM.PPT(01/10/2009)
3.41
Input Synchronization
An asynchronous input must be synchronized if in any
state it affects more than one of the next state bits.
Inputs can be synchronized by passing them through a
register before they go to the combinational logic:
CLOCK
IN
C1
1D
PIN
NS1
S1
NS0
S0
Combinational
Logic
Propagation
Delay = tl
OUT
NS1
NS0
11
PIN
10
PIN
00
T
CLOCK
IN
PIN
NS0:1
tw
tl
ts
SYNCSM.PPT(01/10/2009)
3.42
01
0
10
0
11
1
01
A
A
10
SYNCSM.PPT(01/10/2009)
3.43
INPUTS
STATE
R
Combination
nal
Logic
OUTPUTS
NEXT_STATE
SYNCSM.PPT(01/10/2009)
3.44
Quiz Questions
ANALOG.PPT(01/10/2009)
4.1
Lecture 10
Digital-to-Analog Conversion
Objectives
Understand how a weighted-resister
g
DAC can be
used to convert numbers with binary or non-binary bit
weightings
Understand the meaning of the terms used to specify
DAC accuracy
Understand
U d t dh
how an R
R-2R
2R lladder
dd can b
be used
d tto
convert both unsigned and signed binary numbers
Understand the offset binary representation of
negative numbers
ANALOG.PPT(01/10/2009)
4.2
Digital-to-Analog Conversion
We want to convert a binary number into a voltage
proportional to its value:
X3
V3
R3=1/G3
X2
V2
R2
X1
V1
R1
X0
V0
R0
VOUT
VOUT G3 V0 VOUT G0 0
VOUT
G3 G2 G1 G0
RThevenin
1
G3 G2 G1 G0
ANALOG.PPT(01/10/2009)
4.3
Output Op-Amp
X3
V3
R3=1/G3
X2
V2
R2
RF
VOUT
X1
V1
R1
X0
V0
R0
VOUT
RF
VThvenin RF V3G3 V2 G2 V1G1 V0 G0
RThvenin
Adding an op-amp:
The voltage at the junction of all the resistors is now
held constant by the feedback
Hence current drawn from V3 is independent of the other
voltages V2, , V0
Hence any gate non-linearity has no effect more
accurate.
ANALOG.PPT(01/10/2009)
4.4
DAC Jargon
1 LSB
3
4
X0:2
X0:2
Accuracy=1.8@X=3
Linearity=0.7@X=4
Non-monotonic@34 Diff Linearity=1
Linearity=1.2@
2@ 34
(all in units of LSB)
Resolution
Accuracy
Linearity
Differential Linearity
Worst error in V when XX+1
measures smoothness
Monotonic
ANALOG.PPT(01/10/2009)
4.5
R-2R Ladder
We want to generate currents I0, 2I0, 4I0,
2I0
2R
I0
V0
2R
V1 2I1
R
I0
2R
I1
I1
2R
I0
V0
2R
2I3
I0
2R
I3
2R
I2
2R
I1
2R
I0
R
V2
R
V1
R
V0
2R
I0
ANALOG.PPT(01/10/2009)
4.6
Current-Switched DAC
16I0
VIN
RF
8I0
4I0
0
1
2I0
0
1
I0
0
1
X3
3
X2
X3:0 I0
X1
VOUT
X0
I0
Total
ota current
cu e t into
to summing
su
g junction
ju ct o is
s X3:0
3:0 I0
Hence Vout = X3:0 Vin /16R Rf
We switch currents rather than voltages so that all
nodes in the circuit remain at a constant voltage
no need to charge/discharge
g
g node capacitances
p
faster.
Use CMOS transmission gates as switches: adjust
ladder resistors to account for switch resistance.
Each 2-wayy switch needs four transistors
ANALOG.PPT(01/10/2009)
4.7
Digital Attenuator
C b
Can
be used
d as a di
digital
it l attenuator:
tt
t
VIN
X7:0
DAC
VOUT= X VIN
ANALOG.PPT(01/10/2009)
4.8
Bipolar DAC
A bipolar DAC is one that can give out both positive and
negative voltages according to the sign of its input. There
are two aspects of the circuit that we need to change:
Number Representation
Normally we represent numbers using 2s complement
notation (because we can then use the same
addition/subtraction circuits).
For converters it is more convenient to use offset-binary
notation.
t ti
ANALOG.PPT(01/10/2009)
4.9
Signed Numbers
Value (v)
8
7
6
5
...
1
1
0
1
...
6
7
2s complement (y)
1000
1001
1010
1011
...
1111
0000
0001
...
0110
0111
(u=v+8)
0
1
2
3
7
8
9
14
15
ANALOG.PPT(01/10/2009)
4.10
8I0
VIN
X3:0 I0
X3
4I0
0
1
2I0
0
1
I0
0
1
2(X3:08) I0
X2
X1
X0
I0
(16X3:0) I0
Current
Mirror
(16X3:0) I0
ANALOG.PPT(01/10/2009)
4.11
Current Mirror
A
RF
A
AB
VOUT
+
B
B
VX
ANALOG.PPT(01/10/2009)
4.12
Quiz
Why
y is a weighted-resistor
g
DAC impractical
p
for a 16bit converter?
What is a multiplying DAC ?
Why is a current mirror circuit so-called?
What is the value of the bit pattern 1001 in the
following notations: (a) unsigned binary, (b) twos
complement binary, (c) offset binary ?
How do you convert a number from offset binary to
twos complement notation ?
ANALOG.PPT(01/10/2009)
4.13
Lecture 11
Objectives
Understand the relationship
p between the continuous
input signal to an Analog-to-Digital converter and its
discrete output
Understand the source and magnitude of quantisation
noise
Understand
U d t dh
how a fl
flash
h converter
t works
k
Understand how the use of dither can improve
resolution and decorrelate the quantization noise
ANALOG.PPT(01/10/2009)
4.14
ADC
XN1:0
N 10
VIN
X round
1 LSB
E
Example:
l
If 1 LSB = 0.5 V, then VIN = 2.8 V will be converted to:
2.8
X round
round 5.6 6
0.5
ANALOG.PPT(01/10/2009)
4.15
Sampling
To process a continuous signal in a computer or other
digital system, you must first sample it:
Time Quantisation
Amplitude Quantisation
ANALOG.PPT(01/10/2009)
4.16
1.11
Quantisation Noise
VREF
VIN
ADC
VREF
XN1:0
DAC
VOUT
VIN, VOUT
VOUT VIN
If all error values are equally likely, the RMS value of the
quantisation noise is
2
x dx
1
0.3 LSB
12
0.35 2 n
20 log10 (1.2 2 n ) 1.8 6n dB
20 log10
0.3
ANALOG.PPT(01/10/2009)
4.17
Threshold Voltages
VREF
VIN
ADC
XN1:0
N 10
Threshold Voltages
ANALOG.PPT(01/10/2009)
4.18
05
0.5
15
1.5
Use 2n1
1 comparators:
VIN
G2
VLO = 1.75 V
G3
G4
G5
G6
G7
G1
VHI = 1.25 V
X2
X1
X0
ANALOG.PPT(01/10/2009)
4.19
Priority Encoder
G7:1 can have 27 possible values but only 8 will occur:
G7:1
1111111
0111111
0011111
0001111
0000111
0000011
0000001
0000000
X2:0
011 =+3
010 =+2
001 =+1
000 =+0
111 =
=1
1
110 =2
101 =3
100 =4
Example: G2 !G4
0
0
0
0
1
1
0
0
G4 G2
ANALOG.PPT(01/10/2009)
4.20
1.11
VREF
XN1:0
ADC
VOUT
DAC
0.2
0.4
0.6
0.8
Time
0.2
0.4
0.6
0.8
Time
Correlation Coefficient
-0.5
-1
0
2
4
6
Triangle wave amplitude (+- LSB)
ANALOG.PPT(01/10/2009)
4.21
1.11
Dither
VREF
VIN
ADC
VREF
XNN1:0
1:0
VOUT
DAC
VOUT
1
0.8
0.6
0.4
0.2
0
05
0.5
2
3
15
1.5
2
25
2.5
W and VOUT (LSB)
35
3.5
ANALOG.PPT(01/10/2009)
4.22
1.11
Effects of Dither
VREF
VIN
VREF
XNN1:0
1:0
ADC
DAC
VOUT
before an ADC
before reducing digital precision (e.g. 16 to 8 bits)
Triangular pdf of amplitude 1 LSB at new precision
Good consequences
Quantisation
Q
ti ti noise
i llevell iis constant
t t iindependent
d
d t off VIN
Quant noise is uncorrelated with VIN no distortion
Signal variations are preserved even when < 1 LSB
Bad consequence
0.5
with dither
0.2
04
0.4
0.3
without dither
0.2
0.1
Correlation Coefficien
nt
with dither
0
-0.2
-0.4
-0.6
-0.8
08
without
ith t dith
dither
-1
0
0
2
4
6
8
Triangle wave amplitude (+- LSB)
2
4
6
8
Triangle wave amplitude (+- LSB)
ANALOG.PPT(01/10/2009)
4.23
Quiz
What is a bipolar
p
A/D converter ?
What is the amplitude of the quantisation noise
introduced by an A/D converter ?
How many threshold voltages are there in an n-bit
converter ?
What is the function of a priority encoder ?
What is the level of quantisation noise for large signal
variations ?
What are the good and bad consequences of adding
dither to a signal before conversion to digital ?
ANALOG.PPT(01/10/2009)
4.24
Lecture 12
Objectives
Understand the p
principles
p
behind a successive
approximation converter
Understand how a successive approximation
converter can be implemented using a state machine
Understand the need for using a sample/hold circuit
with
ith a successive
i approximation
i ti converter
t
Understand the origin of glitches at the output of a
DAC and how they can be avoided.
ANALOG.PPT(01/10/2009)
4.25
0.5
1.5
2.5
3.5
1 t guess: 0.25
1st
0 25 V
(too high)
X=1???
X=0???
2nd guess: 2.25 V
(too low)
X=11??
X=1110
X=111?
4th guess: 0.75 V
(too high)
ANALOG.PPT(01/10/2009)
4.26
DONE
VIN
HIGHER
VREF
STATE4:0
X3:0
DAC
State Diagram:
X3:0
ANALOG.PPT(01/10/2009)
4.27
0.5
1.5
2.5
3.5
X=1???
X=0???
2nd guess: 2.25
2 25 V
(too low)
X=11??
t
pu
In
X=111?
lta
Vo
ge
X=1111
ANALOG.PPT(01/10/2009)
4.28
VIN
ADC
DONE
VIN
Aperture time
Aperture uncertainty
Acquisition time
ANALOG.PPT(01/10/2009)
4.29
Sample/Hold Circuit
C
+
IN
SAMPLE
OUT
ANALOG.PPT(01/10/2009)
4.30
Sampling ADC
Many A/D converters include a sample/hold within them:
these are sampling A/D converters.
ANALOG.PPT(01/10/2009)
4.31
X=8
X=7
T
ANALOG.PPT(01/10/2009)
4.32
Deglitching
To minimize the effect of glitches:
Use a register to make inputs change as
simultaneously as possible
Use a sample/hold circuit to disconnect the DAC
output
p while it is changing
g g
CLOCK
D7:0
VREF
C1
1D
X7:0
DAC
VDAC
CONTROL
D7:0
CLOCK
X7:0
VDAC
CONTROL
VOUT
VOUT
ANALOG.PPT(01/10/2009)
4.33
Summary
D/A Converters:
Weighted resistor: very fast (no op-amp), each bit can
have an arbitrary weight, no good for big numbers.
R-2R ladder: used for most converters, switch
currents rather than voltages for higher speed.
Multiplying DAC has an analog input as well.
converters used for audio: very good linearity
linearity.
A/D Converters:
Flash converter: very fast (down to 1 ns), low
precision (8 bits max), expensive and power hungry. A
pipeline converter uses a DAC to subtract the
converted value and measures the difference with
another flash converter .
Successive
S
i A
Approximation:
i ti
medium
di
speed
d (d
(down tto
0.1 s), need to use sample/hold circuit to avoid input
changing during conversion.
converters dominate the medium to low speed
market ((down to 0.5 s).
) Long
g been standard for
audio: very good linearity (up to 24 bits). Very high
speed sampling at low precision with dither, followed
by low-pass digital filter and sub-sampling to desired
sample rate.
ANALOG.PPT(01/10/2009)
4.34
Quiz
How many
y voltage
g comparisons
p
are made by
y an n-bit
successive approximation converter during the course
of a conversion ?
What is a multiplying DAC ?
Why does the DAC in an n-bit successive
approximation converter only need to to generate 2n
1 different values rather than 2n ?
If a 12-bit successive approximation converter is used
without a sample/hold, which of the output values 127,
128 and 129 are likely to occur least frequently ?
What is the aperture uncertainty of a sample/hold
circuit ?
What two effects determine the acquisition time of a
sample/hold circuit ?
What happens if you try to improve a glitchy signal
using a low-pass filter ?
Adder.PPT(10/1/2009)
5.1
Lecture 13
Adder Circuits
Objectives
Understand how to add both signed and unsigned
numbers
Appreciate how the delay of an adder circuit depends
on the data values that are being added together
Adder.PPT(10/1/2009)
5.2
Full Adder
S
Q
CI
+ CI
C
Output is a 2
2-bit
bit number counting how many inputs are
high
P
0
0
0
0
1
1
1
1
Q
0
0
1
1
0
0
1
1
CI
0
1
0
1
0
1
0
1
C
0
0
0
1
0
1
1
1
S
0
1
1
0
1
0
0
1
C P Q P CI Q CI
S P Q CI
Note:
N t P Q CI = (P Q) CI = P (Q CI)
Adder.PPT(10/1/2009)
5.3
Propagation delays:
From
To
Delay
P Q or CI
P,Q
P,Q or CI
Adder.PPT(10/1/2009)
5.4
N-bit adder
We can make an adder of arbitrary size by cascading full
adder sections:
P0
Q0
C1
P1
P
S
S0
Q1
Q
CI
C0
P2
P
S
S1
Q2
Q
CI
P3
P
S
S2
Q3
P
S
Q
C2
C1
CI
S3
CI
C3
P0
P1
P2
P3
Q0
Q1
Q2
Q3
C1
0
P
0
3
0
S0
S1
S2
S3
Q
3
CI
C3
C3
Adder.PPT(10/1/2009)
5.5
P0
P1
P2
P3
0
P
S0
S1
S2
S3
S4
0
?
Q0
Q1
Q2
Q3
4
0
4
Q
?
0
C1
4
CI
C4
C4
Adder.PPT(10/1/2009)
5.6
0101
00000101
13
1101
00001101
Signed numbers
Expand a signed number by duplicating the MSB the
appropriate number of times:
5
0101
00000101
1101
11111101
Adder.PPT(10/1/2009)
5.7
P0
P1
P2
P3
0
P
S0
S1
S2
S3
S4
0
0
Q0
Q1
Q2
Q3
4
0
4
Q
0
0
C1
4
CI
C4
C4
P0
P1
P2
P3
0
P
3
Q0
Q1
Q2
Q3
S0
S1
S2
S3
S4
3
Q
3
0
C1
CI
C3
C3
Adder.PPT(10/1/2009)
5.8
P0
P1
P2
P3
0
P
S0
S1
S2
S3
S4
0
4
Q0
Q1
Q2
Q3
4
Q
4
0
C1
CI
C4
C4
P=0000, Q=1111
Unsigned P+Q=01111
P+Q 01111, Signed P+Q=11111
P+Q 11111
Adder.PPT(10/1/2009)
5.9
P0
Q0
C1
P1
P
S
S0
Q1
Q
CI
P0
C0
C0
P2
P
S
S1
Q2
Q
CI
C0
C1
P3
S
S2
Q3
S3
S
Q
C2
C1
CI
C1
CI
C2
C2
S4
S3
3
P, Q, CI C = 2
Adder.PPT(10/1/2009)
5.10
Answer 1 (B=0):
Initially: A=0, B=0 X=1, Y=0, Z=0, Q=0
Then: A Y Q
2 gate delays
Answer 2 (B=1):
Initially: A=0, B=1 X=1, Y=0, Z=1, Q=1
Then: A X Z Q
3 gate delays
Adder.PPT(10/1/2009)
5.11
Worst-Case Delays
We are normally interested only in the worst-case delay
from a change in any input to any of the outputs.
The worst-case delay determines the maximum clock
speed in a synchronous circuit:
CLOCK
C1
W
C1
X
1D
Logic
1D
CLOCK
W
X
Y
Z
time
tp
tp+tg
tp + tg + ts < T
Since the clock speed must be chosen to ensure that the
circuit always works, it is only the worst-case logic delay
that matters.
Adder.PPT(10/1/2009)
5.12
Quiz
1
1.
In an full adder
adder, why is it normally more important to
reduce the delay from CI to C than to reduce the
delay from P to S ?
2.
3.
How do you convert a 4-bit signed number into an 8bit signed number ?
4.
5.
Adder.PPT(10/1/2009)
5.13
Lecture 14
Adder.PPT(10/1/2009)
5.14
P1
P
S
S0
Q1
Q
CI
P0
C0
C0
2
P2
P
S
S1
Q2
Q
CI
C0
P3
S
S2
Q3
P
S
CI
C1
CI
C2
S3
C2
C1
C1
2
C2
S4
S3
3
Adder.PPT(10/1/2009)
5.15
P0
Q0
C1
P1
Q1
P1
P
S
C
P2
S0
Q1
Q
CI
S1
C0
C0
S1
Q2
Q
CI
C1
C1
P
S
S2
Q
C2
CI
C1
P1
Q1
Adder Stage 0
C0
C0
P2
C1a
C1b
Q2
C1
C1c
Adder Stage 1
C1
Adder Stage 2
C2
Adder.PPT(10/1/2009)
5.16
C1a
C1b
C1c
C0a
C0a
C0b
C0c
C0
C0
C0b
C1a
C1b
C1c
C0c
P1
Q1
P0
Q0
Q2
C2a
C0a
C0c
C0b
C1a
C1b
C2b
C2c
C1c
C1
P2
C1
Adder Stage 0
Adder Stage 1
Adder Stage 2
Adder.PPT(10/1/2009)
5.17
Even stages:
Q
CIa,b,c
COa,b,c
Delays:
P,Q,CI S
P,Q,CI C
3
1
Odd stages:
Delays:
P,Q S
P,Q C
CI S
CI C
5
2
4
1
COa,b,c
CIa,b,c
Adder.PPT(10/1/2009)
5.18
P0
P1
P
S
Q0
S0
Q1
C1
CI
C0
C0
S1
Q2
Q
CI
P1
P0
P2
C0
C
2
1
C1
P3
P
S
S2
Q3
Q
CI
C2
C1
C1
P
S
Q
C3
CI
C2
C1
C2
C
4
C2
S3
S4
S3
2
S4
Adder.PPT(10/1/2009)
5.19
Carry Inhibit
Carry Propagate
Carry Generate
Adder.PPT(10/1/2009)
5.20
1???
+ 1???
11??
+ 01??
101?
+ 011?
1011
+ 0101
1011
+ 0100 +1
Thus
C3 = CG3 + CP3CG2 + CP3CP2CG1 +
CP3CP2CP1CG0+CP3CP2CP1CP0C1
As before,, we can use CGPn in place
p
of CPn.
Adder.PPT(10/1/2009)
5.21
S0
Q CGP CGP0
C1
CI CG CG0
P1
Q1
S1
Q CGP CGP1
C0
CI CG CG1
P2
S2
Q2
Q CGP CGP2
C1
CI CG CG2
S3
Q3
Q CGP CGP3
C2
CI CG CG3
Logic
Logic
To later
stages
Logic
P3
C0 = CG0 + CGP0C11
C1 = CG1 + CGP1CG0 + CGP1CGP0C1
C2 = CG2 + CGP2CG1 + CGP2CGP1CG0 +
CGP2CGP1CGP0C1
Adder.PPT(10/1/2009)
5.22
CG0
To 8
logic
blocks
Adder.PPT(10/1/2009)
5.23
Quiz
1 What does it mean to say that a full
1.
full-adder
adder is self-dual
self dual
?
2. How does placing an inverter between each stage of a
multi-bit adder allow the merging of gates in
consecutive stages ?
3. In a 4-bit adder, give an example of a propagation
delay that increases when alternate bits are inverted.
4. Why is a carry-lookahead adder generally
implemented using CGP rather than CP outputs ?
Adder.PPT(10/1/2009)
5.24
Lecture 15
Adder.PPT(10/1/2009)
5.25
P2,Q2
P1,Q1
C1
P4,Q4
P3,Q3
S0
S1
P6,Q6
P5,Q5
S2
S3
P8,Q8
P7,Q7
S4
S5
P10,Q10
P9,Q9
S6
S7
P11,Q11
S8
S9
S10
C11
S11
The worst-case
worst case delay path is from C
C1
1 to S11
S11.
In carry skip, we speed up this path by allowing the carry
signal to skip over several adder stages at a time:
P0,Q0
P2,Q2
P1,Q1
C1
S0
P4,Q4
P3,Q3
S1
S2
P6,Q6
P5,Q5
S3
S4
P8,Q8
P7,Q7
S5
S6
P10,Q10
P9,Q9
S7
P11,Q11
S8
S9
S10
C11
S11
Adder.PPT(10/1/2009)
5.26
P0
P1
P
S
Q0
S0
Q1
C1
CI
P0
C1
C
1
1
C0
P2
P
S
S1
Q2
Q
CI
C0
P1
C0
C0
C
2
1
C1
S
C
Q3
C3
CI
C2
C1
C2
S3
C2
C1
C1
S2
Q
CI
P3
C2
C
4
1
S3
C3
0101
1010
1
10000
C1 C3 = 4 gate delays
0101
1110
1
10100
C11 C3 = 0 gate delays
Adder.PPT(10/1/2009)
5.27
CP0
CP
P0
Q0
S0
Q1
C1
CI
C0
CP
P2
P
S
S1
Q2
Q
C1
CI
CP2
CP
P1
CP1
P
S
C
MUX
P
Q3
C2
CP3
CP
P3
S2
Q
CI
CSK
S3
G1
Q
CI
C3
C
C3X
1
1
P0
P0
C1
2
1
1
CP0
C0
C0
2
P1
C0
2
1
C1
C1
C2
C1
C2
C2
4
1
CSK
S3
C3
C3X
1
C3X
C3X
C1
C3X
Adder.PPT(10/1/2009)
5.28
G1
C3X
C3
C1
CSK
!C3X
0
1
!C3
!C1
CSK
C3
C3
C1
C
1
C1
C
1
C3X
C3
C3X
C1
C1
Adder.PPT(10/1/2009)
5.29
P3:0
P3:0
Q3:0
Q3:0
S3:0
S3:0
C1
CI C3X
P0
C1
5
1
C3
P7:4
P3:0
Q7:4
Q3:0
S7:4
S3:0
CI C3X
P11:8
Q11:8
C7
P15:12
P3:0
P3:0
Q15:12
Q3:0
Q3:0
S11:8
S3:0
S3:0
CI C3X
CI C3X
P12
C3
C3
C11
C3
C7
C7
C11
C11
7
7
S15:12
C15
S15
S15
2N+1
N+3
N+10
6
Adder.PPT(10/1/2009)
5.30
E
F
Y3:0
Z3:0
Adder.PPT(10/1/2009)
5.31
Addition Tree
In practice we use a tree arrangement of adders:
Number of values, K
16
log 2(K)
Adder.PPT(10/1/2009)
5.32
Carry-Save Adder
Take a normal 4-bit adder but dont connect up the
carrys:
P0
Q0
R0
P1
P
S
S0
Q1
Q
CI
C0
R1
P2
P
S
S1
Q2
Q
CI
C1
R2
P
S
C
Q3
C2
We have P+Q+R = 2C + S
S2
Q
CI
P3
P:
Q:
R:
S:
C:
R3
CI
1001
1100
1101
1000
1101_
CS
P
S
Q
R
S3
C3
Adder.PPT(10/1/2009)
5.33
P
S
B
C
CS
P
Q
R
CS
CS
D
S
C
S
2
Q
C
S
2
J
C
A:
B:
C:
G:
H:
1101
1010
0101
0010
1101_
D:
E:
F:
I
I:
J:
1011
1100
0001
0110
1001_
Notes:
1.
2.
3.
4.
G : _0010
2H: 1101_
I: _ 0 1 1 0
K: 11110
L: _0010_
M:
01000
2N: 1011__
X: 0110100
K: 11110
2L: 0010_
2J: 1001_
M : 01000
N: 1011__
Adder.PPT(10/1/2009)
5.34
Carry-Save Tree
We can construct a tree to add sixteen values together:
CS
CS
CS
CS
CS
CS
CS
CS
Number of
values, K
CS
CS
CS
CS
CS
CS
16
13
4
log2(K)
Delay
0
Delay/log2(K)
3.7
3
3.17
6
2.58
9
2
12
1.58
15
1
18
0
24
10
5.65
5.13
5.13
7.23
5.13
Adder.PPT(10/1/2009)
5.35
Merryy Christmas
The End
Adder.PPT(10/1/2009)
5.36
Quiz
1 In a 4
1.
4-bit
bit adder,
adder how can you tell from P0:3 and Q0:3
whether or not C3 is dependent on C1 ?
2. A multiplexer normally has 2 gate delays from its data
inputs to its output. How is this reduced to 1 gate delay
in the carry skip circuit ?
3. If five 4-bit numbers are added together, how many
bits are needed to represent the result ?