Power
Outline
Power and Energy
Dynamic Power
Static Power
7: Power
Energy:
E = P(t )dt
0
Average Power:
7: Power
E 1
Pavg= =
P(t )dt
T T 0
VR2 ( t )
2
P
=
t
=
I
(
)
R
R (t ) R
R
EC
dV
I ( t )V ( t ) dt C V ( t ) dt
0=
dt
0
VC
C=
V ( t )dV
1
2
CVC2
7: Power
Charging a Capacitor
When the gate output rises
Energy stored in capacitor is
2
EC = 12 CLVDD
EVDD
=
I ( t )V dt C
=
DD
dV
VDD dt
dt
VDD
2
= C=
LVDD d V C LVDD
0
Switching Waveforms
Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz
7: Power
Switching Power
T
Pswitching
1
= iDD (t )VDD dt
T 0
T
VDD
=
iDD (t )dt
T 0
VDD
=
[Tfsw CVDD ]
T
= CVDD 2 f sw
VDD
iDD(t)
fsw
7: Power
Activity Factor
Suppose the system clock frequency = f
Let fsw = f, where = activity factor
If the signal is a clock, = 1
If the signal switches once per cycle, =
Dynamic power:
Pswitching = CVDD 2 f
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7: Power
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Solution
6
Clogic =
50
10
27 nF
(
) (12 )( 0.025 m / )(1.8 fF / m ) =
Cmem =
171 nF
( 950 106 ) ( 4 )( 0.025 m / )(1.8 fF / m ) =
0.1Clogic + 0.02Cmem (1.0 ) (1.0 GHz ) =
Pdynamic =
6.1 W
2
7: Power
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CV
switching
DD f
Try to minimize:
Activity factor
Capacitance
Supply voltage
Frequency
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Switching Probability
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Example
A 4-input AND is built out of two levels of gates
Estimate the activity factor at each node if the inputs
have P = 0.5
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Clock Gating
The best way to reduce the activity is to turn off the
clock to registers in unused blocks
Saves clock activity ( = 1)
Eliminates all switching activity in the block
Requires determining if block will be used
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Capacitance
Gate capacitance
Fewer stages of logic
Small gate sizes
Wire capacitance
Good floorplanning to keep communicating
blocks close to each other
Drive long wires with inverters or buffers rather
than complex gates
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Voltage / Frequency
Run each block at the lowest possible voltage and
frequency that meets performance requirements
Voltage Domains
Provide separate supplies to different blocks
Level converters required when crossing
from low to high VDD domains
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Static Power
Static power is consumed even when chip is
quiescent.
Leakage draws power from nominally OFF
devices
Ratioed circuits burn power in fight between ON
transistors
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Solution
Wnormal-Vt =
0.75 106 m
( 50 106 ) (12 )( 0.025 m / )( 0.05) =
Whigh-Vt = ( 50 106 ) (12 )( 0.95 ) + ( 950 106 ) ( 4 ) ( 0.025 m / ) = 109.25 106 m
Wnormal-Vt 100 nA/ m+Whigh-Vt 10 nA/ m / 2 =
I sub =
584 mA
Pstatic =
859 mW
( 584 mA + 275 mA )(1.0 V ) =
7: Power
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Subthreshold Leakage
For Vds > 50 mV
I sub I off 10
7: Power
Typical values in 65 nm
Ioff = 100 nA/m @ Vt = 0.3 V
Ioff = 10 nA/m @ Vt = 0.4 V
Ioff = 1 nA/m @ Vt = 0.5 V
= 0.1
k = 0.1
S = 100 mV/decade
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Stack Effect
Series OFF transistors have less leakage
Vx > 0, so N2 has negative Vgs
Vx + ( (VDD Vx ) VDD ) k Vx
(Vx VDD )
S
S
=
I sub I=
I off 10
off 10
N2
Vx =
N1
VDD
1 + 2 + k
=
I sub I off 10
1+ + k
VDD
1+ 2 + k
I off 10
VDD
S
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Leakage Control
Leakage and delay trade off
Aim for low leakage in sleep and low delay in
active mode
To reduce leakage:
Increase Vt: multiple Vt
Use low Vt only in critical circuits
Increase Vs: stack effect
Input vector control in sleep
Decrease Vb
Reverse body bias in sleep
Or forward body bias in active mode
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Gate Leakage
Extremely strong function of tox and Vgs
Negligible for older processes
Approaches subthreshold leakage at 65 nm and
below in some processes
An order of magnitude less for pMOS than nMOS
Control leakage in the process using tox > 10.5
High-k gate dielectrics help
Some processes provide multiple tox
e.g. thicker oxide for 3.3 V I/O transistors
Control leakage in circuits by limiting VDD
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Junction Leakage
From reverse-biased p-n junctions
Between diffusion and substrate or well
Ordinary diode leakage is negligible
Band-to-band tunneling (BTBT) can be significant
Especially in high-Vt transistors where other
leakage is small
Worst at Vdb = VDD
Gate-induced drain leakage (GIDL) exacerbates
Worst for Vgd = -VDD (or more negative)
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Power Gating
Turn OFF power to blocks when they are idle to
save leakage
Use virtual VDD (VDDV)
Gate outputs to prevent
invalid logic levels to next block
Voltage drop across sleep transistor degrades
performance during normal operation
Size the transistor wide enough to minimize
impact
Switching wide sleep transistor costs dynamic power
Only justified when circuit sleeps long enough
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