ISHIK UNIVERSITY

Faculty of : ENGINEERING.
Department of : COMPUTER
ENGINEERING
Course:LOGIC DESIGN
..........Code: CMPE 331
Semester :First
Semester..

Date :..
Duration :2
hours
Type of Exam:Quiz Mid-Term
Exam
Final Exam Make-up Exam
App.2

Group

Full Name:

Instructions:
-Exam is over % 40.
-Unless not defined within the question, answer all.
-Unreadable answers will not be graded. Write your answers in detailed
and clear way.
-The names of signals should be used at gate inputs and outputs.
Remember to READ the questions carefully! GOOD LUCK

PART A - QUESTIONS
1. Answer two only:
(4 pts)
a. Convert 9E.C16 to octal system
b. Calculate 37 + (-23) using 2s complement method (use 8
bits)
c. Multiply 10011 x 1010
2. Answer both a and b.
(4 pts)
a. Draw the XNOR gate and write its truth table. When this gate
is useful?
b. Simplify the given expression using Boolean Algebra and De
Morgan rules. (show all steps clearly.)

Z ( A.D B.C ) ( A.B C ) B.D

3. Answer both a and b.
(4 pts)
a. Find output function G for the logic circuit shown: (Indicate
output expression at points 1,2,3)

b. Draw the logic circuit for the function F. (without

simplification):
F= xyz + (x+z) + (x+y)
4. Answer only one ( a or b ). A circuit has four inputs and two outputs.
The inputs, A,B,C,D represent decimal numbers from 0 to 15. Design
truth table, k-map, and simplified Boolean equation for only one of
the case below and sketch the logic circuit. (So you design a special
arithmetic logic function to be used)
(7 pts)
a. Output E should be TRUE if the number is >7 and <=11.

InstructorsName :

Signature :

ISHIK UNIVERSITY
Faculty of : ENGINEERING.
Department of : COMPUTER
ENGINEERING
Course:LOGIC DESIGN
..........Code: CMPE 331
Semester :First
Semester..

Date :..
Duration :2
hours
Type of Exam:Quiz Mid-Term
Exam
Final Exam Make-up Exam
App.2

b. Output D should be
TRUE if the
Group
number is divisible by 5.
5. Design a 6:1 encoder. (Show all details: block figure, truth table
etc.)
(7 pts)
6. Determine the Boolean function implemented by the 8 x 1
multiplexer given below? Write the output function using the SOP
terms.
(6 pts)

Selection Lines are A,

B, C. (S2, S1, S0
respectively). The
multiplexer will direct
selected input line to
the output.

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C D
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1

PART B TEST (each q. 2 pts)

1. If the inputs to a full adder are A=1, B=0, CIN=1 what will be the
logic states on the outputs S and COUT?

a) S=0 COUT=1
c) S=1 COUT=1

b) S=0 COUT=0
d) S=1 COUT=0

2. What type of circuit is illustrated in to Fig 1?

a) Data Selector
c) Equality Comparator

b) Full Adder
d) Demultiplexer

3. Refer to Fig.2, If S1=1 and S2= 0 what will be the logic state at the
output X?

a) X = C
c) X = A

b) X = D
d) X = B

4. Refer to Fig 3. If A = 0 and B = 1, what will be the logic states at X,

Y and Z?

a) X=1, Y=1, Z=0

c) X=0, Y=1, Z=0

InstructorsName :

b) X=1, Y=0, Z=0

d) X=0, Y=0, Z=1

Signature :

ISHIK UNIVERSITY
Faculty of : ENGINEERING.
Department of : COMPUTER
ENGINEERING
Course:LOGIC DESIGN
..........Code: CMPE 331
Semester :First
Semester..

Date :..
Duration :2
hours
Type of Exam:Quiz Mid-Term
Exam
Final Exam Make-up Exam
App.2

END OF QUESTIONS Group

InstructorsName :

Signature :