Alcatel Omnipcx 4400: Section XX Cpu3 (Step2-Step3) Board

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Alcatel OmniPCX 4400
SECTION xx
CPU3 (step2-step3) board
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Section xx - CPU3 (step2-step3) board

SUMMARY
CPU3 board (step2 - step3)

Operation .......................................................................................................
1. Presentation..........................................................................................
2. Environment..........................................................................................
3. General operating principles ...............................................................
4. Functional blocks ..................................................................................
Configuration..................................................................................................
1. CPU3 step 2 board ................................................................................
2. CPU3 step 3 board ................................................................................
3. Meaning of the LED...............................................................................
Connection ......................................................................................................
1. Connection ............................................................................................
2. Output pins ...........................................................................................
OBCA board
Operation .......................................................................................................
1. Presentation..........................................................................................
2. Environment..........................................................................................
3. General principle of operation.............................................................
VMU-OBCA board
Operation .......................................................................................................
1. Presentation..........................................................................................
2. Environment..........................................................................................
3. General principe of operation..............................................................
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Ref.3BA19919ENAA
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xx. 3
xx. 3
xx. 4
xx. 5
xx.11
xx.11
xx.13
xx.15
xx.17
xx.17
xx.18
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xx.23
xx.24
xx.25
xx.26
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xx.29
xx.30
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Ed.02
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Operation
44A03222123A100AAEN

Operation
Edition: 02
1.
Presentation
The CPU3 board (step 2 or step 3) is the heart of the system. It generates the clock signals and processes the system applications (atelephone, telematics, messaging applications, etc.). It is used to
download the flash EPROMs of each of the systems boards. It permits connection of an external music
on-hold and a voice service and provides four V24 channels, an SCSI bus (step 2 only), an on-board
backplane Ethernet access and a direct 10base T access.
A second CPU3 board (optional) (same step) can be installed to back up the first board. A backplane
signal (depending on the position) specifies, on system power up, the master or slave function of each
CPU3 (step 2 or 3) board. Switch-over takes place in the event of faulty clock signals.
The following daughter boards (optionnal) can be installed on the CPU3 board (step 2 or 3):
- OBCA: 64kbit/s access (seemodule VMU-OBCA board - Operation ),
- VMU-OBCA: voice mail + 64kbit/s access (seemodule VMU-OBCA board - Operation ).
The CPU3 board (step 2 or 3) configuration is described in module CPU3 board (step2 - step3) Configuration .
The CPU3 board (step 2 or 3) connection is described in module CPU3 board (step2 - step3) - Connection .
2.
Environment
2.1.
Position in the rack
The CPU3 (step 2 or 3) is connected to the other system boards via the I/O controller which integrates
a C1 to establish the type 1 links wityh the 27 other system boards.
The CPU3 board (step 2 or 3) can be connected to the following, on the front side :
- the IO2 board, via ATB2 connection interface board,
- the IO2N board, via ISAB2 connection interface board.
The CPU3 (step 2 or 3) has a predefined position according to the type of ACT.
Ed.02
Ref.3BA19919ENAA
xx.3
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Operation
2.2.
Inputs/outputs
Figure 1 : CPU3 (step2-step3) board inputs/outputs diagram
10 base T port, AUI
Ethernet interface
Embedded Ethernet link

TYPE 1 links
T1 to T28
TYPE 1 links
R1 to R28
I/O controller
Master/slave
Alarm
Network line forwarding
External music on hold

Voice service
B bus
CPU
Floppy
SCSI bus (step 2)
Remote reset
4 V24 links
512kHz external
reference clock
256kHz converter
synchronisation
Rectifier alarm
DEM1 to 5
-48V
0V48
3.
System
clocks
Power supply
16MHz system clocks

8kHz frame synchronisation
On/Off
General operating principles
In case of failure of the main (master) CPU3 (Step 2 or 3) board, a backup (slave) CPU3 (same step)
board will take over. The backplane master/slave signal specifies to each CPU (according to its position) the master (-48V) or slave (0V48) function on initialisation. During normal operation, the master
CPU considers the slave CPU as an interface board. The CPUs communicate via the 256 kbit/s channel of the type 1 link. The CPU in stand-by monitors the backplane generated clocks of the active CPU.
In case of master CPU reset (resulting in loss of clocks) or clock failure, switch over will take place and
the slave CPU will become master CPU.
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4.
Functional blocks
4.1.
LIST

Operation
The CPU3 (step 2 or 3) is made up of the following blocks:

- control unit,
- I/O controller integrating clock and tone generation,
- Ethernet, SCSI (step 2 only) and V24 interfaces,
- power supply block.
Ed.02
Ref.3BA19919ENAA
xx.5
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Operation
Figure 2 : CPU3 (step2 or step3) board functional summary diagram

Front
panel
Backplane
Ethernet LED
Processor
LED
2 asynchronous
V24 (A/B)
802.3 ports
80386EX
(10 base T)
ETHERNET
interface
Embedded
Ethernet link
DRAM
NAR6
Bus interface
2xV24
interfaces
2 asynchronous
Disk drive
controller
Disk drive
ISA
ATB2
SCSI bus
SCSI
Daughter
board
ISAB2
V24 (C/D)
(step 2 only)
EPROM
Bus inter
face
Bus interface
Protection key
Hard
disk
Music on
hold
External
music
on hold
C1
T1/ R1
to
T28/R28
B bus
B bus
Bus interface
Processor
IO2
IO2N
PCM E
Voice mail
interface
PCM R
HB, SYNC
Shared
RAM
512 kHz
8 kHz
256 kHz
16 MHZ
ASIC
VIVALDI
Shared
FLASH
EPROM flash
On/Off
xx.6
+5V
+12V
Ref.3BA19919ENAA
JTAG
CM2 converter
JTAG
256 kHz
-48V
Ed.02
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4.2.

Operation
Blocks description
4.2.1. Control unit

This is a PC-AT platform organized around an 80386 EX-33 microprocessor. It comprises the following
elements:
- microprocessor,
- dynamic memory,
- ASIC NAR6.
Microprocessor
The microprocessor is a 32-bit 80386 EX-33 de 32bits integrating a parallel bus controller, clock
controller, watchdog, serial asynchronous I/O unit (2 V24, COM A and COM B).
DRAM
The DRAM has a maximum capacity of 64 MB (memory modules).
ASIC NAR6
The NAR6 works directly on the picroprocessor bus. It supports the following system functions:
- DRAM controller,
- bus interface management (ISA, IDE, I/O),
- real time clock (calendar),
- JTAG functionality.
4.2.2. I/O controller
The I/O controller is made up of the following parts:
- C1 circuit,
- processor,
- clock and tone module,
- shared memory,
- voice service interface,
- external music interface.
C1 circuit
This component handles the I/Os for the CPU3 (Step 2 or 3) board. It is connected to the other system
boards via type 1 backplane links and carries out the following functions:
- distribution of music on hold and multi-frequencies to the interface boards,
- extraction of the four signalling TSs from each type 1 link and transmission to the control unit,
Ed.02
Ref.3BA19919ENAA
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Operation
- exchange on type 1 links of voice channels with the other couplers,

- injection of the signalling from the CPU3 (Step 2 or 3) on the four type 1 link TSs destined for
an interface board.
Processor
This 80C188 type processor controls the C1 circuit, FLASH memory programming and activation of the
common part processor LED. In case of system failure (PSAL rectifier alarm or watch dog), it generates
two signals:
- the network line forwarding signal controls the forwarding relays installed on the MDF. This
forwards the network lines directly to the back-up telephone stations,
- the alarm signal informs the exterior that the system is no longer operational.
Clocks and tones module
Most peripherals are integrated in a VIVALDI ASIC. This carries out:
- clock generator.
Clock signals are generated for the whole system:
16 MHz system clocks (16M1 and 16M2),
8 KHz frame sync (8K1 and 8K2),
converter synchronisation (256 KHz).
Clocks 16M2 and 8K2 only service the lower shelf in the 28 position backplane.
This module can be synchronised by a 512 KHz reference clock signal from the public network via
a T2, PCM or T0 interface board or a DECT board.
The clocks sent on the system are generated from the external clock or else by a local oscillator
(16.384 MHz not slaved). VIVALDI ensures the selection.
- tone generator.
The frequencies are generated from samples stored in a FLASH EPROM, which is programmed via
the VIVALDI component. The tones and multi-frequencies used by the system interface boards are
MFQ23 type (16 frequencies), ringing frequency (50 Hz), TL frequency (50 Hz), modem frequency
(2100 Hz) as well as the tones specific to each country (Dial tone, send tone, etc.).
- watchdog function.
Voice mail interface (optional)
This module is an optional daughter board (MICROPAC interface). It interfaces with the Alcatel 4630
voice messaging system.
Shared memory
This 256 kB memory can be accessed for read/write by the 80C188 processor and 80386 EX platform
via the ISA bus. Memory access is controlled by an arbitrator.
Music on hold interface
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Operation
This module interfaces with an external music on hold . This music is then distributed to the system
boards via type 1 links.
4.2.3. Interfaces
Ethernet interface
This interface is used for connection to an Ethernet network (connection to a server, etc.) via a connection box. The accesses available are:
- 802.3 link implemented in the circuit (on-board Ethernet link) which distributes to the ECX1 board,
- 10 Base T AUI type interface. When this interface is in service, the 10 Base T LED on the front
panel is on.
SCSI controller (step 2 only)
This interfaces with the ISA bus and offers an SCSI port for data transfer to the circuits on a parallel
I/O bus (SCSI peripheral installed on an MMS board, for example).
Floppy interface
The floppy controller is 82078 (step 2) or PC 8477B (step 3) type. The connection to the floppy is by
cable via the backplane.
V24 interfaces
Two V24 channels (COMC and COMD) are handled by a DUART (Dual Universal Asynchronous Receiver/Transmitter).
Hard disk
The IDE standard hard disk with integrated controller has a minimum capacity of 350 MB.
Protection key
A key, protecting the software is plugged into a support.
4.2.4. Power supply
This is controlled by a power switch. The CM2 converter supplies the +5V/5A and +12V/60mA voltages required for board operation. An alarm signal (rectifier alarm) informs the control unit of rectifier
failure, thus allowing hard disk update before cut-off.
The "On/Off" signal is used to simultaneously start-up/cut-off the power supply to the CPU board and
the other boards connected on the CPU bus so that the bus interface circuits are not damaged.
Ed.02
Ref.3BA19919ENAA
xx.9
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Operation
xx.10
Ref.3BA19919ENAA
Ed.02
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Configuration
44A03222123A020AAEN

Configuration
Edition: 02
1.
CPU3 step 2 board
1.1.
Reference
CPU3 step 2 board: 3BA 57162 AB / 3BA 57162 BB (USA).

1.2.
Presentation
The diagram below gives the position and number for each strap present on the CPU3 step 2 board.
Ed.02
Ref.3BA19919ENAA
xx.11
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Configuration
Figure 3 : View of the CPU3 step 2 board
H1
X54
X55
X26
H2
X24
X25
connecteur
micropac
1.3.
Strappings
Ex-factory strappings are shown on a grey background.
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Ref.3BA19919ENAA
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Configuration
Loop closed
Alarm relay
X54
X54
X55
X55
X26
X26
33 KOhms in the loop

Alarm loop
2.
CPU3 step 3 board
2.1.
Reference
Loop open
X24
33 KOhms short-circuited
X25
X24
X25
CPU3 step 3 board: 3BA 57162 NA / 3BA 57162 MA (USA).

2.2.
Presentation
The diagram below gives the position and number for each strap present on the CPU3 step 3 board.
Ed.02
Ref.3BA19919ENAA
xx.13
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Configuration
Figure 4 : View of the CPU3 step 3 board
H1
H2
X25
X24
X26
connecteur
Micropac
2.3.
Strappings
Ex-factory strappings are shown on a grey background.
xx.14
Ref.3BA19919ENAA
Ed.02
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Configuration
Loop closed
Alarm relay
X25
X25
33 KOhms in loop
Alarm loop
Loop open
33 KOhms short-circuited
X24
X24
Music on hold
A law
Board: 3BA 57162 NA
Board: 3BA 57162 MA (USA)
3.
Meaning of the LED
3.1.
Display
law
X26
X26
X26
X26
The CPU3 (step 2 or step 3) board has 2 LED located on the front panel.
Ed.02
Ref.3BA19919ENAA
xx.15
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Configuration
Figure 5 : CPU3 (step 2 or step 3) board front panel
CPU3
CPU
ETH
3.2.
Meaning
Table 1 : Summary
LED
Meaning
CPU (Green LED)
CPU activity indicator
ETH (Orange LED)
Ethernet link activity indicator
3.3.
Cadencing
Table 2 : CPU LED

Cadencing
Meaning
ON fixed
Initialization in progress
100 ms (ON)/ 1s (OFF)
Loading in progress
10 ms (ON)/ 10 ms (OFF)
Re-flashing boot
300 ms (ON)/ 300 ms (OFF)
CPU wait
8 x (900 ms (ON)/ 600 ms (OFF))/1 s (OFF)
RAM Test error
8 x (300 ms (ON)/ 600 ms (OFF))/1 s (OFF)
Checksum error
xx.16
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Ed.02
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Connection
44A03222123A030AAEN

Connection
Edition: 02
1.
Connection
The CPU3 (step 2 or 3) board must be installed in a CPU slot of the main ACT.
The CPU positions depend on the type of ACT (see the related cabinet installation documentation).
Daughter boards connection to CPU3 step 2-3
Figure 6 : Connection diagram
Memory modules
Hard kee
CPU3 board
OBCA board
(option)
Hard disk
VMU-OBCA board
(option)
The CPU3 connection to external components depends on the type of ACT:

- M2 or M3 cabinet, see module M2/M3 cabinet - Internal connections ,
- VH rack, see module VH rack - Internal connections ,
- WM1 rack, see module WM1 Rack - Internal connections .
Ed.02
Ref.3BA19919ENAA
xx.17
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Connection
2.
Output pins
2.1.
CPU3 step 2 board
The output pins of the CPU3 board step 2 are shown below:
C
REMARKS
RXDA
RIA
TXDA
CTSA
GND
RTSA
TXDi, RXDi, RTSi,

CTSi, DTRi, DSRi,
DCDi, RIi = output
wires for the V24 A
and B
DSRA
DCDA
DTRA
RIB
DCDB
GND
RXDB
DSRB
GND
CTSB
DTRB
RTSB
TXDB
GND
GND
RESEXT1 = used to
reset by applying
12 V for 10 ms
GND
GND
(*)
(*)see CPU5
TR2
GND
TR1
CTSC, RTSC, RXDC,

TXDC = port C
(PIOC board)
10
CTSC
RESEXT1
RTSC
11
RXDC
RL1
TXDC
12
MICRN
RL2
MICRP
13
MICEN
AL1
MICEP
14
SYNCP
AL2
SYNCN
15
CLKP
GND
CLKN
16
SCSI_DPPN
GND
SCSI_D0N
xx.18
Ref.3BA19919ENAA
TR1, TR2 = wires for

the external music
on hold
MICEN, MICRN,
MICEP, MICRP,
SYNCN, SYNCP,
CLKN, CLKP =
wires for the 4630
voice service
RL1, RL2 =
command for
external line
forwarding
AL1, AL2 = alarm
wires
Ed.02
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Connection
17
TPI_RXP
SCSI_D7N
SCSI_D1N
18
TPI_RXN
SCSI_D6N
SCSI_D2N
19
SCSI_SELN
TPI_TXP
SCSI_D3N
20
GND (*)
TPI_TXN
SCSI_D4N
21
SCSI_ACKN
GND
SCSI_D5N
22
CTSD
RESEXT2
RTSD
23
RXDD
GND
TXDD
24
SCSI_BSYN
GND
SCSI_ATNN
25
INDX
GND
ME0
26
ME1
SCSI_RSTN
DS0
27
DS1
SCSI_CDN
DIR
28
STEP
SCSI_ION
WRDATA
29
WE
5V
TRK0
30
WP
GND
RDDATA
31
HDSEL
GND
DSKCHG
32
SCSI_REQN
GND
TERMPWR
2.2.
REMARKS
SCSI_xxx, TERMPWR
= for the SCSI
interface
TPI_RXP, TPI_RXN,
TPI_TXP, TPI_TXN =
for Ethernet in 10
baseT
RESEXT2 = Not
connected
CTSD, RTSD, RXDD,
TXDD = port D
(PIOC board)
INDX, ME0, ME1,

DS0, DS1, DIR,
STEP WRDATA,
WE, 5V, TRK0, WP,
RDDATA, HDSEL,
DSKCHG = wires
for the disk drive
CPU3 step 3 board
The output pins of the CPU3 board step 3 are shown below:
C
REMARQUES
RXDA
RIA
TXDA
CTSA
GND
RTSA
TXDi, RXDi, RTSi, CTSi, DTRi,

DSRi, DCDi, RIi = output
wires for the V24 A and B
DSRA
DCDA
DTRA
Ed.02
Ref.3BA19919ENAA
xx.19
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Connection
REMARQUES
RIB
DCDB
GND
TR1, TR2 =wires for the

external music on hold
RXDB
DSRB
GND
CTSB
DTRB
RTSB
TXDB
GND
GND
RESEXT1 = used to reset by

applying 12 V current for 10
ms
GND
GND
(*)
(*) see CPU5
TR2
GND
TR1
CTSC, RTSC, RXDC, TXDC =

port C (PIOC board)
10
CTSC
RESEXT1
RTSC
11
RXDC
RL1
TXDC
12
MICRN
RL2
MICRP
13
MICEN
AL1
MICEP
14
SYNCP
AL2
SYNCN
15
CLKP
GND
CLKN
16
GND
17
TPI_RXP
18
TPI_RXN
19
20
21
RL1, RL2 = command for

external line forwarding
AL1, AL2 = alarm wires
TPI_RXP, TPI_RXN, TPI_TXP,
TPI_TXN = for Ethernet in 10
baseT
TPI_TXP
GND (*)
MICEN, MICRN, MICEP,

MICRP, SYNCN, SYNCP,
CLKN, CLKP = wires for the
Alcatel 4630 voice services
TPI_TXN
GND
22
CTSD
RESEXT2
RTSD
23
RXDD
GND
TXDD
RESEXT2 = Not connected
ME0
CTSD, RTSD, RXDD, TXDD =

port D (PIOC board)
24
GND
25
INDX
26
ME1
DS0
27
DS1
DIR
xx.20
GND
Ref.3BA19919ENAA
Ed.02
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Connection
REMARQUES
WRDATA
INDX, ME0, ME1, DS0, DS1,

DIR, STEP WRDATA, WE, 5V,
TRK0, WP, RDDATA, HDSEL,
DSKCHG = wires for the disk
drive
28
STEP
29
WE
5V
TRK0
30
WP
GND
RDDATA
31
HDSEL
GND
DSKCHG
32
Ed.02
GND
Ref.3BA19919ENAA
xx.21
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Connection
xx.22
Ref.3BA19919ENAA
Ed.02
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OBCA board
Operation
44A03222503A100AAEN
OBCA board
Operation
Edition: 01a
1.
Presentation
The OBCA (Optimised B-channel CPU Access) board is a daughter board supporting 3 B channels at
64 kbit/s.
It offers:
-
remote access to the system (management, download),
- access to terminals for internal applications.

OBCA board reference : 3BA 23099 AA .
The OBCA board is a board not requiring configuration.
It is installed on a CPU3 (step 2 or 3) board (see module CPU3 board (step2 - step3) - Connection ) or
CPU5 board (see module CPU5 step2 board - Connection or module CPU5 step3 board - Connection
).
Ed.02
Ref.3BA19919ENAA
xx.23
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OBCA board
Operation
2.
Environment
2.1.
Functional environment
Figure 7 : Integration of the OBCA board in the ACT architecture.
CPU board
CPU
ISA bus
Appli
cations
Application
terminal
OBCA
IPCM2
C1
V24
TA
Terminal adapter
with protocol V120
UA
BPRA
T0/T2
Remote access
Network
2.2.
The OBCA board, installed on a CPU motherboard, is connected to the IPCM2 of the board C1 component.
The exchanges between the two boards are carried out via the ISA (Industry Standard Architecture) bus.
xx.24
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Ed.02
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2.3.
OBCA board
Operation
Inputs/outputs
Figure 8 : OBCA board inputs/outputs diagram
CPU
IPCM2 input
Physical interface
IPCM2 output
Synchros
Communication
control
ISA interface
+5V
3.
ISA bus
Power supply
General principle of operation
The OBCA board is a daughter board for CPU3 and CPU5 boards. It offers connection oriented full
duplex links between the CPU and the external entities. These links allow dialogs with character or
packet mode applications. This board can handle up to three channels B in HDLC mode. The OBCA
board can handle the following proocols: Q922, LAPD, LAPB, V120 synchronous and asynchronous.
The OBCA board only provides Frame Relay operation (D overflow into B) on the end nodes.
The OBCA board can handle several data links multiplexed on one physical channel. It can therefore
process up to 30 concurrent data links. It is not equipped with any circuit C1,thus it cannot handle
packet switching nor frame relay.
OBCA and IO2 boards can be fitted together on the same CPU. In this way, the amount of channels
B which can be operated concurrently is 33. However, the max. amount of channels B which can be
operated in packet or character mode remains at 30.
Ed.02
Ref.3BA19919ENAA
xx.25
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T E L

OBCA board
Operation
4.
Functional blocks
4.1.
List
The OBCA daughter board is made up of different blocks:

- CPU,
- physical interface,
- communication control,
- ISA interface,
- power supply.
xx.26
Ref.3BA19919ENAA
Ed.02
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OBCA board
Operation
Figure 9 : OBCA board functional summary diagram

FRONT
PANEL
BACKPLANE
CPU motherboard
Physical
interface
IPCM2
TS
allocation
Synchros
CPU
Memory
Register
Arbitrator
ISA
interface
ISA bus
Shared
memory
+5V
OBCA board
256 kHz
+5V
Ed.02
Converter
Ref.3BA19919ENAA
-48V
xx.27
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OBCA board
Operation
4.2.
Blocks description
4.2.1. CPU
The CPU part, with its architecture organised around a 68302 microcontroller, handles the following
functions:
- management of the OBCA board,
- management of the physical interface with the motherboard,
- management of communications control.
There is no manual reset on the OBCA board (this function is carried out by the CPU motherboard).
4.2.2. Physical interface
The physical interface is connected to the Internal 2 PCM of the mother CPU board. The synchronisations (4 MHz clock signal and 8 kHz frame sync signal) from the C1 component drive the OBCA board.
4.2.3. Communication control
The communications are carried out on 3 independent serial controllers. The 3 PCM channels of the
IPCM2 are assigned as follows: TS1 = channel 1, TS2 = channel 2 and TS3 = channel 3.
4.2.4. ISA interface
The ISA interface handles the exchanges between the OBCA board and the mother CPU board via the
ISA bus. It allows the motherboard to access the shared memory, board register and CPU memory
(download, maintenance functions).
The OBCA board is considered as an ISA bus peripheral.
4.2.5. Power supply
The board power supply is delivered from the converter located on the motherboard. Only the +5V is
required.
xx.28
Ref.3BA19919ENAA
Ed.02
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T E L

VMU-OBCA board
Operation
44A03222513A100AAEN
VMU-OBCA board
Operation
Edition: 01a
1.
Presentation
The VMU-OBCA board is a daughter board which is composed of 2 parts:

- a VMU (Voice Mail Unit) voice mail part which has 4 accesses (Alcatel 4615 voice mail),
- an OBCA (Optimized B-channel CPU Access) part which supports 3 64 kbit/s B channels.
The VMU-OBCA is a board not requiring configuration.
VMU-OBCA board reference: 3BA 53176 AA .
It must be installed only on a CPU3 step 2 or 3 motherboard (see module CPU3 board (step2 - step3)
- Connection ).
Ed.02
Ref.3BA19919ENAA
xx.29
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VMU-OBCA board
Operation
2.
Environment
2.1.
Functional environment
CPU
VMU/
OBCA
ISA bus
Mother board
Voice mail
management
terminal
C1
V24
Z
TA
UA
UA
Set with voice

mail system
BPRA
T0/T2
Remote access
Network
2.2.
The VMU-OBCA board, installed on a CPU motherboard, is connected to the IPCM2 of the board C1
component.
The exchanges between the CPU3 and VMU-OBCA boards are conducted via the ISA bus.
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Ed.02
A L C
T E L

2.3.
VMU-OBCA board
Operation
Inputs/outputs
Figure 10 : VMU-OBCA board environment
OBCA
Communication
control
PCM2
ISA bus
System
interface
Synchros
VMU-OBCA
PCM2
CLK4M
System
interface
Physical interface
and ISA interface
FSY28
PCM0
PCM0
VMU
+5V
Power supply
The system interface is composed of PCM links and synchronisation signals.
3.
General principe of operation
The 2 VMU and OBCA parts integrate the following functions:

- ISA Bus Interface,
- shared FPGA (Field Programmable Gate Array) for the ISA (Industry Standard Architecture) Bus
interface command.
The VMU part has the following features:
- 2x64 Kwords DSP data memory,
- 512 Kwords of code memory,
Ed.02
Ref.3BA19919ENAA
xx.31
A L C
T E L

VMU-OBCA board
Operation
- 128 Mbits of FLASH NAND storage.

The OBCA part has the following features:
- MC68302 processor,
- 64 Kwords of code memory,
- 64 Kwords of shared memory.
4.
Functional blocks
4.1.
List
The VMU-OBCA daughter board is constitued of the following parts:

- OBCA module,
- VMU module,
- power supply.
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Ref.3BA19919ENAA
Ed.02
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T E L

VMU-OBCA board
Operation
Figure 11 : VMU-OBCA board functional summary diagram

FRONT
PANEL
BACKPLANE
CPU mother board

VMU/OBCA daughter
board
Physical
interface
MICI2
CPU
Memory
TS assign
ment
Synchros
Register
Arbitra
tor
ISA
interface
Bus ISA
Shared
memory
OBCA part
VMU part
EPROM
Nand
Main DSP
SRAM
+5V
SRAM
Slave DSP
Logic
Reset
CPLD
256 kHz
-48V
Convertor
+5V
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Ref.3BA19919ENAA
xx.33
A L C
T E L

VMU-OBCA board
Operation
4.2.
Blocks description
4.2.1. OBCA module

See OBCA board (voir module OBCA board - Operation ).
4.2.2. VMU module
The Voice mail module (VMU) has 4 voice accesses, up to 128 voice mailboxes and 340 minutes of
speech storage (maximum 4 minutes per message).
VMU interface
The host interface of the slave DSP is used for all the exchanges with the CPU, including the start-up of
each DSP. All the signalling messages are transferred from the slave DSP to the main DSP via the SSI
0 interface.
The host interface of the slave DSP is accessed via a logic applied to the CPLD (Complex Programmable
Logic Device).
The logic provides functional accesses, including the time conditions between the ISA-BUS interface
and the host interface of the slave DSP.
The quick interrupt of the slave DSP is used for both transfer directions between the CPU and the slave
DSP. The interrupt vector of the Host Receiver and the Host Emitter may be written as a move instruction
instead of a hop instruction. The DSP will insert this instruction in the normal execution of a waiting
queue without deleting this queue.
The slave DSP must never inhibit the interrrupts for a duration greater than a word read access cycle
or 2 bytes of the Host interface.
Reset circuit
After a CPU hardware reset, the VMU part must be reset. The reset may be removed from the VMU
part of the CPU software. The VMU part may be reset during a shutdown. The reset function applies
to the CPLDs OBCA part.
DSP LLP programming
The DSPs are controlled by the 4 MHz clock of the C1 link. The start-up program must have programming which is suitable for the PLL.
Features of the main DSP
- Start-up by SSI 0 synchronous serial interface,
- Reset and interrupt of the EPROM NAND,
- Communication interrupt,
- Access time request,
- Configuration of the B port bits to control the external hardware,
- Configuration of the C port bits as SSI 0 synchronous serial interface,
- Interface of the signals to the CPLD,
- Data bus connection,
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Ref.3BA19919ENAA
Ed.02
A L C
T E L

VMU-OBCA board
Operation
- Exchange of speech data on TSs 1,2,3 and 4 of PCMI 0 and PCMO 0,

- Use of the SSI 0 synchronous serial interface to transfer the boot codes to the main DSP and
exchange messages with the CPU.
Features of the slave DSP
- Communication interrupt to the main DSP,
- Access time request,
- Configuration of the B port bits to act as a host interface,
- Configuration of the C port bits as SSI 0 synchronous serial interface,
- Exchange of speech data on TSs 1,2,3 and 4 of PCMI 0 and PCMO 0,
- Use of the SSI 0 synchronous serial interface to transfer the boot codes to the main DSP and
exchange messages with the CPU.
4.2.3. Power supply
The converter located on the mother board supplies the board with power. Only +5V will be used.
Ed.02
Ref.3BA19919ENAA
xx.35

Alcatel Omnipcx 4400: Section XX Cpu3 (Step2-Step3) Board

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Alcatel Omnipcx 4400: Section XX Cpu3 (Step2-Step3) Board

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A L C

Alcatel OmniPCX 4400

Alcatel OmniPCX 4400

Section xx - CPU3 (step2-step3) board

CPU3 board (step2 - step3)

Alcatel OmniPCX 4400

Alcatel OmniPCX 4400

CPU3 board (step2 - step3)

CPU3 board (step2 - step3)

Position in the rack

Alcatel OmniPCX 4400

Section xx - CPU3 (step2-step3) board

Embedded Ethernet link

External music on hold

16MHz system clocks

General operating principles

Alcatel OmniPCX 4400

CPU3 board (step2 - step3)

The CPU3 (step 2 or 3) is made up of the following blocks:

Alcatel OmniPCX 4400

Section xx - CPU3 (step2-step3) board

Figure 2 : CPU3 (step2 or step3) board functional summary diagram

Alcatel OmniPCX 4400

CPU3 board (step2 - step3)

4.2.1. Control unit

Alcatel OmniPCX 4400

Section xx - CPU3 (step2-step3) board

- exchange on type 1 links of voice channels with the other couplers,

Alcatel OmniPCX 4400

CPU3 board (step2 - step3)

Alcatel OmniPCX 4400

Section xx - CPU3 (step2-step3) board

Alcatel OmniPCX 4400

CPU3 board (step2 - step3)

CPU3 board (step2 - step3)

CPU3 step 2 board

CPU3 step 2 board: 3BA 57162 AB / 3BA 57162 BB (USA).

Alcatel OmniPCX 4400

Section xx - CPU3 (step2-step3) board

Figure 3 : View of the CPU3 step 2 board

Ex-factory strappings are shown on a grey background.

Alcatel OmniPCX 4400

CPU3 board (step2 - step3)

33 KOhms in the loop

CPU3 step 3 board

CPU3 step 3 board: 3BA 57162 NA / 3BA 57162 MA (USA).

Alcatel OmniPCX 4400

Section xx - CPU3 (step2-step3) board

Figure 4 : View of the CPU3 step 3 board

Ex-factory strappings are shown on a grey background.

Alcatel OmniPCX 4400

CPU3 board (step2 - step3)

Board: 3BA 57162 NA

Board: 3BA 57162 MA (USA)

Meaning of the LED

Alcatel OmniPCX 4400

Section xx - CPU3 (step2-step3) board

Figure 5 : CPU3 (step 2 or step 3) board front panel

CPU (Green LED)

CPU activity indicator

ETH (Orange LED)

Ethernet link activity indicator

Table 2 : CPU LED